| commit | 9aa2126f16daeb8cd3027a70a2629130b0e618d9 | [log] [tgz] |
|---|---|---|
| author | Phil Edworthy <phil.edworthy@renesas.com> | Mon Sep 10 17:02:54 2018 +0100 |
| committer | Simon Horman <horms+renesas@verge.net.au> | Fri Sep 14 15:34:50 2018 +0200 |
| tree | 0698d1e83dd6d5f418d971b0259c532db1c2262d | |
| parent | 1926bd6bf20fe306797fbf366902674d2d6c20cc [diff] |
ARM: dts: r9a06g032: Correct UART and add all other UARTs
- UART0 was missing the bus clock ("apb_pclk").
- Use recently accepted r9a06g032 and rzn1 compat strings.
- Add all the other UARTs.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
[simon: updated changelog]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>