qed*: Refactoring and rearranging FW API with no functional impact
This patch refactors and reorders the FW API files in preparation of
upgrading the code to support new FW.
- Make use of the BIT macro in appropriate places.
- Whitespace changes to align values and code blocks.
- Comments are updated (spelling mistakes, removed if not clear).
- Group together code blocks which are related or deal with similar
matters.
Signed-off-by: Ariel Elior <Ariel.Elior@cavium.com>
Signed-off-by: Michal Kalderon <Michal.Kalderon@cavium.com>
Signed-off-by: Tomer Tayar <Tomer.Tayar@cavium.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
diff --git a/include/linux/qed/common_hsi.h b/include/linux/qed/common_hsi.h
index 39e2a2a..4874c10 100644
--- a/include/linux/qed/common_hsi.h
+++ b/include/linux/qed/common_hsi.h
@@ -32,14 +32,15 @@
#ifndef _COMMON_HSI_H
#define _COMMON_HSI_H
+
#include <linux/types.h>
#include <asm/byteorder.h>
#include <linux/bitops.h>
#include <linux/slab.h>
/* dma_addr_t manip */
-#define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
-#define PTR_HI(x) ((u32)((((uintptr_t)(x)) >> 16) >> 16))
+#define PTR_LO(x) ((u32)(((uintptr_t)(x)) & 0xffffffff))
+#define PTR_HI(x) ((u32)((((uintptr_t)(x)) >> 16) >> 16))
#define DMA_LO_LE(x) cpu_to_le32(lower_32_bits(x))
#define DMA_HI_LE(x) cpu_to_le32(upper_32_bits(x))
#define DMA_REGPAIR_LE(x, val) do { \
@@ -47,39 +48,45 @@
(x).lo = DMA_LO_LE((val)); \
} while (0)
-#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
-#define HILO_64(hi, lo) HILO_GEN((le32_to_cpu(hi)), (le32_to_cpu(lo)), u64)
-#define HILO_64_REGPAIR(regpair) (HILO_64(regpair.hi, regpair.lo))
+#define HILO_GEN(hi, lo, type) ((((type)(hi)) << 32) + (lo))
+#define HILO_64(hi, lo) \
+ HILO_GEN(le32_to_cpu(hi), le32_to_cpu(lo), u64)
+#define HILO_64_REGPAIR(regpair) ({ \
+ typeof(regpair) __regpair = (regpair); \
+ HILO_64(__regpair.hi, __regpair.lo); })
#define HILO_DMA_REGPAIR(regpair) ((dma_addr_t)HILO_64_REGPAIR(regpair))
#ifndef __COMMON_HSI__
#define __COMMON_HSI__
+/********************************/
+/* PROTOCOL COMMON FW CONSTANTS */
+/********************************/
-#define X_FINAL_CLEANUP_AGG_INT 1
+#define X_FINAL_CLEANUP_AGG_INT 1
-#define EVENT_RING_PAGE_SIZE_BYTES 4096
+#define EVENT_RING_PAGE_SIZE_BYTES 4096
-#define NUM_OF_GLOBAL_QUEUES 128
-#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
+#define NUM_OF_GLOBAL_QUEUES 128
+#define COMMON_QUEUE_ENTRY_MAX_BYTE_SIZE 64
-#define ISCSI_CDU_TASK_SEG_TYPE 0
-#define FCOE_CDU_TASK_SEG_TYPE 0
-#define RDMA_CDU_TASK_SEG_TYPE 1
+#define ISCSI_CDU_TASK_SEG_TYPE 0
+#define FCOE_CDU_TASK_SEG_TYPE 0
+#define RDMA_CDU_TASK_SEG_TYPE 1
-#define FW_ASSERT_GENERAL_ATTN_IDX 32
+#define FW_ASSERT_GENERAL_ATTN_IDX 32
-#define MAX_PINNED_CCFC 32
+#define MAX_PINNED_CCFC 32
/* Queue Zone sizes in bytes */
-#define TSTORM_QZONE_SIZE 8
-#define MSTORM_QZONE_SIZE 16
-#define USTORM_QZONE_SIZE 8
-#define XSTORM_QZONE_SIZE 8
-#define YSTORM_QZONE_SIZE 0
-#define PSTORM_QZONE_SIZE 0
+#define TSTORM_QZONE_SIZE 8
+#define MSTORM_QZONE_SIZE 16
+#define USTORM_QZONE_SIZE 8
+#define XSTORM_QZONE_SIZE 8
+#define YSTORM_QZONE_SIZE 0
+#define PSTORM_QZONE_SIZE 0
-#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
+#define MSTORM_VF_ZONE_DEFAULT_SIZE_LOG 7
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DEFAULT 16
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_DOUBLE 48
#define ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD 112
@@ -115,10 +122,10 @@
#define MAX_NUM_PORTS_BB (2)
#define MAX_NUM_PORTS (MAX_NUM_PORTS_K2)
-#define MAX_NUM_PFS_K2 (16)
-#define MAX_NUM_PFS_BB (8)
-#define MAX_NUM_PFS (MAX_NUM_PFS_K2)
-#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
+#define MAX_NUM_PFS_K2 (16)
+#define MAX_NUM_PFS_BB (8)
+#define MAX_NUM_PFS (MAX_NUM_PFS_K2)
+#define MAX_NUM_OF_PFS_IN_CHIP (16) /* On both engines */
#define MAX_NUM_VFS_K2 (192)
#define MAX_NUM_VFS_BB (120)
@@ -147,9 +154,6 @@
#define LB_TC (NUM_OF_PHYS_TCS)
-/* Num of possible traffic priority values */
-#define NUM_OF_PRIO (8)
-
#define MAX_NUM_VOQS_K2 (NUM_TCS_4PORT_K2 * MAX_NUM_PORTS_K2)
#define MAX_NUM_VOQS_BB (NUM_OF_TCS * MAX_NUM_PORTS_BB)
#define MAX_NUM_VOQS (MAX_NUM_VOQS_K2)
@@ -157,13 +161,8 @@
/* CIDs */
#define NUM_OF_CONNECTION_TYPES (8)
-#define NUM_OF_LCIDS (320)
-#define NUM_OF_LTIDS (320)
-
-/* Clock values */
-#define MASTER_CLK_FREQ_E4 (375e6)
-#define STORM_CLK_FREQ_E4 (1000e6)
-#define CLK25M_CLK_FREQ_E4 (25e6)
+#define NUM_OF_LCIDS (320)
+#define NUM_OF_LTIDS (320)
/* Global PXP windows (GTT) */
#define NUM_OF_GTT 19
@@ -172,17 +171,17 @@
#define GTT_DWORD_SIZE BIT(GTT_DWORD_SIZE_BITS)
/* Tools Version */
-#define TOOLS_VERSION 10
+#define TOOLS_VERSION 10
/*****************/
/* CDU CONSTANTS */
/*****************/
-#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
-#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
+#define CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (17)
+#define CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0x1ffff)
-#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
-#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
+#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_TYPE_SHIFT (12)
+#define CDU_VF_FL_SEG_TYPE_OFFSET_REG_OFFSET_MASK (0xfff)
#define CDU_CONTEXT_VALIDATION_CFG_ENABLE_SHIFT (0)
#define CDU_CONTEXT_VALIDATION_CFG_VALIDATION_TYPE_SHIFT (1)
@@ -201,45 +200,45 @@
#define DQ_DEMS_TOE_LOCAL_ADV_WND 4
#define DQ_DEMS_ROCE_CQ_CONS 7
-/* XCM agg val selection */
-#define DQ_XCM_AGG_VAL_SEL_WORD2 0
-#define DQ_XCM_AGG_VAL_SEL_WORD3 1
-#define DQ_XCM_AGG_VAL_SEL_WORD4 2
-#define DQ_XCM_AGG_VAL_SEL_WORD5 3
-#define DQ_XCM_AGG_VAL_SEL_REG3 4
-#define DQ_XCM_AGG_VAL_SEL_REG4 5
-#define DQ_XCM_AGG_VAL_SEL_REG5 6
-#define DQ_XCM_AGG_VAL_SEL_REG6 7
+/* XCM agg val selection (HW) */
+#define DQ_XCM_AGG_VAL_SEL_WORD2 0
+#define DQ_XCM_AGG_VAL_SEL_WORD3 1
+#define DQ_XCM_AGG_VAL_SEL_WORD4 2
+#define DQ_XCM_AGG_VAL_SEL_WORD5 3
+#define DQ_XCM_AGG_VAL_SEL_REG3 4
+#define DQ_XCM_AGG_VAL_SEL_REG4 5
+#define DQ_XCM_AGG_VAL_SEL_REG5 6
+#define DQ_XCM_AGG_VAL_SEL_REG6 7
-/* XCM agg val selection */
-#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
-#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2
-#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
-#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
-#define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
-#define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5
-#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
-#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
-#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
-#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
-#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
-#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
+/* XCM agg val selection (FW) */
+#define DQ_XCM_CORE_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
+#define DQ_XCM_CORE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_CORE_SPQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_ETH_EDPM_NUM_BDS_CMD DQ_XCM_AGG_VAL_SEL_WORD2
+#define DQ_XCM_ETH_TX_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
+#define DQ_XCM_ETH_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_ETH_GO_TO_BD_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD5
+#define DQ_XCM_FCOE_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
+#define DQ_XCM_FCOE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_FCOE_X_FERQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD5
+#define DQ_XCM_ISCSI_SQ_CONS_CMD DQ_XCM_AGG_VAL_SEL_WORD3
+#define DQ_XCM_ISCSI_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_ISCSI_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
+#define DQ_XCM_ISCSI_EXP_STAT_SN_CMD DQ_XCM_AGG_VAL_SEL_REG6
+#define DQ_XCM_ROCE_SQ_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_TOE_TX_BD_PROD_CMD DQ_XCM_AGG_VAL_SEL_WORD4
+#define DQ_XCM_TOE_MORE_TO_SEND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG3
+#define DQ_XCM_TOE_LOCAL_ADV_WND_SEQ_CMD DQ_XCM_AGG_VAL_SEL_REG4
/* UCM agg val selection (HW) */
#define DQ_UCM_AGG_VAL_SEL_WORD0 0
#define DQ_UCM_AGG_VAL_SEL_WORD1 1
#define DQ_UCM_AGG_VAL_SEL_WORD2 2
#define DQ_UCM_AGG_VAL_SEL_WORD3 3
-#define DQ_UCM_AGG_VAL_SEL_REG0 4
-#define DQ_UCM_AGG_VAL_SEL_REG1 5
-#define DQ_UCM_AGG_VAL_SEL_REG2 6
-#define DQ_UCM_AGG_VAL_SEL_REG3 7
+#define DQ_UCM_AGG_VAL_SEL_REG0 4
+#define DQ_UCM_AGG_VAL_SEL_REG1 5
+#define DQ_UCM_AGG_VAL_SEL_REG2 6
+#define DQ_UCM_AGG_VAL_SEL_REG3 7
/* UCM agg val selection (FW) */
#define DQ_UCM_ETH_PMD_TX_CONS_CMD DQ_UCM_AGG_VAL_SEL_WORD2
@@ -263,7 +262,7 @@
#define DQ_TCM_ROCE_RQ_PROD_CMD \
DQ_TCM_AGG_VAL_SEL_WORD0
-/* XCM agg counter flag selection */
+/* XCM agg counter flag selection (HW) */
#define DQ_XCM_AGG_FLG_SHIFT_BIT14 0
#define DQ_XCM_AGG_FLG_SHIFT_BIT15 1
#define DQ_XCM_AGG_FLG_SHIFT_CF12 2
@@ -273,20 +272,20 @@
#define DQ_XCM_AGG_FLG_SHIFT_CF22 6
#define DQ_XCM_AGG_FLG_SHIFT_CF23 7
-/* XCM agg counter flag selection */
-#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
-#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
-#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
-#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
-#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
-#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
-#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
-#define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
-#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
-#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
-#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
-#define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
-#define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
+/* XCM agg counter flag selection (FW) */
+#define DQ_XCM_CORE_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
+#define DQ_XCM_CORE_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
+#define DQ_XCM_CORE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
+#define DQ_XCM_ETH_DQ_CF_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF18)
+#define DQ_XCM_ETH_TERMINATE_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
+#define DQ_XCM_ETH_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
+#define DQ_XCM_ETH_TPH_EN_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
+#define DQ_XCM_FCOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
+#define DQ_XCM_ISCSI_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
+#define DQ_XCM_ISCSI_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
+#define DQ_XCM_ISCSI_PROC_ONLY_CLEANUP_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF23)
+#define DQ_XCM_TOE_DQ_FLUSH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF19)
+#define DQ_XCM_TOE_SLOW_PATH_CMD BIT(DQ_XCM_AGG_FLG_SHIFT_CF22)
/* UCM agg counter flag selection (HW) */
#define DQ_UCM_AGG_FLG_SHIFT_CF0 0
@@ -317,9 +316,9 @@
#define DQ_TCM_AGG_FLG_SHIFT_CF6 6
#define DQ_TCM_AGG_FLG_SHIFT_CF7 7
/* TCM agg counter flag selection (FW) */
-#define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
-#define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2)
-#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
+#define DQ_TCM_FCOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
+#define DQ_TCM_FCOE_DUMMY_TIMER_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF2)
+#define DQ_TCM_FCOE_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
#define DQ_TCM_ISCSI_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
#define DQ_TCM_ISCSI_TIMER_STOP_ALL_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF3)
#define DQ_TCM_TOE_FLUSH_Q0_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
@@ -327,18 +326,18 @@
#define DQ_TCM_IWARP_POST_RQ_CF_CMD BIT(DQ_TCM_AGG_FLG_SHIFT_CF1)
/* PWM address mapping */
-#define DQ_PWM_OFFSET_DPM_BASE 0x0
-#define DQ_PWM_OFFSET_DPM_END 0x27
+#define DQ_PWM_OFFSET_DPM_BASE 0x0
+#define DQ_PWM_OFFSET_DPM_END 0x27
#define DQ_PWM_OFFSET_XCM16_BASE 0x40
#define DQ_PWM_OFFSET_XCM32_BASE 0x44
#define DQ_PWM_OFFSET_UCM16_BASE 0x48
#define DQ_PWM_OFFSET_UCM32_BASE 0x4C
-#define DQ_PWM_OFFSET_UCM16_4 0x50
+#define DQ_PWM_OFFSET_UCM16_4 0x50
#define DQ_PWM_OFFSET_TCM16_BASE 0x58
#define DQ_PWM_OFFSET_TCM32_BASE 0x5C
-#define DQ_PWM_OFFSET_XCM_FLAGS 0x68
-#define DQ_PWM_OFFSET_UCM_FLAGS 0x69
-#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
+#define DQ_PWM_OFFSET_XCM_FLAGS 0x68
+#define DQ_PWM_OFFSET_UCM_FLAGS 0x69
+#define DQ_PWM_OFFSET_TCM_FLAGS 0x6B
#define DQ_PWM_OFFSET_XCM_RDMA_SQ_PROD (DQ_PWM_OFFSET_XCM16_BASE + 2)
#define DQ_PWM_OFFSET_UCM_RDMA_CQ_CONS_32BIT (DQ_PWM_OFFSET_UCM32_BASE)
@@ -347,10 +346,11 @@
#define DQ_PWM_OFFSET_UCM_RDMA_ARM_FLAGS (DQ_PWM_OFFSET_UCM_FLAGS)
#define DQ_PWM_OFFSET_TCM_ROCE_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 1)
#define DQ_PWM_OFFSET_TCM_IWARP_RQ_PROD (DQ_PWM_OFFSET_TCM16_BASE + 3)
-#define DQ_REGION_SHIFT (12)
+
+#define DQ_REGION_SHIFT (12)
/* DPM */
-#define DQ_DPM_WQE_BUFF_SIZE (320)
+#define DQ_DPM_WQE_BUFF_SIZE (320)
/* Conn type ranges */
#define DQ_CONN_TYPE_RANGE_SHIFT (4)
@@ -359,29 +359,30 @@
/* QM CONSTANTS */
/*****************/
-/* number of TX queues in the QM */
+/* Number of TX queues in the QM */
#define MAX_QM_TX_QUEUES_K2 512
#define MAX_QM_TX_QUEUES_BB 448
#define MAX_QM_TX_QUEUES MAX_QM_TX_QUEUES_K2
-/* number of Other queues in the QM */
+/* Number of Other queues in the QM */
#define MAX_QM_OTHER_QUEUES_BB 64
#define MAX_QM_OTHER_QUEUES_K2 128
#define MAX_QM_OTHER_QUEUES MAX_QM_OTHER_QUEUES_K2
-/* number of queues in a PF queue group */
+/* Number of queues in a PF queue group */
#define QM_PF_QUEUE_GROUP_SIZE 8
-/* the size of a single queue element in bytes */
-#define QM_PQ_ELEMENT_SIZE 4
+/* The size of a single queue element in bytes */
+#define QM_PQ_ELEMENT_SIZE 4
-/* base number of Tx PQs in the CM PQ representation.
- * should be used when storing PQ IDs in CM PQ registers and context
+/* Base number of Tx PQs in the CM PQ representation.
+ * Should be used when storing PQ IDs in CM PQ registers and context.
*/
-#define CM_TX_PQ_BASE 0x200
+#define CM_TX_PQ_BASE 0x200
-/* number of global Vport/QCN rate limiters */
+/* Number of global Vport/QCN rate limiters */
#define MAX_QM_GLOBAL_RLS 256
+
/* QM registers data */
#define QM_LINE_CRD_REG_WIDTH 16
#define QM_LINE_CRD_REG_SIGN_BIT BIT((QM_LINE_CRD_REG_WIDTH - 1))
@@ -432,8 +433,7 @@
#define IGU_CMD_INT_ACK_BASE 0x0400
#define IGU_CMD_INT_ACK_UPPER (IGU_CMD_INT_ACK_BASE + \
- MAX_TOT_SB_PER_PATH - \
- 1)
+ MAX_TOT_SB_PER_PATH - 1)
#define IGU_CMD_INT_ACK_RESERVED_UPPER 0x05ff
#define IGU_CMD_ATTN_BIT_UPD_UPPER 0x05f0
@@ -447,8 +447,7 @@
#define IGU_CMD_PROD_UPD_BASE 0x0600
#define IGU_CMD_PROD_UPD_UPPER (IGU_CMD_PROD_UPD_BASE +\
- MAX_TOT_SB_PER_PATH - \
- 1)
+ MAX_TOT_SB_PER_PATH - 1)
#define IGU_CMD_PROD_UPD_RESERVED_UPPER 0x07ff
/*****************/
@@ -514,129 +513,121 @@
PXP_EXTERNAL_BAR_GLOBAL_WINDOW_LENGTH - 1)
/* PF BAR */
-#define PXP_BAR0_START_GRC 0x0000
-#define PXP_BAR0_GRC_LENGTH 0x1C00000
-#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \
- PXP_BAR0_GRC_LENGTH - 1)
+#define PXP_BAR0_START_GRC 0x0000
+#define PXP_BAR0_GRC_LENGTH 0x1C00000
+#define PXP_BAR0_END_GRC (PXP_BAR0_START_GRC + \
+ PXP_BAR0_GRC_LENGTH - 1)
-#define PXP_BAR0_START_IGU 0x1C00000
-#define PXP_BAR0_IGU_LENGTH 0x10000
-#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \
- PXP_BAR0_IGU_LENGTH - 1)
+#define PXP_BAR0_START_IGU 0x1C00000
+#define PXP_BAR0_IGU_LENGTH 0x10000
+#define PXP_BAR0_END_IGU (PXP_BAR0_START_IGU + \
+ PXP_BAR0_IGU_LENGTH - 1)
-#define PXP_BAR0_START_TSDM 0x1C80000
-#define PXP_BAR0_SDM_LENGTH 0x40000
+#define PXP_BAR0_START_TSDM 0x1C80000
+#define PXP_BAR0_SDM_LENGTH 0x40000
#define PXP_BAR0_SDM_RESERVED_LENGTH 0x40000
-#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_END_TSDM (PXP_BAR0_START_TSDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
-#define PXP_BAR0_START_MSDM 0x1D00000
-#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_START_MSDM 0x1D00000
+#define PXP_BAR0_END_MSDM (PXP_BAR0_START_MSDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
-#define PXP_BAR0_START_USDM 0x1D80000
-#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_START_USDM 0x1D80000
+#define PXP_BAR0_END_USDM (PXP_BAR0_START_USDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
-#define PXP_BAR0_START_XSDM 0x1E00000
-#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_START_XSDM 0x1E00000
+#define PXP_BAR0_END_XSDM (PXP_BAR0_START_XSDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
-#define PXP_BAR0_START_YSDM 0x1E80000
-#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_START_YSDM 0x1E80000
+#define PXP_BAR0_END_YSDM (PXP_BAR0_START_YSDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
-#define PXP_BAR0_START_PSDM 0x1F00000
-#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \
- PXP_BAR0_SDM_LENGTH - 1)
+#define PXP_BAR0_START_PSDM 0x1F00000
+#define PXP_BAR0_END_PSDM (PXP_BAR0_START_PSDM + \
+ PXP_BAR0_SDM_LENGTH - 1)
#define PXP_BAR0_FIRST_INVALID_ADDRESS (PXP_BAR0_END_PSDM + 1)
/* VF BAR */
-#define PXP_VF_BAR0 0
+#define PXP_VF_BAR0 0
-#define PXP_VF_BAR0_START_GRC 0x3E00
-#define PXP_VF_BAR0_GRC_LENGTH 0x200
-#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
- PXP_VF_BAR0_GRC_LENGTH - 1)
+#define PXP_VF_BAR0_START_IGU 0
+#define PXP_VF_BAR0_IGU_LENGTH 0x3000
+#define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \
+ PXP_VF_BAR0_IGU_LENGTH - 1)
-#define PXP_VF_BAR0_START_IGU 0
-#define PXP_VF_BAR0_IGU_LENGTH 0x3000
-#define PXP_VF_BAR0_END_IGU (PXP_VF_BAR0_START_IGU + \
- PXP_VF_BAR0_IGU_LENGTH - 1)
+#define PXP_VF_BAR0_START_DQ 0x3000
+#define PXP_VF_BAR0_DQ_LENGTH 0x200
+#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
+#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \
+ PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
+#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
+ + 4)
+#define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \
+ PXP_VF_BAR0_DQ_LENGTH - 1)
-#define PXP_VF_BAR0_START_DQ 0x3000
-#define PXP_VF_BAR0_DQ_LENGTH 0x200
-#define PXP_VF_BAR0_DQ_OPAQUE_OFFSET 0
-#define PXP_VF_BAR0_ME_OPAQUE_ADDRESS (PXP_VF_BAR0_START_DQ + \
- PXP_VF_BAR0_DQ_OPAQUE_OFFSET)
-#define PXP_VF_BAR0_ME_CONCRETE_ADDRESS (PXP_VF_BAR0_ME_OPAQUE_ADDRESS \
- + 4)
-#define PXP_VF_BAR0_END_DQ (PXP_VF_BAR0_START_DQ + \
- PXP_VF_BAR0_DQ_LENGTH - 1)
+#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
+#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
+#define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
-#define PXP_VF_BAR0_START_TSDM_ZONE_B 0x3200
-#define PXP_VF_BAR0_SDM_LENGTH_ZONE_B 0x200
-#define PXP_VF_BAR0_END_TSDM_ZONE_B (PXP_VF_BAR0_START_TSDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
+#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
+#define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
-#define PXP_VF_BAR0_START_MSDM_ZONE_B 0x3400
-#define PXP_VF_BAR0_END_MSDM_ZONE_B (PXP_VF_BAR0_START_MSDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
+#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
+#define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
-#define PXP_VF_BAR0_START_USDM_ZONE_B 0x3600
-#define PXP_VF_BAR0_END_USDM_ZONE_B (PXP_VF_BAR0_START_USDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
+#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
+#define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
-#define PXP_VF_BAR0_START_XSDM_ZONE_B 0x3800
-#define PXP_VF_BAR0_END_XSDM_ZONE_B (PXP_VF_BAR0_START_XSDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
+#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
+#define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
-#define PXP_VF_BAR0_START_YSDM_ZONE_B 0x3a00
-#define PXP_VF_BAR0_END_YSDM_ZONE_B (PXP_VF_BAR0_START_YSDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
+#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
+#define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B + \
+ PXP_VF_BAR0_SDM_LENGTH_ZONE_B - 1)
-#define PXP_VF_BAR0_START_PSDM_ZONE_B 0x3c00
-#define PXP_VF_BAR0_END_PSDM_ZONE_B (PXP_VF_BAR0_START_PSDM_ZONE_B \
- + \
- PXP_VF_BAR0_SDM_LENGTH_ZONE_B \
- - 1)
+#define PXP_VF_BAR0_START_GRC 0x3E00
+#define PXP_VF_BAR0_GRC_LENGTH 0x200
+#define PXP_VF_BAR0_END_GRC (PXP_VF_BAR0_START_GRC + \
+ PXP_VF_BAR0_GRC_LENGTH - 1)
-#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
-#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
+#define PXP_VF_BAR0_START_SDM_ZONE_A 0x4000
+#define PXP_VF_BAR0_END_SDM_ZONE_A 0x10000
-#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
+#define PXP_VF_BAR0_GRC_WINDOW_LENGTH 32
-#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
-#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
+#define PXP_ILT_PAGE_SIZE_NUM_BITS_MIN 12
+#define PXP_ILT_BLOCK_FACTOR_MULTIPLIER 1024
/* ILT Records */
#define PXP_NUM_ILT_RECORDS_BB 7600
#define PXP_NUM_ILT_RECORDS_K2 11000
#define MAX_NUM_ILT_RECORDS MAX(PXP_NUM_ILT_RECORDS_BB, PXP_NUM_ILT_RECORDS_K2)
-#define PXP_QUEUES_ZONE_MAX_NUM 320
+
+/* Host Interface */
+#define PXP_QUEUES_ZONE_MAX_NUM 320
+
/*****************/
/* PRM CONSTANTS */
/*****************/
-#define PRM_DMA_PAD_BYTES_NUM 2
+#define PRM_DMA_PAD_BYTES_NUM 2
+
/*****************/
/* SDMs CONSTANTS */
/*****************/
-#define SDM_OP_GEN_TRIG_NONE 0
-#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
-#define SDM_OP_GEN_TRIG_AGG_INT 2
-#define SDM_OP_GEN_TRIG_LOADER 4
+#define SDM_OP_GEN_TRIG_NONE 0
+#define SDM_OP_GEN_TRIG_WAKE_THREAD 1
+#define SDM_OP_GEN_TRIG_AGG_INT 2
+#define SDM_OP_GEN_TRIG_LOADER 4
#define SDM_OP_GEN_TRIG_INDICATE_ERROR 6
#define SDM_OP_GEN_TRIG_INC_ORDER_CNT 9
@@ -644,26 +635,26 @@
/* Completion types */
/********************/
-#define SDM_COMP_TYPE_NONE 0
-#define SDM_COMP_TYPE_WAKE_THREAD 1
-#define SDM_COMP_TYPE_AGG_INT 2
-#define SDM_COMP_TYPE_CM 3
-#define SDM_COMP_TYPE_LOADER 4
-#define SDM_COMP_TYPE_PXP 5
-#define SDM_COMP_TYPE_INDICATE_ERROR 6
-#define SDM_COMP_TYPE_RELEASE_THREAD 7
-#define SDM_COMP_TYPE_RAM 8
-#define SDM_COMP_TYPE_INC_ORDER_CNT 9
+#define SDM_COMP_TYPE_NONE 0
+#define SDM_COMP_TYPE_WAKE_THREAD 1
+#define SDM_COMP_TYPE_AGG_INT 2
+#define SDM_COMP_TYPE_CM 3
+#define SDM_COMP_TYPE_LOADER 4
+#define SDM_COMP_TYPE_PXP 5
+#define SDM_COMP_TYPE_INDICATE_ERROR 6
+#define SDM_COMP_TYPE_RELEASE_THREAD 7
+#define SDM_COMP_TYPE_RAM 8
+#define SDM_COMP_TYPE_INC_ORDER_CNT 9
/*****************/
-/* PBF Constants */
+/* PBF CONSTANTS */
/*****************/
/* Number of PBF command queue lines. Each line is 32B. */
-#define PBF_MAX_CMD_LINES 3328
+#define PBF_MAX_CMD_LINES 3328
/* Number of BTB blocks. Each block is 256B. */
-#define BTB_MAX_BLOCKS 1440
+#define BTB_MAX_BLOCKS 1440
/*****************/
/* PRS CONSTANTS */
@@ -679,6 +670,7 @@ struct async_data {
u8 fw_debug_param;
};
+/* Interrupt coalescing TimeSet */
struct coalescing_timeset {
u8 value;
#define COALESCING_TIMESET_TIMESET_MASK 0x7F
@@ -692,20 +684,12 @@ struct common_queue_zone {
__le16 reserved;
};
+/* ETH Rx producers data */
struct eth_rx_prod_data {
__le16 bd_prod;
__le16 cqe_prod;
};
-struct regpair {
- __le32 lo;
- __le32 hi;
-};
-
-struct vf_pf_channel_eqe_data {
- struct regpair msg_addr;
-};
-
struct iscsi_eqe_data {
__le32 cid;
__le16 conn_id;
@@ -719,52 +703,6 @@ struct iscsi_eqe_data {
#define ISCSI_EQE_DATA_RESERVED0_SHIFT 7
};
-struct rdma_eqe_destroy_qp {
- __le32 cid;
- u8 reserved[4];
-};
-
-union rdma_eqe_data {
- struct regpair async_handle;
- struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
-};
-
-struct malicious_vf_eqe_data {
- u8 vf_id;
- u8 err_id;
- __le16 reserved[3];
-};
-
-struct initial_cleanup_eqe_data {
- u8 vf_id;
- u8 reserved[7];
-};
-
-/* Event Data Union */
-union event_ring_data {
- u8 bytes[8];
- struct vf_pf_channel_eqe_data vf_pf_channel;
- struct iscsi_eqe_data iscsi_info;
- union rdma_eqe_data rdma_data;
- struct malicious_vf_eqe_data malicious_vf;
- struct initial_cleanup_eqe_data vf_init_cleanup;
-};
-
-/* Event Ring Entry */
-struct event_ring_entry {
- u8 protocol_id;
- u8 opcode;
- __le16 reserved0;
- __le16 echo;
- u8 fw_return_code;
- u8 flags;
-#define EVENT_RING_ENTRY_ASYNC_MASK 0x1
-#define EVENT_RING_ENTRY_ASYNC_SHIFT 0
-#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F
-#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1
- union event_ring_data data;
-};
-
/* Multi function mode */
enum mf_mode {
ERROR_MODE /* Unsupported mode */,
@@ -781,13 +719,31 @@ enum protocol_type {
PROTOCOLID_CORE,
PROTOCOLID_ETH,
PROTOCOLID_IWARP,
- PROTOCOLID_RESERVED5,
+ PROTOCOLID_RESERVED0,
PROTOCOLID_PREROCE,
PROTOCOLID_COMMON,
- PROTOCOLID_RESERVED6,
+ PROTOCOLID_RESERVED1,
MAX_PROTOCOL_TYPE
};
+struct regpair {
+ __le32 lo;
+ __le32 hi;
+};
+
+/* RoCE Destroy Event Data */
+struct rdma_eqe_destroy_qp {
+ __le32 cid;
+ u8 reserved[4];
+};
+
+/* RDMA Event Data Union */
+union rdma_eqe_data {
+ struct regpair async_handle;
+ struct rdma_eqe_destroy_qp rdma_destroy_qp_data;
+};
+
+/* Ustorm Queue Zone */
struct ustorm_eth_queue_zone {
struct coalescing_timeset int_coalescing_timeset;
u8 reserved[3];
@@ -798,62 +754,71 @@ struct ustorm_queue_zone {
struct common_queue_zone common;
};
-/* status block structure */
+/* Status block structure */
struct cau_pi_entry {
u32 prod;
-#define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
-#define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
-#define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
-#define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
-#define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
-#define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
-#define CAU_PI_ENTRY_RESERVED_MASK 0xFF
-#define CAU_PI_ENTRY_RESERVED_SHIFT 24
+#define CAU_PI_ENTRY_PROD_VAL_MASK 0xFFFF
+#define CAU_PI_ENTRY_PROD_VAL_SHIFT 0
+#define CAU_PI_ENTRY_PI_TIMESET_MASK 0x7F
+#define CAU_PI_ENTRY_PI_TIMESET_SHIFT 16
+#define CAU_PI_ENTRY_FSM_SEL_MASK 0x1
+#define CAU_PI_ENTRY_FSM_SEL_SHIFT 23
+#define CAU_PI_ENTRY_RESERVED_MASK 0xFF
+#define CAU_PI_ENTRY_RESERVED_SHIFT 24
};
-/* status block structure */
+/* Status block structure */
struct cau_sb_entry {
u32 data;
-#define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
-#define CAU_SB_ENTRY_SB_PROD_SHIFT 0
-#define CAU_SB_ENTRY_STATE0_MASK 0xF
-#define CAU_SB_ENTRY_STATE0_SHIFT 24
-#define CAU_SB_ENTRY_STATE1_MASK 0xF
-#define CAU_SB_ENTRY_STATE1_SHIFT 28
+#define CAU_SB_ENTRY_SB_PROD_MASK 0xFFFFFF
+#define CAU_SB_ENTRY_SB_PROD_SHIFT 0
+#define CAU_SB_ENTRY_STATE0_MASK 0xF
+#define CAU_SB_ENTRY_STATE0_SHIFT 24
+#define CAU_SB_ENTRY_STATE1_MASK 0xF
+#define CAU_SB_ENTRY_STATE1_SHIFT 28
u32 params;
-#define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
-#define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
-#define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
-#define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
-#define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
-#define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
-#define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
-#define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
-#define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
-#define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
-#define CAU_SB_ENTRY_VF_VALID_MASK 0x1
-#define CAU_SB_ENTRY_VF_VALID_SHIFT 26
-#define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
-#define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
-#define CAU_SB_ENTRY_TPH_MASK 0x1
-#define CAU_SB_ENTRY_TPH_SHIFT 31
+#define CAU_SB_ENTRY_SB_TIMESET0_MASK 0x7F
+#define CAU_SB_ENTRY_SB_TIMESET0_SHIFT 0
+#define CAU_SB_ENTRY_SB_TIMESET1_MASK 0x7F
+#define CAU_SB_ENTRY_SB_TIMESET1_SHIFT 7
+#define CAU_SB_ENTRY_TIMER_RES0_MASK 0x3
+#define CAU_SB_ENTRY_TIMER_RES0_SHIFT 14
+#define CAU_SB_ENTRY_TIMER_RES1_MASK 0x3
+#define CAU_SB_ENTRY_TIMER_RES1_SHIFT 16
+#define CAU_SB_ENTRY_VF_NUMBER_MASK 0xFF
+#define CAU_SB_ENTRY_VF_NUMBER_SHIFT 18
+#define CAU_SB_ENTRY_VF_VALID_MASK 0x1
+#define CAU_SB_ENTRY_VF_VALID_SHIFT 26
+#define CAU_SB_ENTRY_PF_NUMBER_MASK 0xF
+#define CAU_SB_ENTRY_PF_NUMBER_SHIFT 27
+#define CAU_SB_ENTRY_TPH_MASK 0x1
+#define CAU_SB_ENTRY_TPH_SHIFT 31
};
-/* core doorbell data */
+/* Igu cleanup bit values to distinguish between clean or producer consumer
+ * update.
+ */
+enum command_type_bit {
+ IGU_COMMAND_TYPE_NOP = 0,
+ IGU_COMMAND_TYPE_SET = 1,
+ MAX_COMMAND_TYPE_BIT
+};
+
+/* Core doorbell data */
struct core_db_data {
u8 params;
-#define CORE_DB_DATA_DEST_MASK 0x3
-#define CORE_DB_DATA_DEST_SHIFT 0
-#define CORE_DB_DATA_AGG_CMD_MASK 0x3
-#define CORE_DB_DATA_AGG_CMD_SHIFT 2
-#define CORE_DB_DATA_BYPASS_EN_MASK 0x1
-#define CORE_DB_DATA_BYPASS_EN_SHIFT 4
-#define CORE_DB_DATA_RESERVED_MASK 0x1
-#define CORE_DB_DATA_RESERVED_SHIFT 5
-#define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
-#define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
- u8 agg_flags;
- __le16 spq_prod;
+#define CORE_DB_DATA_DEST_MASK 0x3
+#define CORE_DB_DATA_DEST_SHIFT 0
+#define CORE_DB_DATA_AGG_CMD_MASK 0x3
+#define CORE_DB_DATA_AGG_CMD_SHIFT 2
+#define CORE_DB_DATA_BYPASS_EN_MASK 0x1
+#define CORE_DB_DATA_BYPASS_EN_SHIFT 4
+#define CORE_DB_DATA_RESERVED_MASK 0x1
+#define CORE_DB_DATA_RESERVED_SHIFT 5
+#define CORE_DB_DATA_AGG_VAL_SEL_MASK 0x3
+#define CORE_DB_DATA_AGG_VAL_SEL_SHIFT 6
+ u8 agg_flags;
+ __le16 spq_prod;
};
/* Enum of doorbell aggregative command selection */
@@ -909,67 +874,69 @@ struct db_l2_dpm_sge {
struct regpair addr;
__le16 nbytes;
__le16 bitfields;
-#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
-#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
-#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
-#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
-#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
-#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
-#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
-#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
+#define DB_L2_DPM_SGE_TPH_ST_INDEX_MASK 0x1FF
+#define DB_L2_DPM_SGE_TPH_ST_INDEX_SHIFT 0
+#define DB_L2_DPM_SGE_RESERVED0_MASK 0x3
+#define DB_L2_DPM_SGE_RESERVED0_SHIFT 9
+#define DB_L2_DPM_SGE_ST_VALID_MASK 0x1
+#define DB_L2_DPM_SGE_ST_VALID_SHIFT 11
+#define DB_L2_DPM_SGE_RESERVED1_MASK 0xF
+#define DB_L2_DPM_SGE_RESERVED1_SHIFT 12
__le32 reserved2;
};
/* Structure for doorbell address, in legacy mode */
struct db_legacy_addr {
__le32 addr;
-#define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
-#define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
-#define DB_LEGACY_ADDR_DEMS_MASK 0x7
-#define DB_LEGACY_ADDR_DEMS_SHIFT 2
-#define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF
-#define DB_LEGACY_ADDR_ICID_SHIFT 5
+#define DB_LEGACY_ADDR_RESERVED0_MASK 0x3
+#define DB_LEGACY_ADDR_RESERVED0_SHIFT 0
+#define DB_LEGACY_ADDR_DEMS_MASK 0x7
+#define DB_LEGACY_ADDR_DEMS_SHIFT 2
+#define DB_LEGACY_ADDR_ICID_MASK 0x7FFFFFF
+#define DB_LEGACY_ADDR_ICID_SHIFT 5
};
/* Structure for doorbell address, in PWM mode */
struct db_pwm_addr {
__le32 addr;
#define DB_PWM_ADDR_RESERVED0_MASK 0x7
-#define DB_PWM_ADDR_RESERVED0_SHIFT 0
-#define DB_PWM_ADDR_OFFSET_MASK 0x7F
+#define DB_PWM_ADDR_RESERVED0_SHIFT 0
+#define DB_PWM_ADDR_OFFSET_MASK 0x7F
#define DB_PWM_ADDR_OFFSET_SHIFT 3
-#define DB_PWM_ADDR_WID_MASK 0x3
-#define DB_PWM_ADDR_WID_SHIFT 10
-#define DB_PWM_ADDR_DPI_MASK 0xFFFF
-#define DB_PWM_ADDR_DPI_SHIFT 12
+#define DB_PWM_ADDR_WID_MASK 0x3
+#define DB_PWM_ADDR_WID_SHIFT 10
+#define DB_PWM_ADDR_DPI_MASK 0xFFFF
+#define DB_PWM_ADDR_DPI_SHIFT 12
#define DB_PWM_ADDR_RESERVED1_MASK 0xF
-#define DB_PWM_ADDR_RESERVED1_SHIFT 28
+#define DB_PWM_ADDR_RESERVED1_SHIFT 28
};
-/* Parameters to RoCE firmware, passed in EDPM doorbell */
+/* Parameters to RDMA firmware, passed in EDPM doorbell */
struct db_rdma_dpm_params {
__le32 params;
-#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
-#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
-#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
-#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6
-#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
-#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8
-#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
-#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16
-#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
-#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27
-#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
-#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
-#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1
-#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29
-#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1
-#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30
+#define DB_RDMA_DPM_PARAMS_SIZE_MASK 0x3F
+#define DB_RDMA_DPM_PARAMS_SIZE_SHIFT 0
+#define DB_RDMA_DPM_PARAMS_DPM_TYPE_MASK 0x3
+#define DB_RDMA_DPM_PARAMS_DPM_TYPE_SHIFT 6
+#define DB_RDMA_DPM_PARAMS_OPCODE_MASK 0xFF
+#define DB_RDMA_DPM_PARAMS_OPCODE_SHIFT 8
+#define DB_RDMA_DPM_PARAMS_WQE_SIZE_MASK 0x7FF
+#define DB_RDMA_DPM_PARAMS_WQE_SIZE_SHIFT 16
+#define DB_RDMA_DPM_PARAMS_RESERVED0_MASK 0x1
+#define DB_RDMA_DPM_PARAMS_RESERVED0_SHIFT 27
+#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_MASK 0x1
+#define DB_RDMA_DPM_PARAMS_COMPLETION_FLG_SHIFT 28
+#define DB_RDMA_DPM_PARAMS_S_FLG_MASK 0x1
+#define DB_RDMA_DPM_PARAMS_S_FLG_SHIFT 29
+#define DB_RDMA_DPM_PARAMS_RESERVED1_MASK 0x1
+#define DB_RDMA_DPM_PARAMS_RESERVED1_SHIFT 30
#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_MASK 0x1
#define DB_RDMA_DPM_PARAMS_CONN_TYPE_IS_IWARP_SHIFT 31
};
-/* Structure for doorbell data, in ROCE DPM mode, for 1st db in a DPM burst */
+/* Structure for doorbell data, in RDMA DPM mode, for the first doorbell in a
+ * DPM burst.
+ */
struct db_rdma_dpm_data {
__le16 icid;
__le16 prod_val;
@@ -988,20 +955,20 @@ enum igu_int_cmd {
/* IGU producer or consumer update command */
struct igu_prod_cons_update {
u32 sb_id_and_flags;
-#define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
-#define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
-#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
-#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
-#define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
-#define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
-#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
-#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
-#define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
-#define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
-#define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
-#define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
-#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
-#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
+#define IGU_PROD_CONS_UPDATE_SB_INDEX_MASK 0xFFFFFF
+#define IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT 0
+#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_MASK 0x1
+#define IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT 24
+#define IGU_PROD_CONS_UPDATE_ENABLE_INT_MASK 0x3
+#define IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT 25
+#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_MASK 0x1
+#define IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT 27
+#define IGU_PROD_CONS_UPDATE_TIMER_MASK_MASK 0x1
+#define IGU_PROD_CONS_UPDATE_TIMER_MASK_SHIFT 28
+#define IGU_PROD_CONS_UPDATE_RESERVED0_MASK 0x3
+#define IGU_PROD_CONS_UPDATE_RESERVED0_SHIFT 29
+#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_MASK 0x1
+#define IGU_PROD_CONS_UPDATE_COMMAND_TYPE_SHIFT 31
u32 reserved1;
};
@@ -1014,36 +981,37 @@ enum igu_seg_access {
struct parsing_and_err_flags {
__le16 flags;
-#define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
-#define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
-#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
-#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
-#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
-#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
-#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
-#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
-#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
-#define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
-#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
-#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
-#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
-#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
-#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
-#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
-#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
+#define PARSING_AND_ERR_FLAGS_L3TYPE_MASK 0x3
+#define PARSING_AND_ERR_FLAGS_L3TYPE_SHIFT 0
+#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_MASK 0x3
+#define PARSING_AND_ERR_FLAGS_L4PROTOCOL_SHIFT 2
+#define PARSING_AND_ERR_FLAGS_IPV4FRAG_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_IPV4FRAG_SHIFT 4
+#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TAG8021QEXIST_SHIFT 5
+#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_L4CHKSMWASCALCULATED_SHIFT 6
+#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TIMESYNCPKT_SHIFT 7
+#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TIMESTAMPRECORDED_SHIFT 8
+#define PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT 9
+#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT 10
+#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TUNNELEXIST_SHIFT 11
+#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TUNNEL8021QTAGEXIST_SHIFT 12
+#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT 13
+#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMWASCALCULATED_SHIFT 14
+#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK 0x1
+#define PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT 15
};
+/* Parsing error flags bitmap */
struct parsing_err_flags {
__le16 flags;
#define PARSING_ERR_FLAGS_MAC_ERROR_MASK 0x1
@@ -1080,168 +1048,160 @@ struct parsing_err_flags {
#define PARSING_ERR_FLAGS_TUNNEL_L4_CHKSM_ERROR_SHIFT 15
};
+/* Pb context */
struct pb_context {
__le32 crc[4];
};
+/* Concrete Function ID */
struct pxp_concrete_fid {
__le16 fid;
-#define PXP_CONCRETE_FID_PFID_MASK 0xF
-#define PXP_CONCRETE_FID_PFID_SHIFT 0
-#define PXP_CONCRETE_FID_PORT_MASK 0x3
-#define PXP_CONCRETE_FID_PORT_SHIFT 4
-#define PXP_CONCRETE_FID_PATH_MASK 0x1
-#define PXP_CONCRETE_FID_PATH_SHIFT 6
-#define PXP_CONCRETE_FID_VFVALID_MASK 0x1
-#define PXP_CONCRETE_FID_VFVALID_SHIFT 7
-#define PXP_CONCRETE_FID_VFID_MASK 0xFF
-#define PXP_CONCRETE_FID_VFID_SHIFT 8
+#define PXP_CONCRETE_FID_PFID_MASK 0xF
+#define PXP_CONCRETE_FID_PFID_SHIFT 0
+#define PXP_CONCRETE_FID_PORT_MASK 0x3
+#define PXP_CONCRETE_FID_PORT_SHIFT 4
+#define PXP_CONCRETE_FID_PATH_MASK 0x1
+#define PXP_CONCRETE_FID_PATH_SHIFT 6
+#define PXP_CONCRETE_FID_VFVALID_MASK 0x1
+#define PXP_CONCRETE_FID_VFVALID_SHIFT 7
+#define PXP_CONCRETE_FID_VFID_MASK 0xFF
+#define PXP_CONCRETE_FID_VFID_SHIFT 8
};
+/* Concrete Function ID */
struct pxp_pretend_concrete_fid {
__le16 fid;
-#define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
-#define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
-#define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
-#define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
-#define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
-#define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
-#define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
-#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
+#define PXP_PRETEND_CONCRETE_FID_PFID_MASK 0xF
+#define PXP_PRETEND_CONCRETE_FID_PFID_SHIFT 0
+#define PXP_PRETEND_CONCRETE_FID_RESERVED_MASK 0x7
+#define PXP_PRETEND_CONCRETE_FID_RESERVED_SHIFT 4
+#define PXP_PRETEND_CONCRETE_FID_VFVALID_MASK 0x1
+#define PXP_PRETEND_CONCRETE_FID_VFVALID_SHIFT 7
+#define PXP_PRETEND_CONCRETE_FID_VFID_MASK 0xFF
+#define PXP_PRETEND_CONCRETE_FID_VFID_SHIFT 8
};
+/* Function ID */
union pxp_pretend_fid {
struct pxp_pretend_concrete_fid concrete_fid;
- __le16 opaque_fid;
+ __le16 opaque_fid;
};
-/* Pxp Pretend Command Register. */
+/* Pxp Pretend Command Register */
struct pxp_pretend_cmd {
- union pxp_pretend_fid fid;
- __le16 control;
-#define PXP_PRETEND_CMD_PATH_MASK 0x1
-#define PXP_PRETEND_CMD_PATH_SHIFT 0
-#define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
-#define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
-#define PXP_PRETEND_CMD_PORT_MASK 0x3
-#define PXP_PRETEND_CMD_PORT_SHIFT 2
-#define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
-#define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
-#define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
-#define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
-#define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
-#define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
-#define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
-#define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
-#define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
-#define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
-#define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
-#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
+ union pxp_pretend_fid fid;
+ __le16 control;
+#define PXP_PRETEND_CMD_PATH_MASK 0x1
+#define PXP_PRETEND_CMD_PATH_SHIFT 0
+#define PXP_PRETEND_CMD_USE_PORT_MASK 0x1
+#define PXP_PRETEND_CMD_USE_PORT_SHIFT 1
+#define PXP_PRETEND_CMD_PORT_MASK 0x3
+#define PXP_PRETEND_CMD_PORT_SHIFT 2
+#define PXP_PRETEND_CMD_RESERVED0_MASK 0xF
+#define PXP_PRETEND_CMD_RESERVED0_SHIFT 4
+#define PXP_PRETEND_CMD_RESERVED1_MASK 0xF
+#define PXP_PRETEND_CMD_RESERVED1_SHIFT 8
+#define PXP_PRETEND_CMD_PRETEND_PATH_MASK 0x1
+#define PXP_PRETEND_CMD_PRETEND_PATH_SHIFT 12
+#define PXP_PRETEND_CMD_PRETEND_PORT_MASK 0x1
+#define PXP_PRETEND_CMD_PRETEND_PORT_SHIFT 13
+#define PXP_PRETEND_CMD_PRETEND_FUNCTION_MASK 0x1
+#define PXP_PRETEND_CMD_PRETEND_FUNCTION_SHIFT 14
+#define PXP_PRETEND_CMD_IS_CONCRETE_MASK 0x1
+#define PXP_PRETEND_CMD_IS_CONCRETE_SHIFT 15
};
-/* PTT Record in PXP Admin Window. */
+/* PTT Record in PXP Admin Window */
struct pxp_ptt_entry {
- __le32 offset;
-#define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
-#define PXP_PTT_ENTRY_OFFSET_SHIFT 0
-#define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
-#define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
- struct pxp_pretend_cmd pretend;
+ __le32 offset;
+#define PXP_PTT_ENTRY_OFFSET_MASK 0x7FFFFF
+#define PXP_PTT_ENTRY_OFFSET_SHIFT 0
+#define PXP_PTT_ENTRY_RESERVED0_MASK 0x1FF
+#define PXP_PTT_ENTRY_RESERVED0_SHIFT 23
+ struct pxp_pretend_cmd pretend;
};
-/* VF Zone A Permission Register. */
+/* VF Zone A Permission Register */
struct pxp_vf_zone_a_permission {
__le32 control;
-#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
-#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
-#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
-#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
-#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
-#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
-#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
-#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
+#define PXP_VF_ZONE_A_PERMISSION_VFID_MASK 0xFF
+#define PXP_VF_ZONE_A_PERMISSION_VFID_SHIFT 0
+#define PXP_VF_ZONE_A_PERMISSION_VALID_MASK 0x1
+#define PXP_VF_ZONE_A_PERMISSION_VALID_SHIFT 8
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_MASK 0x7F
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED0_SHIFT 9
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_MASK 0xFFFF
+#define PXP_VF_ZONE_A_PERMISSION_RESERVED1_SHIFT 16
};
-/* RSS hash type */
+/* Rdif context */
struct rdif_task_context {
__le32 initial_ref_tag;
__le16 app_tag_value;
__le16 app_tag_mask;
u8 flags0;
-#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
-#define RDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
-#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
-#define RDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
-#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
-#define RDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
-#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
-#define RDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
-#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
-#define RDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
-#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
-#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
-#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
-#define RDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 7
+#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
+#define RDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
+#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
+#define RDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
+#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
+#define RDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
+#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
+#define RDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
+#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
+#define RDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
+#define RDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
+#define RDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
+#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
+#define RDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 7
u8 partial_dif_data[7];
__le16 partial_crc_value;
__le16 partial_checksum_value;
__le32 offset_in_io;
__le16 flags1;
-#define RDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
-#define RDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
-#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
-#define RDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
-#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
-#define RDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
-#define RDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
-#define RDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
-#define RDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
-#define RDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
-#define RDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
-#define RDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
-#define RDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
-#define RDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
-#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
-#define RDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
-#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
-#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
-#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
-#define RDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
-#define RDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 14
-#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
-#define RDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 15
+#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
+#define RDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
+#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
+#define RDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
+#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
+#define RDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
+#define RDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
+#define RDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
+#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
+#define RDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
+#define RDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
+#define RDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
+#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
+#define RDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
+#define RDIF_TASK_CONTEXT_RESERVED0_MASK 0x1
+#define RDIF_TASK_CONTEXT_RESERVED0_SHIFT 12
+#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
+#define RDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
+#define RDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 14
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
+#define RDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 15
__le16 state;
-#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_MASK 0xF
-#define RDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFT_SHIFT 0
-#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_MASK 0xF
-#define RDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFT_SHIFT 4
-#define RDIF_TASK_CONTEXT_ERRORINIO_MASK 0x1
-#define RDIF_TASK_CONTEXT_ERRORINIO_SHIFT 8
-#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
-#define RDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
-#define RDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
-#define RDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 10
-#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
-#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
+#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_MASK 0xF
+#define RDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_SHIFT 0
+#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_MASK 0xF
+#define RDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_SHIFT 4
+#define RDIF_TASK_CONTEXT_ERROR_IN_IO_MASK 0x1
+#define RDIF_TASK_CONTEXT_ERROR_IN_IO_SHIFT 8
+#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_MASK 0x1
+#define RDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_SHIFT 9
+#define RDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
+#define RDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 10
+#define RDIF_TASK_CONTEXT_RESERVED1_MASK 0x3
+#define RDIF_TASK_CONTEXT_RESERVED1_SHIFT 14
__le32 reserved2;
};
-/* RSS hash type */
-enum rss_hash_type {
- RSS_HASH_TYPE_DEFAULT = 0,
- RSS_HASH_TYPE_IPV4 = 1,
- RSS_HASH_TYPE_TCP_IPV4 = 2,
- RSS_HASH_TYPE_IPV6 = 3,
- RSS_HASH_TYPE_TCP_IPV6 = 4,
- RSS_HASH_TYPE_UDP_IPV4 = 5,
- RSS_HASH_TYPE_UDP_IPV6 = 6,
- MAX_RSS_HASH_TYPE
-};
-
-/* status block structure */
+/* Status block structure */
struct status_block {
__le16 pi_array[PIS_PER_SB];
__le32 sb_num;
@@ -1258,88 +1218,90 @@ struct status_block {
#define STATUS_BLOCK_ZERO_PAD3_SHIFT 24
};
+/* Tdif context */
struct tdif_task_context {
__le32 initial_ref_tag;
__le16 app_tag_value;
__le16 app_tag_mask;
- __le16 partial_crc_valueB;
- __le16 partial_checksum_valueB;
+ __le16 partial_crc_value_b;
+ __le16 partial_checksum_value_b;
__le16 stateB;
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_MASK 0xF
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTB_SHIFT 0
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_MASK 0xF
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTB_SHIFT 4
-#define TDIF_TASK_CONTEXT_ERRORINIOB_MASK 0x1
-#define TDIF_TASK_CONTEXT_ERRORINIOB_SHIFT 8
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_MASK 0x1
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOW_SHIFT 9
-#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
-#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_MASK 0xF
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_B_SHIFT 0
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_MASK 0xF
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_B_SHIFT 4
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_MASK 0x1
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_B_SHIFT 8
+#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_MASK 0x1
+#define TDIF_TASK_CONTEXT_CHECKSUM_VERFLOW_SHIFT 9
+#define TDIF_TASK_CONTEXT_RESERVED0_MASK 0x3F
+#define TDIF_TASK_CONTEXT_RESERVED0_SHIFT 10
u8 reserved1;
u8 flags0;
-#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_MASK 0x1
-#define TDIF_TASK_CONTEXT_IGNOREAPPTAG_SHIFT 0
-#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_MASK 0x1
-#define TDIF_TASK_CONTEXT_INITIALREFTAGVALID_SHIFT 1
-#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_MASK 0x1
-#define TDIF_TASK_CONTEXT_HOSTGUARDTYPE_SHIFT 2
-#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_MASK 0x1
-#define TDIF_TASK_CONTEXT_SETERRORWITHEOP_SHIFT 3
-#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_MASK 0x3
-#define TDIF_TASK_CONTEXT_PROTECTIONTYPE_SHIFT 4
-#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
-#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
-#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
-#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
+#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_MASK 0x1
+#define TDIF_TASK_CONTEXT_IGNORE_APP_TAG_SHIFT 0
+#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_MASK 0x1
+#define TDIF_TASK_CONTEXT_INITIAL_REF_TAG_VALID_SHIFT 1
+#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_MASK 0x1
+#define TDIF_TASK_CONTEXT_HOST_GUARD_TYPE_SHIFT 2
+#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_MASK 0x1
+#define TDIF_TASK_CONTEXT_SET_ERROR_WITH_EOP_SHIFT 3
+#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_MASK 0x3
+#define TDIF_TASK_CONTEXT_PROTECTION_TYPE_SHIFT 4
+#define TDIF_TASK_CONTEXT_CRC_SEED_MASK 0x1
+#define TDIF_TASK_CONTEXT_CRC_SEED_SHIFT 6
+#define TDIF_TASK_CONTEXT_RESERVED2_MASK 0x1
+#define TDIF_TASK_CONTEXT_RESERVED2_SHIFT 7
__le32 flags1;
-#define TDIF_TASK_CONTEXT_VALIDATEGUARD_MASK 0x1
-#define TDIF_TASK_CONTEXT_VALIDATEGUARD_SHIFT 0
-#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_MASK 0x1
-#define TDIF_TASK_CONTEXT_VALIDATEAPPTAG_SHIFT 1
-#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_MASK 0x1
-#define TDIF_TASK_CONTEXT_VALIDATEREFTAG_SHIFT 2
-#define TDIF_TASK_CONTEXT_FORWARDGUARD_MASK 0x1
-#define TDIF_TASK_CONTEXT_FORWARDGUARD_SHIFT 3
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_MASK 0x1
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAG_SHIFT 4
-#define TDIF_TASK_CONTEXT_FORWARDREFTAG_MASK 0x1
-#define TDIF_TASK_CONTEXT_FORWARDREFTAG_SHIFT 5
-#define TDIF_TASK_CONTEXT_INTERVALSIZE_MASK 0x7
-#define TDIF_TASK_CONTEXT_INTERVALSIZE_SHIFT 6
-#define TDIF_TASK_CONTEXT_HOSTINTERFACE_MASK 0x3
-#define TDIF_TASK_CONTEXT_HOSTINTERFACE_SHIFT 9
-#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_MASK 0x1
-#define TDIF_TASK_CONTEXT_DIFBEFOREDATA_SHIFT 11
-#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
-#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
-#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_MASK 0x1
-#define TDIF_TASK_CONTEXT_NETWORKINTERFACE_SHIFT 13
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_MASK 0xF
-#define TDIF_TASK_CONTEXT_RECEIVEDDIFBYTESLEFTA_SHIFT 14
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_MASK 0xF
-#define TDIF_TASK_CONTEXT_TRANSMITEDDIFBYTESLEFTA_SHIFT 18
-#define TDIF_TASK_CONTEXT_ERRORINIOA_MASK 0x1
-#define TDIF_TASK_CONTEXT_ERRORINIOA_SHIFT 22
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_MASK 0x1
-#define TDIF_TASK_CONTEXT_CHECKSUMOVERFLOWA_SHIFT 23
-#define TDIF_TASK_CONTEXT_REFTAGMASK_MASK 0xF
-#define TDIF_TASK_CONTEXT_REFTAGMASK_SHIFT 24
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_MASK 0x1
-#define TDIF_TASK_CONTEXT_FORWARDAPPTAGWITHMASK_SHIFT 28
-#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_MASK 0x1
-#define TDIF_TASK_CONTEXT_FORWARDREFTAGWITHMASK_SHIFT 29
-#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_MASK 0x1
-#define TDIF_TASK_CONTEXT_KEEPREFTAGCONST_SHIFT 30
-#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
-#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
- __le32 offset_in_iob;
+#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_MASK 0x1
+#define TDIF_TASK_CONTEXT_VALIDATE_GUARD_SHIFT 0
+#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_MASK 0x1
+#define TDIF_TASK_CONTEXT_VALIDATE_APP_TAG_SHIFT 1
+#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_MASK 0x1
+#define TDIF_TASK_CONTEXT_VALIDATE_REF_TAG_SHIFT 2
+#define TDIF_TASK_CONTEXT_FORWARD_GUARD_MASK 0x1
+#define TDIF_TASK_CONTEXT_FORWARD_GUARD_SHIFT 3
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_MASK 0x1
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_SHIFT 4
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_MASK 0x1
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_SHIFT 5
+#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_MASK 0x7
+#define TDIF_TASK_CONTEXT_INTERVAL_SIZE_SHIFT 6
+#define TDIF_TASK_CONTEXT_HOST_INTERFACE_MASK 0x3
+#define TDIF_TASK_CONTEXT_HOST_INTERFACE_SHIFT 9
+#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_MASK 0x1
+#define TDIF_TASK_CONTEXT_DIF_BEFORE_DATA_SHIFT 11
+#define TDIF_TASK_CONTEXT_RESERVED3_MASK 0x1
+#define TDIF_TASK_CONTEXT_RESERVED3_SHIFT 12
+#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_MASK 0x1
+#define TDIF_TASK_CONTEXT_NETWORK_INTERFACE_SHIFT 13
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_MASK 0xF
+#define TDIF_TASK_CONTEXT_RECEIVED_DIF_BYTES_LEFT_A_SHIFT 14
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_MASK 0xF
+#define TDIF_TASK_CONTEXT_TRANSMITED_DIF_BYTES_LEFT_A_SHIFT 18
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_MASK 0x1
+#define TDIF_TASK_CONTEXT_ERROR_IN_IO_A_SHIFT 22
+#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_MASK 0x1
+#define TDIF_TASK_CONTEXT_CHECKSUM_OVERFLOW_A_SHIFT 23
+#define TDIF_TASK_CONTEXT_REF_TAG_MASK_MASK 0xF
+#define TDIF_TASK_CONTEXT_REF_TAG_MASK_SHIFT 24
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_MASK 0x1
+#define TDIF_TASK_CONTEXT_FORWARD_APP_TAG_WITH_MASK_SHIFT 28
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_MASK 0x1
+#define TDIF_TASK_CONTEXT_FORWARD_REF_TAG_WITH_MASK_SHIFT 29
+#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_MASK 0x1
+#define TDIF_TASK_CONTEXT_KEEP_REF_TAG_CONST_SHIFT 30
+#define TDIF_TASK_CONTEXT_RESERVED4_MASK 0x1
+#define TDIF_TASK_CONTEXT_RESERVED4_SHIFT 31
+ __le32 offset_in_io_b;
__le16 partial_crc_value_a;
- __le16 partial_checksum_valuea_;
- __le32 offset_in_ioa;
+ __le16 partial_checksum_value_a;
+ __le32 offset_in_io_a;
u8 partial_dif_data_a[8];
u8 partial_dif_data_b[8];
};
+/* Timers context */
struct timers_context {
__le32 logical_client_0;
#define TIMERS_CONTEXT_EXPIRATIONTIMELC0_MASK 0x7FFFFFF
@@ -1385,6 +1347,7 @@ struct timers_context {
#define TIMERS_CONTEXT_RESERVED7_SHIFT 29
};
+/* Enum for next_protocol field of tunnel_parsing_flags / tunnelTypeDesc */
enum tunnel_next_protocol {
e_unknown = 0,
e_l2 = 1,
diff --git a/include/linux/qed/eth_common.h b/include/linux/qed/eth_common.h
index cb06e6e..f554f4b 100644
--- a/include/linux/qed/eth_common.h
+++ b/include/linux/qed/eth_common.h
@@ -36,139 +36,140 @@
/********************/
/* ETH FW CONSTANTS */
/********************/
-#define ETH_HSI_VER_MAJOR 3
-#define ETH_HSI_VER_MINOR 10
+
+#define ETH_HSI_VER_MAJOR 3
+#define ETH_HSI_VER_MINOR 10
#define ETH_HSI_VER_NO_PKT_LEN_TUNN 5
-#define ETH_CACHE_LINE_SIZE 64
-#define ETH_RX_CQE_GAP 32
-#define ETH_MAX_RAMROD_PER_CON 8
-#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
-#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
-#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
-#define ETH_RX_NUM_NEXT_PAGE_BDS 2
+#define ETH_CACHE_LINE_SIZE 64
+#define ETH_RX_CQE_GAP 32
+#define ETH_MAX_RAMROD_PER_CON 8
+#define ETH_TX_BD_PAGE_SIZE_BYTES 4096
+#define ETH_RX_BD_PAGE_SIZE_BYTES 4096
+#define ETH_RX_CQE_PAGE_SIZE_BYTES 4096
+#define ETH_RX_NUM_NEXT_PAGE_BDS 2
-#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
-#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
+#define ETH_MAX_TUNN_LSO_INNER_IPV4_OFFSET 253
+#define ETH_MAX_TUNN_LSO_INNER_IPV6_OFFSET 251
-#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
-#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
-#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
-#define ETH_TX_MAX_LSO_HDR_NBD 4
-#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
-#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
-#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
-#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
-#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
-#define ETH_TX_MAX_LSO_HDR_BYTES 510
-#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
-#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
-#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
-#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
-#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
+#define ETH_TX_MIN_BDS_PER_NON_LSO_PKT 1
+#define ETH_TX_MAX_BDS_PER_NON_LSO_PACKET 18
+#define ETH_TX_MAX_BDS_PER_LSO_PACKET 255
+#define ETH_TX_MAX_LSO_HDR_NBD 4
+#define ETH_TX_MIN_BDS_PER_LSO_PKT 3
+#define ETH_TX_MIN_BDS_PER_TUNN_IPV6_WITH_EXT_PKT 3
+#define ETH_TX_MIN_BDS_PER_IPV6_WITH_EXT_PKT 2
+#define ETH_TX_MIN_BDS_PER_PKT_W_LOOPBACK_MODE 2
+#define ETH_TX_MAX_NON_LSO_PKT_LEN (9700 - (4 + 4 + 12 + 8))
+#define ETH_TX_MAX_LSO_HDR_BYTES 510
+#define ETH_TX_LSO_WINDOW_BDS_NUM (18 - 1)
+#define ETH_TX_LSO_WINDOW_MIN_LEN 9700
+#define ETH_TX_MAX_LSO_PAYLOAD_LEN 0xFE000
+#define ETH_TX_NUM_SAME_AS_LAST_ENTRIES 320
+#define ETH_TX_INACTIVE_SAME_AS_LAST 0xFFFF
-#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
+#define ETH_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
#define ETH_NUM_STATISTIC_COUNTERS_DOUBLE_VF_ZONE \
(ETH_NUM_STATISTIC_COUNTERS - MAX_NUM_VFS / 2)
#define ETH_NUM_STATISTIC_COUNTERS_QUAD_VF_ZONE \
(ETH_NUM_STATISTIC_COUNTERS - 3 * MAX_NUM_VFS / 4)
/* Maximum number of buffers, used for RX packet placement */
-#define ETH_RX_MAX_BUFF_PER_PKT 5
-#define ETH_RX_BD_THRESHOLD 12
+#define ETH_RX_MAX_BUFF_PER_PKT 5
+#define ETH_RX_BD_THRESHOLD 12
-/* num of MAC/VLAN filters */
-#define ETH_NUM_MAC_FILTERS 512
-#define ETH_NUM_VLAN_FILTERS 512
+/* Num of MAC/VLAN filters */
+#define ETH_NUM_MAC_FILTERS 512
+#define ETH_NUM_VLAN_FILTERS 512
-/* approx. multicast constants */
-#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
-#define ETH_MULTICAST_MAC_BINS 256
-#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
+/* Approx. multicast constants */
+#define ETH_MULTICAST_BIN_FROM_MAC_SEED 0
+#define ETH_MULTICAST_MAC_BINS 256
+#define ETH_MULTICAST_MAC_BINS_IN_REGS (ETH_MULTICAST_MAC_BINS / 32)
-/* ethernet vport update constants */
-#define ETH_FILTER_RULES_COUNT 10
-#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
-#define ETH_RSS_KEY_SIZE_REGS 10
-#define ETH_RSS_ENGINE_NUM_K2 207
-#define ETH_RSS_ENGINE_NUM_BB 127
+/* Ethernet vport update constants */
+#define ETH_FILTER_RULES_COUNT 10
+#define ETH_RSS_IND_TABLE_ENTRIES_NUM 128
+#define ETH_RSS_KEY_SIZE_REGS 10
+#define ETH_RSS_ENGINE_NUM_K2 207
+#define ETH_RSS_ENGINE_NUM_BB 127
/* TPA constants */
-#define ETH_TPA_MAX_AGGS_NUM 64
-#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
-#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
-#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
+#define ETH_TPA_MAX_AGGS_NUM 64
+#define ETH_TPA_CQE_START_LEN_LIST_SIZE ETH_RX_MAX_BUFF_PER_PKT
+#define ETH_TPA_CQE_CONT_LEN_LIST_SIZE 6
+#define ETH_TPA_CQE_END_LEN_LIST_SIZE 4
/* Control frame check constants */
#define ETH_CTL_FRAME_ETH_TYPE_NUM 4
struct eth_tx_1st_bd_flags {
u8 bitfields;
-#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
-#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
-#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
-#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
-#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
-#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
-#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
-#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
-#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
+#define ETH_TX_1ST_BD_FLAGS_START_BD_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_START_BD_SHIFT 0
+#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_FORCE_VLAN_MODE_SHIFT 1
+#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_IP_CSUM_SHIFT 2
+#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_L4_CSUM_SHIFT 3
+#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_VLAN_INSERTION_SHIFT 4
+#define ETH_TX_1ST_BD_FLAGS_LSO_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_LSO_SHIFT 5
+#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_TUNN_IP_CSUM_SHIFT 6
+#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_MASK 0x1
+#define ETH_TX_1ST_BD_FLAGS_TUNN_L4_CSUM_SHIFT 7
};
-/* The parsing information data fo rthe first tx bd of a given packet. */
+/* The parsing information data fo rthe first tx bd of a given packet */
struct eth_tx_data_1st_bd {
__le16 vlan;
u8 nbds;
struct eth_tx_1st_bd_flags bd_flags;
__le16 bitfields;
-#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
-#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
-#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
-#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
-#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
-#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
+#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_MASK 0x1
+#define ETH_TX_DATA_1ST_BD_TUNN_FLAG_SHIFT 0
+#define ETH_TX_DATA_1ST_BD_RESERVED0_MASK 0x1
+#define ETH_TX_DATA_1ST_BD_RESERVED0_SHIFT 1
+#define ETH_TX_DATA_1ST_BD_PKT_LEN_MASK 0x3FFF
+#define ETH_TX_DATA_1ST_BD_PKT_LEN_SHIFT 2
};
-/* The parsing information data for the second tx bd of a given packet. */
+/* The parsing information data for the second tx bd of a given packet */
struct eth_tx_data_2nd_bd {
__le16 tunn_ip_size;
__le16 bitfields1;
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
-#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
-#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
-#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
-#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
-#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
-#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
-#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
-#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
-#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
-#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_MASK 0xF
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_L2_HDR_SIZE_W_SHIFT 0
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_MASK 0x3
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_ETH_TYPE_SHIFT 4
+#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_MASK 0x3
+#define ETH_TX_DATA_2ND_BD_DEST_PORT_MODE_SHIFT 6
+#define ETH_TX_DATA_2ND_BD_START_BD_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_START_BD_SHIFT 8
+#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_MASK 0x3
+#define ETH_TX_DATA_2ND_BD_TUNN_TYPE_SHIFT 9
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_TUNN_INNER_IPV6_SHIFT 11
+#define ETH_TX_DATA_2ND_BD_IPV6_EXT_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_IPV6_EXT_SHIFT 12
+#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_TUNN_IPV6_EXT_SHIFT 13
+#define ETH_TX_DATA_2ND_BD_L4_UDP_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_L4_UDP_SHIFT 14
+#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_MASK 0x1
+#define ETH_TX_DATA_2ND_BD_L4_PSEUDO_CSUM_MODE_SHIFT 15
__le16 bitfields2;
-#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
-#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
-#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
-#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
+#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_MASK 0x1FFF
+#define ETH_TX_DATA_2ND_BD_L4_HDR_START_OFFSET_W_SHIFT 0
+#define ETH_TX_DATA_2ND_BD_RESERVED0_MASK 0x7
+#define ETH_TX_DATA_2ND_BD_RESERVED0_SHIFT 13
};
-/* Firmware data for L2-EDPM packet. */
+/* Firmware data for L2-EDPM packet */
struct eth_edpm_fw_data {
struct eth_tx_data_1st_bd data_1st_bd;
struct eth_tx_data_2nd_bd data_2nd_bd;
@@ -179,7 +180,7 @@ struct eth_fast_path_cqe_fw_debug {
__le16 reserved2;
};
-/* tunneling parsing flags */
+/* Tunneling parsing flags */
struct eth_tunnel_parsing_flags {
u8 flags;
#define ETH_TUNNEL_PARSING_FLAGS_TYPE_MASK 0x3
@@ -199,24 +200,24 @@ struct eth_tunnel_parsing_flags {
/* PMD flow control bits */
struct eth_pmd_flow_flags {
u8 flags;
-#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
-#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
-#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
-#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
-#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
-#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
+#define ETH_PMD_FLOW_FLAGS_VALID_MASK 0x1
+#define ETH_PMD_FLOW_FLAGS_VALID_SHIFT 0
+#define ETH_PMD_FLOW_FLAGS_TOGGLE_MASK 0x1
+#define ETH_PMD_FLOW_FLAGS_TOGGLE_SHIFT 1
+#define ETH_PMD_FLOW_FLAGS_RESERVED_MASK 0x3F
+#define ETH_PMD_FLOW_FLAGS_RESERVED_SHIFT 2
};
-/* Regular ETH Rx FP CQE. */
+/* Regular ETH Rx FP CQE */
struct eth_fast_path_rx_reg_cqe {
u8 type;
u8 bitfields;
-#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
-#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
-#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
-#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
-#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
-#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
+#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_MASK 0x7
+#define ETH_FAST_PATH_RX_REG_CQE_RSS_HASH_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_REG_CQE_TC_MASK 0xF
+#define ETH_FAST_PATH_RX_REG_CQE_TC_SHIFT 3
+#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_MASK 0x1
+#define ETH_FAST_PATH_RX_REG_CQE_RESERVED0_SHIFT 7
__le16 pkt_len;
struct parsing_and_err_flags pars_flags;
__le16 vlan_tag;
@@ -231,7 +232,7 @@ struct eth_fast_path_rx_reg_cqe {
struct eth_pmd_flow_flags pmd_flags;
};
-/* TPA-continue ETH Rx FP CQE. */
+/* TPA-continue ETH Rx FP CQE */
struct eth_fast_path_rx_tpa_cont_cqe {
u8 type;
u8 tpa_agg_index;
@@ -243,7 +244,7 @@ struct eth_fast_path_rx_tpa_cont_cqe {
struct eth_pmd_flow_flags pmd_flags;
};
-/* TPA-end ETH Rx FP CQE. */
+/* TPA-end ETH Rx FP CQE */
struct eth_fast_path_rx_tpa_end_cqe {
u8 type;
u8 tpa_agg_index;
@@ -259,16 +260,16 @@ struct eth_fast_path_rx_tpa_end_cqe {
struct eth_pmd_flow_flags pmd_flags;
};
-/* TPA-start ETH Rx FP CQE. */
+/* TPA-start ETH Rx FP CQE */
struct eth_fast_path_rx_tpa_start_cqe {
u8 type;
u8 bitfields;
-#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
-#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
-#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
-#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
-#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
-#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
+#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_MASK 0x7
+#define ETH_FAST_PATH_RX_TPA_START_CQE_RSS_HASH_TYPE_SHIFT 0
+#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_MASK 0xF
+#define ETH_FAST_PATH_RX_TPA_START_CQE_TC_SHIFT 3
+#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_MASK 0x1
+#define ETH_FAST_PATH_RX_TPA_START_CQE_RESERVED0_SHIFT 7
__le16 seg_len;
struct parsing_and_err_flags pars_flags;
__le16 vlan_tag;
@@ -295,24 +296,24 @@ struct eth_rx_bd {
struct regpair addr;
};
-/* regular ETH Rx SP CQE */
+/* Regular ETH Rx SP CQE */
struct eth_slow_path_rx_cqe {
- u8 type;
- u8 ramrod_cmd_id;
- u8 error_flag;
- u8 reserved[25];
- __le16 echo;
- u8 reserved1;
+ u8 type;
+ u8 ramrod_cmd_id;
+ u8 error_flag;
+ u8 reserved[25];
+ __le16 echo;
+ u8 reserved1;
struct eth_pmd_flow_flags pmd_flags;
};
-/* union for all ETH Rx CQE types */
+/* Union for all ETH Rx CQE types */
union eth_rx_cqe {
- struct eth_fast_path_rx_reg_cqe fast_path_regular;
- struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
- struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
- struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
- struct eth_slow_path_rx_cqe slow_path;
+ struct eth_fast_path_rx_reg_cqe fast_path_regular;
+ struct eth_fast_path_rx_tpa_start_cqe fast_path_tpa_start;
+ struct eth_fast_path_rx_tpa_cont_cqe fast_path_tpa_cont;
+ struct eth_fast_path_rx_tpa_end_cqe fast_path_tpa_end;
+ struct eth_slow_path_rx_cqe slow_path;
};
/* ETH Rx CQE type */
@@ -339,7 +340,7 @@ enum eth_rx_tunn_type {
MAX_ETH_RX_TUNN_TYPE
};
-/* Aggregation end reason. */
+/* Aggregation end reason. */
enum eth_tpa_end_reason {
ETH_AGG_END_UNUSED,
ETH_AGG_END_SP_UPDATE,
@@ -354,59 +355,59 @@ enum eth_tpa_end_reason {
/* The first tx bd of a given packet */
struct eth_tx_1st_bd {
- struct regpair addr;
- __le16 nbytes;
- struct eth_tx_data_1st_bd data;
+ struct regpair addr;
+ __le16 nbytes;
+ struct eth_tx_data_1st_bd data;
};
/* The second tx bd of a given packet */
struct eth_tx_2nd_bd {
- struct regpair addr;
- __le16 nbytes;
- struct eth_tx_data_2nd_bd data;
+ struct regpair addr;
+ __le16 nbytes;
+ struct eth_tx_data_2nd_bd data;
};
-/* The parsing information data for the third tx bd of a given packet. */
+/* The parsing information data for the third tx bd of a given packet */
struct eth_tx_data_3rd_bd {
__le16 lso_mss;
__le16 bitfields;
-#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
-#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
-#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
-#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
-#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
-#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
-#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
-#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
+#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_MASK 0xF
+#define ETH_TX_DATA_3RD_BD_TCP_HDR_LEN_DW_SHIFT 0
+#define ETH_TX_DATA_3RD_BD_HDR_NBD_MASK 0xF
+#define ETH_TX_DATA_3RD_BD_HDR_NBD_SHIFT 4
+#define ETH_TX_DATA_3RD_BD_START_BD_MASK 0x1
+#define ETH_TX_DATA_3RD_BD_START_BD_SHIFT 8
+#define ETH_TX_DATA_3RD_BD_RESERVED0_MASK 0x7F
+#define ETH_TX_DATA_3RD_BD_RESERVED0_SHIFT 9
u8 tunn_l4_hdr_start_offset_w;
u8 tunn_hdr_size_w;
};
/* The third tx bd of a given packet */
struct eth_tx_3rd_bd {
- struct regpair addr;
- __le16 nbytes;
- struct eth_tx_data_3rd_bd data;
+ struct regpair addr;
+ __le16 nbytes;
+ struct eth_tx_data_3rd_bd data;
};
-/* Complementary information for the regular tx bd of a given packet. */
+/* Complementary information for the regular tx bd of a given packet */
struct eth_tx_data_bd {
- __le16 reserved0;
- __le16 bitfields;
-#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
-#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
-#define ETH_TX_DATA_BD_START_BD_MASK 0x1
-#define ETH_TX_DATA_BD_START_BD_SHIFT 8
-#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
-#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
+ __le16 reserved0;
+ __le16 bitfields;
+#define ETH_TX_DATA_BD_RESERVED1_MASK 0xFF
+#define ETH_TX_DATA_BD_RESERVED1_SHIFT 0
+#define ETH_TX_DATA_BD_START_BD_MASK 0x1
+#define ETH_TX_DATA_BD_START_BD_SHIFT 8
+#define ETH_TX_DATA_BD_RESERVED2_MASK 0x7F
+#define ETH_TX_DATA_BD_RESERVED2_SHIFT 9
__le16 reserved3;
};
/* The common non-special TX BD ring element */
struct eth_tx_bd {
- struct regpair addr;
- __le16 nbytes;
- struct eth_tx_data_bd data;
+ struct regpair addr;
+ __le16 nbytes;
+ struct eth_tx_data_bd data;
};
union eth_tx_bd_types {
@@ -434,18 +435,30 @@ struct xstorm_eth_queue_zone {
/* ETH doorbell data */
struct eth_db_data {
u8 params;
-#define ETH_DB_DATA_DEST_MASK 0x3
-#define ETH_DB_DATA_DEST_SHIFT 0
-#define ETH_DB_DATA_AGG_CMD_MASK 0x3
-#define ETH_DB_DATA_AGG_CMD_SHIFT 2
-#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
-#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
-#define ETH_DB_DATA_RESERVED_MASK 0x1
-#define ETH_DB_DATA_RESERVED_SHIFT 5
-#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
-#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
+#define ETH_DB_DATA_DEST_MASK 0x3
+#define ETH_DB_DATA_DEST_SHIFT 0
+#define ETH_DB_DATA_AGG_CMD_MASK 0x3
+#define ETH_DB_DATA_AGG_CMD_SHIFT 2
+#define ETH_DB_DATA_BYPASS_EN_MASK 0x1
+#define ETH_DB_DATA_BYPASS_EN_SHIFT 4
+#define ETH_DB_DATA_RESERVED_MASK 0x1
+#define ETH_DB_DATA_RESERVED_SHIFT 5
+#define ETH_DB_DATA_AGG_VAL_SEL_MASK 0x3
+#define ETH_DB_DATA_AGG_VAL_SEL_SHIFT 6
u8 agg_flags;
__le16 bd_prod;
};
+/* RSS hash type */
+enum rss_hash_type {
+ RSS_HASH_TYPE_DEFAULT = 0,
+ RSS_HASH_TYPE_IPV4 = 1,
+ RSS_HASH_TYPE_TCP_IPV4 = 2,
+ RSS_HASH_TYPE_IPV6 = 3,
+ RSS_HASH_TYPE_TCP_IPV6 = 4,
+ RSS_HASH_TYPE_UDP_IPV4 = 5,
+ RSS_HASH_TYPE_UDP_IPV6 = 6,
+ MAX_RSS_HASH_TYPE
+};
+
#endif /* __ETH_COMMON__ */
diff --git a/include/linux/qed/fcoe_common.h b/include/linux/qed/fcoe_common.h
index 12fc9e7..e720a7b 100644
--- a/include/linux/qed/fcoe_common.h
+++ b/include/linux/qed/fcoe_common.h
@@ -8,12 +8,298 @@
#ifndef __FCOE_COMMON__
#define __FCOE_COMMON__
+
/*********************/
/* FCOE FW CONSTANTS */
/*********************/
#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12
+/* The fcoe storm task context protection-information of Ystorm */
+struct protection_info_ctx {
+ __le16 flags;
+#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
+#define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0
+#define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
+#define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2
+#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
+#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
+#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF
+#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
+#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
+#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
+#define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F
+#define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9
+ u8 dix_block_size;
+ u8 dst_size;
+};
+
+/* The fcoe storm task context protection-information of Ystorm */
+union protection_info_union_ctx {
+ struct protection_info_ctx info;
+ __le32 value;
+};
+
+/* FCP CMD payload */
+struct fcoe_fcp_cmd_payload {
+ __le32 opaque[8];
+};
+
+/* FCP RSP payload */
+struct fcoe_fcp_rsp_payload {
+ __le32 opaque[6];
+};
+
+/* FCP RSP payload */
+struct fcp_rsp_payload_padded {
+ struct fcoe_fcp_rsp_payload rsp_payload;
+ __le32 reserved[2];
+};
+
+/* FCP RSP payload */
+struct fcoe_fcp_xfer_payload {
+ __le32 opaque[3];
+};
+
+/* FCP RSP payload */
+struct fcp_xfer_payload_padded {
+ struct fcoe_fcp_xfer_payload xfer_payload;
+ __le32 reserved[5];
+};
+
+/* Task params */
+struct fcoe_tx_data_params {
+ __le32 data_offset;
+ __le32 offset_in_io;
+ u8 flags;
+#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1
+#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
+#define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1
+#define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1
+#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1
+#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2
+#define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F
+#define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
+ u8 dif_residual;
+ __le16 seq_cnt;
+ __le16 single_sge_saved_offset;
+ __le16 next_dif_offset;
+ __le16 seq_id;
+ __le16 reserved3;
+};
+
+/* Middle path parameters: FC header fields provided by the driver */
+struct fcoe_tx_mid_path_params {
+ __le32 parameter;
+ u8 r_ctl;
+ u8 type;
+ u8 cs_ctl;
+ u8 df_ctl;
+ __le16 rx_id;
+ __le16 ox_id;
+};
+
+/* Task params */
+struct fcoe_tx_params {
+ struct fcoe_tx_data_params data;
+ struct fcoe_tx_mid_path_params mid_path;
+};
+
+/* Union of FCP CMD payload \ TX params \ ABTS \ Cleanup */
+union fcoe_tx_info_union_ctx {
+ struct fcoe_fcp_cmd_payload fcp_cmd_payload;
+ struct fcp_rsp_payload_padded fcp_rsp_payload;
+ struct fcp_xfer_payload_padded fcp_xfer_payload;
+ struct fcoe_tx_params tx_params;
+};
+
+/* Data sgl */
+struct fcoe_slow_sgl_ctx {
+ struct regpair base_sgl_addr;
+ __le16 curr_sge_off;
+ __le16 remainder_num_sges;
+ __le16 curr_sgl_index;
+ __le16 reserved;
+};
+
+/* Union of DIX SGL \ cached DIX sges */
+union fcoe_dix_desc_ctx {
+ struct fcoe_slow_sgl_ctx dix_sgl;
+ struct scsi_sge cached_dix_sge;
+};
+
+/* The fcoe storm task context of Ystorm */
+struct ystorm_fcoe_task_st_ctx {
+ u8 task_type;
+ u8 sgl_mode;
+#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
+#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
+#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F
+#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1
+ u8 cached_dix_sge;
+ u8 expect_first_xfer;
+ __le32 num_pbf_zero_write;
+ union protection_info_union_ctx protection_info_union;
+ __le32 data_2_trns_rem;
+ struct scsi_sgl_params sgl_params;
+ u8 reserved1[12];
+ union fcoe_tx_info_union_ctx tx_info_union;
+ union fcoe_dix_desc_ctx dix_desc;
+ struct scsi_cached_sges data_desc;
+ __le16 ox_id;
+ __le16 rx_id;
+ __le32 task_rety_identifier;
+ u8 reserved2[8];
+};
+
+struct ystorm_fcoe_task_ag_ctx {
+ u8 byte0;
+ u8 byte1;
+ __le16 word0;
+ u8 flags0;
+#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
+#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
+#define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
+#define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
+#define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
+#define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
+ u8 flags1;
+#define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
+#define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
+#define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
+#define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
+#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
+#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
+#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
+#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
+ u8 flags2;
+#define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
+#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
+ u8 byte2;
+ __le32 reg0;
+ u8 byte3;
+ u8 byte4;
+ __le16 rx_id;
+ __le16 word2;
+ __le16 word3;
+ __le16 word4;
+ __le16 word5;
+ __le32 reg1;
+ __le32 reg2;
+};
+
+struct tstorm_fcoe_task_ag_ctx {
+ u8 reserved;
+ u8 byte1;
+ __le16 icid;
+ u8 flags0;
+#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
+#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
+#define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
+ u8 flags1;
+#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
+#define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
+#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
+#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
+#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
+#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
+#define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
+#define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
+ u8 flags2;
+#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
+#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
+#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
+#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
+#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
+#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
+#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
+#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
+ u8 flags3;
+#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
+#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
+#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
+#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
+#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
+#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
+#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
+#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
+ u8 flags4;
+#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
+#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
+#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
+#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
+#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
+#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
+#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
+#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
+ u8 cleanup_state;
+ __le16 last_sent_tid;
+ __le32 rec_rr_tov_exp_timeout;
+ u8 byte3;
+ u8 byte4;
+ __le16 word2;
+ __le16 word3;
+ __le16 word4;
+ __le32 data_offset_end_of_seq;
+ __le32 data_offset_next;
+};
+
+/* Cached data sges */
+struct fcoe_exp_ro {
+ __le32 data_offset;
+ __le32 reserved;
+};
+
+/* Union of Cleanup address \ expected relative offsets */
+union fcoe_cleanup_addr_exp_ro_union {
+ struct regpair abts_rsp_fc_payload_hi;
+ struct fcoe_exp_ro exp_ro;
+};
+
+/* Fields coppied from ABTSrsp pckt */
struct fcoe_abts_pkt {
__le32 abts_rsp_fc_payload_lo;
__le16 abts_rsp_rx_id;
@@ -21,6 +307,215 @@ struct fcoe_abts_pkt {
u8 reserved2;
};
+/* FW read- write (modifyable) part The fcoe task storm context of Tstorm */
+struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
+ union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union;
+ __le16 flags;
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF
+#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8
+ __le16 seq_cnt;
+ u8 seq_id;
+ u8 ooo_rx_seq_id;
+ __le16 rx_id;
+ struct fcoe_abts_pkt abts_data;
+ __le32 e_d_tov_exp_timeout_val;
+ __le16 ooo_rx_seq_cnt;
+ __le16 reserved1;
+};
+
+/* FW read only part The fcoe task storm context of Tstorm */
+struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
+ u8 task_type;
+ u8 dev_type;
+ u8 conf_supported;
+ u8 glbl_q_num;
+ __le32 cid;
+ __le32 fcp_cmd_trns_size;
+ __le32 rsrv;
+};
+
+/** The fcoe task storm context of Tstorm */
+struct tstorm_fcoe_task_st_ctx {
+ struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write;
+ struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
+};
+
+struct mstorm_fcoe_task_ag_ctx {
+ u8 byte0;
+ u8 byte1;
+ __le16 icid;
+ u8 flags0;
+#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
+#define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
+#define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
+ u8 flags1;
+#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
+#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
+#define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
+#define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
+#define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
+#define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
+#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
+#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
+ u8 flags2;
+#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
+#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
+#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
+ u8 cleanup_state;
+ __le32 received_bytes;
+ u8 byte3;
+ u8 glbl_q_num;
+ __le16 word1;
+ __le16 tid_to_xfer;
+ __le16 word3;
+ __le16 word4;
+ __le16 word5;
+ __le32 expected_bytes;
+ __le32 reg2;
+};
+
+/* The fcoe task storm context of Mstorm */
+struct mstorm_fcoe_task_st_ctx {
+ struct regpair rsp_buf_addr;
+ __le32 rsrv[2];
+ struct scsi_sgl_params sgl_params;
+ __le32 data_2_trns_rem;
+ __le32 data_buffer_offset;
+ __le16 parent_id;
+ __le16 flags;
+#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF
+#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0
+#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3
+#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4
+#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6
+#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7
+#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3
+#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8
+#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10
+#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11
+#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12
+#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
+#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13
+#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3
+#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14
+ struct scsi_cached_sges data_desc;
+};
+
+struct ustorm_fcoe_task_ag_ctx {
+ u8 reserved;
+ u8 byte1;
+ __le16 icid;
+ u8 flags0;
+#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
+#define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
+#define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
+ u8 flags1;
+#define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
+#define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
+#define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
+#define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
+#define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
+#define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
+#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
+#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
+ u8 flags2;
+#define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
+#define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
+#define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
+#define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
+#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
+#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
+#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
+#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
+ u8 flags3;
+#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
+#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
+#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
+#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
+#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
+#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
+ __le32 dif_err_intervals;
+ __le32 dif_error_1st_interval;
+ __le32 global_cq_num;
+ __le32 reg3;
+ __le32 reg4;
+ __le32 reg5;
+};
+
+/* FCoE task context */
+struct fcoe_task_context {
+ struct ystorm_fcoe_task_st_ctx ystorm_st_context;
+ struct regpair ystorm_st_padding[2];
+ struct tdif_task_context tdif_context;
+ struct ystorm_fcoe_task_ag_ctx ystorm_ag_context;
+ struct tstorm_fcoe_task_ag_ctx tstorm_ag_context;
+ struct timers_context timer_context;
+ struct tstorm_fcoe_task_st_ctx tstorm_st_context;
+ struct regpair tstorm_st_padding[2];
+ struct mstorm_fcoe_task_ag_ctx mstorm_ag_context;
+ struct mstorm_fcoe_task_st_ctx mstorm_st_context;
+ struct ustorm_fcoe_task_ag_ctx ustorm_ag_context;
+ struct rdif_task_context rdif_context;
+};
+
/* FCoE additional WQE (Sq/XferQ) information */
union fcoe_additional_info_union {
__le32 previous_tid;
@@ -29,16 +524,6 @@ union fcoe_additional_info_union {
__le32 seq_rec_updated_offset;
};
-struct fcoe_exp_ro {
- __le32 data_offset;
- __le32 reserved;
-};
-
-union fcoe_cleanup_addr_exp_ro_union {
- struct regpair abts_rsp_fc_payload_hi;
- struct fcoe_exp_ro exp_ro;
-};
-
/* FCoE Ramrod Command IDs */
enum fcoe_completion_status {
FCOE_COMPLETION_STATUS_SUCCESS,
@@ -47,6 +532,7 @@ enum fcoe_completion_status {
MAX_FCOE_COMPLETION_STATUS
};
+/* FC address (SID/DID) network presentation */
struct fc_addr_nw {
u8 addr_lo;
u8 addr_mid;
@@ -74,30 +560,30 @@ struct fcoe_conn_offload_ramrod_data {
__le16 e_d_tov_timer_val;
__le16 rx_max_fc_pay_len;
__le16 vlan_tag;
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13
__le16 physical_q0;
__le16 rec_rr_tov_timer_val;
struct fc_addr_nw s_id;
u8 max_conc_seqs_c3;
struct fc_addr_nw d_id;
u8 flags;
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3
-#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 4
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x3
+#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 6
__le16 conn_id;
u8 def_q_idx;
u8 reserved[5];
@@ -108,19 +594,7 @@ struct fcoe_conn_terminate_ramrod_data {
struct regpair terminate_params_addr;
};
-struct fcoe_slow_sgl_ctx {
- struct regpair base_sgl_addr;
- __le16 curr_sge_off;
- __le16 remainder_num_sges;
- __le16 curr_sgl_index;
- __le16 reserved;
-};
-
-union fcoe_dix_desc_ctx {
- struct fcoe_slow_sgl_ctx dix_sgl;
- struct scsi_sge cached_dix_sge;
-};
-
+/* Data sgl */
struct fcoe_fast_sgl_ctx {
struct regpair sgl_start_addr;
__le32 sgl_byte_offset;
@@ -128,18 +602,6 @@ struct fcoe_fast_sgl_ctx {
__le16 init_offset_in_first_sge;
};
-struct fcoe_fcp_cmd_payload {
- __le32 opaque[8];
-};
-
-struct fcoe_fcp_rsp_payload {
- __le32 opaque[6];
-};
-
-struct fcoe_fcp_xfer_payload {
- __le32 opaque[3];
-};
-
/* FCoE firmware function init */
struct fcoe_init_func_ramrod_data {
struct scsi_init_func_params func_params;
@@ -157,6 +619,7 @@ enum fcoe_mode_type {
MAX_FCOE_MODE_TYPE
};
+/* Per PF FCoE receive path statistics - tStorm RAM structure */
struct fcoe_rx_stat {
struct regpair fcoe_rx_byte_cnt;
struct regpair fcoe_rx_data_pkt_cnt;
@@ -170,447 +633,12 @@ struct fcoe_rx_stat {
__le32 rsrv;
};
+/* FCoe statistics request */
struct fcoe_stat_ramrod_data {
struct regpair stat_params_addr;
};
-struct protection_info_ctx {
- __le16 flags;
-#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3
-#define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0
-#define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1
-#define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2
-#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1
-#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3
-#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF
-#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4
-#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
-#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8
-#define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F
-#define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9
- u8 dix_block_size;
- u8 dst_size;
-};
-
-union protection_info_union_ctx {
- struct protection_info_ctx info;
- __le32 value;
-};
-
-struct fcp_rsp_payload_padded {
- struct fcoe_fcp_rsp_payload rsp_payload;
- __le32 reserved[2];
-};
-
-struct fcp_xfer_payload_padded {
- struct fcoe_fcp_xfer_payload xfer_payload;
- __le32 reserved[5];
-};
-
-struct fcoe_tx_data_params {
- __le32 data_offset;
- __le32 offset_in_io;
- u8 flags;
-#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1
-#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0
-#define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1
-#define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1
-#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1
-#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2
-#define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F
-#define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3
- u8 dif_residual;
- __le16 seq_cnt;
- __le16 single_sge_saved_offset;
- __le16 next_dif_offset;
- __le16 seq_id;
- __le16 reserved3;
-};
-
-struct fcoe_tx_mid_path_params {
- __le32 parameter;
- u8 r_ctl;
- u8 type;
- u8 cs_ctl;
- u8 df_ctl;
- __le16 rx_id;
- __le16 ox_id;
-};
-
-struct fcoe_tx_params {
- struct fcoe_tx_data_params data;
- struct fcoe_tx_mid_path_params mid_path;
-};
-
-union fcoe_tx_info_union_ctx {
- struct fcoe_fcp_cmd_payload fcp_cmd_payload;
- struct fcp_rsp_payload_padded fcp_rsp_payload;
- struct fcp_xfer_payload_padded fcp_xfer_payload;
- struct fcoe_tx_params tx_params;
-};
-
-struct ystorm_fcoe_task_st_ctx {
- u8 task_type;
- u8 sgl_mode;
-#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
-#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0
-#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F
-#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1
- u8 cached_dix_sge;
- u8 expect_first_xfer;
- __le32 num_pbf_zero_write;
- union protection_info_union_ctx protection_info_union;
- __le32 data_2_trns_rem;
- struct scsi_sgl_params sgl_params;
- u8 reserved1[12];
- union fcoe_tx_info_union_ctx tx_info_union;
- union fcoe_dix_desc_ctx dix_desc;
- struct scsi_cached_sges data_desc;
- __le16 ox_id;
- __le16 rx_id;
- __le32 task_rety_identifier;
- u8 reserved2[8];
-};
-
-struct ystorm_fcoe_task_ag_ctx {
- u8 byte0;
- u8 byte1;
- __le16 word0;
- u8 flags0;
-#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF
-#define YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0
-#define YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4
-#define YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
-#define YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
-#define YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
- u8 flags1;
-#define YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
-#define YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0
-#define YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
-#define YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
-#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
-#define YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
-#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6
-#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
- u8 flags2;
-#define YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0
-#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
- u8 byte2;
- __le32 reg0;
- u8 byte3;
- u8 byte4;
- __le16 rx_id;
- __le16 word2;
- __le16 word3;
- __le16 word4;
- __le16 word5;
- __le32 reg1;
- __le32 reg2;
-};
-
-struct tstorm_fcoe_task_ag_ctx {
- u8 reserved;
- u8 byte1;
- __le16 icid;
- u8 flags0;
-#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
-#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6
-#define TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7
- u8 flags1;
-#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6
- u8 flags2;
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6
- u8 flags3;
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3
-#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7
- u8 flags4;
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2
-#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3
-#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4
-#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5
-#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6
-#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7
- u8 cleanup_state;
- __le16 last_sent_tid;
- __le32 rec_rr_tov_exp_timeout;
- u8 byte3;
- u8 byte4;
- __le16 word2;
- __le16 word3;
- __le16 word4;
- __le32 data_offset_end_of_seq;
- __le32 data_offset_next;
-};
-
-struct fcoe_tstorm_fcoe_task_st_ctx_read_write {
- union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union;
- __le16 flags;
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF
-#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8
- __le16 seq_cnt;
- u8 seq_id;
- u8 ooo_rx_seq_id;
- __le16 rx_id;
- struct fcoe_abts_pkt abts_data;
- __le32 e_d_tov_exp_timeout_val;
- __le16 ooo_rx_seq_cnt;
- __le16 reserved1;
-};
-
-struct fcoe_tstorm_fcoe_task_st_ctx_read_only {
- u8 task_type;
- u8 dev_type;
- u8 conf_supported;
- u8 glbl_q_num;
- __le32 cid;
- __le32 fcp_cmd_trns_size;
- __le32 rsrv;
-};
-
-struct tstorm_fcoe_task_st_ctx {
- struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write;
- struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only;
-};
-
-struct mstorm_fcoe_task_ag_ctx {
- u8 byte0;
- u8 byte1;
- __le16 icid;
- u8 flags0;
-#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5
-#define MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6
-#define MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7
- u8 flags1;
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0
-#define MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
-#define MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2
-#define MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
-#define MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6
-#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7
- u8 flags2;
-#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0
-#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6
-#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7
- u8 cleanup_state;
- __le32 received_bytes;
- u8 byte3;
- u8 glbl_q_num;
- __le16 word1;
- __le16 tid_to_xfer;
- __le16 word3;
- __le16 word4;
- __le16 word5;
- __le32 expected_bytes;
- __le32 reg2;
-};
-
-struct mstorm_fcoe_task_st_ctx {
- struct regpair rsp_buf_addr;
- __le32 rsrv[2];
- struct scsi_sgl_params sgl_params;
- __le32 data_2_trns_rem;
- __le32 data_buffer_offset;
- __le16 parent_id;
- __le16 flags;
-#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF
-#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0
-#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3
-#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4
-#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6
-#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7
-#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3
-#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8
-#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10
-#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11
-#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12
-#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1
-#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13
-#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3
-#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14
- struct scsi_cached_sges data_desc;
-};
-
-struct ustorm_fcoe_task_ag_ctx {
- u8 reserved;
- u8 byte1;
- __le16 icid;
- u8 flags0;
-#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5
-#define USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6
- u8 flags1;
-#define USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2
-#define USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
- u8 flags2;
-#define USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1
-#define USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2
-#define USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
-#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5
-#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6
-#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7
- u8 flags3;
-#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0
-#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1
-#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2
-#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
-#define USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
- __le32 dif_err_intervals;
- __le32 dif_error_1st_interval;
- __le32 global_cq_num;
- __le32 reg3;
- __le32 reg4;
- __le32 reg5;
-};
-
-struct fcoe_task_context {
- struct ystorm_fcoe_task_st_ctx ystorm_st_context;
- struct regpair ystorm_st_padding[2];
- struct tdif_task_context tdif_context;
- struct ystorm_fcoe_task_ag_ctx ystorm_ag_context;
- struct tstorm_fcoe_task_ag_ctx tstorm_ag_context;
- struct timers_context timer_context;
- struct tstorm_fcoe_task_st_ctx tstorm_st_context;
- struct regpair tstorm_st_padding[2];
- struct mstorm_fcoe_task_ag_ctx mstorm_ag_context;
- struct mstorm_fcoe_task_st_ctx mstorm_st_context;
- struct ustorm_fcoe_task_ag_ctx ustorm_ag_context;
- struct rdif_task_context rdif_context;
-};
-
+/* Per PF FCoE transmit path statistics - pStorm RAM structure */
struct fcoe_tx_stat {
struct regpair fcoe_tx_byte_cnt;
struct regpair fcoe_tx_data_pkt_cnt;
@@ -618,51 +646,55 @@ struct fcoe_tx_stat {
struct regpair fcoe_tx_other_pkt_cnt;
};
+/* FCoE SQ/XferQ element */
struct fcoe_wqe {
__le16 task_id;
__le16 flags;
-#define FCOE_WQE_REQ_TYPE_MASK 0xF
-#define FCOE_WQE_REQ_TYPE_SHIFT 0
-#define FCOE_WQE_SGL_MODE_MASK 0x1
-#define FCOE_WQE_SGL_MODE_SHIFT 4
-#define FCOE_WQE_CONTINUATION_MASK 0x1
-#define FCOE_WQE_CONTINUATION_SHIFT 5
-#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1
-#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6
-#define FCOE_WQE_RESERVED_MASK 0x1
-#define FCOE_WQE_RESERVED_SHIFT 7
-#define FCOE_WQE_NUM_SGES_MASK 0xF
-#define FCOE_WQE_NUM_SGES_SHIFT 8
-#define FCOE_WQE_RESERVED1_MASK 0xF
-#define FCOE_WQE_RESERVED1_SHIFT 12
+#define FCOE_WQE_REQ_TYPE_MASK 0xF
+#define FCOE_WQE_REQ_TYPE_SHIFT 0
+#define FCOE_WQE_SGL_MODE_MASK 0x1
+#define FCOE_WQE_SGL_MODE_SHIFT 4
+#define FCOE_WQE_CONTINUATION_MASK 0x1
+#define FCOE_WQE_CONTINUATION_SHIFT 5
+#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1
+#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6
+#define FCOE_WQE_RESERVED_MASK 0x1
+#define FCOE_WQE_RESERVED_SHIFT 7
+#define FCOE_WQE_NUM_SGES_MASK 0xF
+#define FCOE_WQE_NUM_SGES_SHIFT 8
+#define FCOE_WQE_RESERVED1_MASK 0xF
+#define FCOE_WQE_RESERVED1_SHIFT 12
union fcoe_additional_info_union additional_info_union;
};
+/* FCoE XFRQ element */
struct xfrqe_prot_flags {
u8 flags;
-#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
-#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
-#define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1
-#define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4
-#define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3
-#define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5
-#define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1
-#define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7
+#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
+#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
+#define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1
+#define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4
+#define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3
+#define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5
+#define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1
+#define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7
};
+/* FCoE doorbell data */
struct fcoe_db_data {
u8 params;
-#define FCOE_DB_DATA_DEST_MASK 0x3
-#define FCOE_DB_DATA_DEST_SHIFT 0
-#define FCOE_DB_DATA_AGG_CMD_MASK 0x3
-#define FCOE_DB_DATA_AGG_CMD_SHIFT 2
-#define FCOE_DB_DATA_BYPASS_EN_MASK 0x1
-#define FCOE_DB_DATA_BYPASS_EN_SHIFT 4
-#define FCOE_DB_DATA_RESERVED_MASK 0x1
-#define FCOE_DB_DATA_RESERVED_SHIFT 5
-#define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
-#define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
+#define FCOE_DB_DATA_DEST_MASK 0x3
+#define FCOE_DB_DATA_DEST_SHIFT 0
+#define FCOE_DB_DATA_AGG_CMD_MASK 0x3
+#define FCOE_DB_DATA_AGG_CMD_SHIFT 2
+#define FCOE_DB_DATA_BYPASS_EN_MASK 0x1
+#define FCOE_DB_DATA_BYPASS_EN_SHIFT 4
+#define FCOE_DB_DATA_RESERVED_MASK 0x1
+#define FCOE_DB_DATA_RESERVED_SHIFT 5
+#define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3
+#define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6
u8 agg_flags;
__le16 sq_prod;
};
+
#endif /* __FCOE_COMMON__ */
diff --git a/include/linux/qed/iscsi_common.h b/include/linux/qed/iscsi_common.h
index 85e086c..b8f8350 100644
--- a/include/linux/qed/iscsi_common.h
+++ b/include/linux/qed/iscsi_common.h
@@ -32,47 +32,48 @@
#ifndef __ISCSI_COMMON__
#define __ISCSI_COMMON__
+
/**********************/
/* ISCSI FW CONSTANTS */
/**********************/
/* iSCSI HSI constants */
-#define ISCSI_DEFAULT_MTU (1500)
+#define ISCSI_DEFAULT_MTU (1500)
/* KWQ (kernel work queue) layer codes */
-#define ISCSI_SLOW_PATH_LAYER_CODE (6)
+#define ISCSI_SLOW_PATH_LAYER_CODE (6)
/* iSCSI parameter defaults */
-#define ISCSI_DEFAULT_HEADER_DIGEST (0)
-#define ISCSI_DEFAULT_DATA_DIGEST (0)
-#define ISCSI_DEFAULT_INITIAL_R2T (1)
-#define ISCSI_DEFAULT_IMMEDIATE_DATA (1)
-#define ISCSI_DEFAULT_MAX_PDU_LENGTH (0x2000)
-#define ISCSI_DEFAULT_FIRST_BURST_LENGTH (0x10000)
-#define ISCSI_DEFAULT_MAX_BURST_LENGTH (0x40000)
-#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)
+#define ISCSI_DEFAULT_HEADER_DIGEST (0)
+#define ISCSI_DEFAULT_DATA_DIGEST (0)
+#define ISCSI_DEFAULT_INITIAL_R2T (1)
+#define ISCSI_DEFAULT_IMMEDIATE_DATA (1)
+#define ISCSI_DEFAULT_MAX_PDU_LENGTH (0x2000)
+#define ISCSI_DEFAULT_FIRST_BURST_LENGTH (0x10000)
+#define ISCSI_DEFAULT_MAX_BURST_LENGTH (0x40000)
+#define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)
/* iSCSI parameter limits */
-#define ISCSI_MIN_VAL_MAX_PDU_LENGTH (0x200)
-#define ISCSI_MAX_VAL_MAX_PDU_LENGTH (0xffffff)
-#define ISCSI_MIN_VAL_BURST_LENGTH (0x200)
-#define ISCSI_MAX_VAL_BURST_LENGTH (0xffffff)
-#define ISCSI_MIN_VAL_MAX_OUTSTANDING_R2T (1)
-#define ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T (0xff)
+#define ISCSI_MIN_VAL_MAX_PDU_LENGTH (0x200)
+#define ISCSI_MAX_VAL_MAX_PDU_LENGTH (0xffffff)
+#define ISCSI_MIN_VAL_BURST_LENGTH (0x200)
+#define ISCSI_MAX_VAL_BURST_LENGTH (0xffffff)
+#define ISCSI_MIN_VAL_MAX_OUTSTANDING_R2T (1)
+#define ISCSI_MAX_VAL_MAX_OUTSTANDING_R2T (0xff)
-#define ISCSI_AHS_CNTL_SIZE 4
+#define ISCSI_AHS_CNTL_SIZE 4
-#define ISCSI_WQE_NUM_SGES_SLOWIO (0xf)
+#define ISCSI_WQE_NUM_SGES_SLOWIO (0xf)
/* iSCSI reserved params */
#define ISCSI_ITT_ALL_ONES (0xffffffff)
#define ISCSI_TTT_ALL_ONES (0xffffffff)
-#define ISCSI_OPTION_1_OFF_CHIP_TCP 1
-#define ISCSI_OPTION_2_ON_CHIP_TCP 2
+#define ISCSI_OPTION_1_OFF_CHIP_TCP 1
+#define ISCSI_OPTION_2_ON_CHIP_TCP 2
-#define ISCSI_INITIATOR_MODE 0
-#define ISCSI_TARGET_MODE 1
+#define ISCSI_INITIATOR_MODE 0
+#define ISCSI_TARGET_MODE 1
/* iSCSI request op codes */
#define ISCSI_OPCODE_NOP_OUT (0)
@@ -84,41 +85,42 @@
#define ISCSI_OPCODE_LOGOUT_REQUEST (6)
/* iSCSI response/messages op codes */
-#define ISCSI_OPCODE_NOP_IN (0x20)
-#define ISCSI_OPCODE_SCSI_RESPONSE (0x21)
-#define ISCSI_OPCODE_TMF_RESPONSE (0x22)
-#define ISCSI_OPCODE_LOGIN_RESPONSE (0x23)
-#define ISCSI_OPCODE_TEXT_RESPONSE (0x24)
-#define ISCSI_OPCODE_DATA_IN (0x25)
-#define ISCSI_OPCODE_LOGOUT_RESPONSE (0x26)
-#define ISCSI_OPCODE_R2T (0x31)
-#define ISCSI_OPCODE_ASYNC_MSG (0x32)
-#define ISCSI_OPCODE_REJECT (0x3f)
+#define ISCSI_OPCODE_NOP_IN (0x20)
+#define ISCSI_OPCODE_SCSI_RESPONSE (0x21)
+#define ISCSI_OPCODE_TMF_RESPONSE (0x22)
+#define ISCSI_OPCODE_LOGIN_RESPONSE (0x23)
+#define ISCSI_OPCODE_TEXT_RESPONSE (0x24)
+#define ISCSI_OPCODE_DATA_IN (0x25)
+#define ISCSI_OPCODE_LOGOUT_RESPONSE (0x26)
+#define ISCSI_OPCODE_R2T (0x31)
+#define ISCSI_OPCODE_ASYNC_MSG (0x32)
+#define ISCSI_OPCODE_REJECT (0x3f)
/* iSCSI stages */
-#define ISCSI_STAGE_SECURITY_NEGOTIATION (0)
-#define ISCSI_STAGE_LOGIN_OPERATIONAL_NEGOTIATION (1)
-#define ISCSI_STAGE_FULL_FEATURE_PHASE (3)
+#define ISCSI_STAGE_SECURITY_NEGOTIATION (0)
+#define ISCSI_STAGE_LOGIN_OPERATIONAL_NEGOTIATION (1)
+#define ISCSI_STAGE_FULL_FEATURE_PHASE (3)
/* iSCSI CQE errors */
-#define CQE_ERROR_BITMAP_DATA_DIGEST (0x08)
-#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN (0x10)
-#define CQE_ERROR_BITMAP_DATA_TRUNCATED (0x20)
+#define CQE_ERROR_BITMAP_DATA_DIGEST (0x08)
+#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN (0x10)
+#define CQE_ERROR_BITMAP_DATA_TRUNCATED (0x20)
+/* ISCSI SGL entry */
struct cqe_error_bitmap {
u8 cqe_error_status_bits;
-#define CQE_ERROR_BITMAP_DIF_ERR_BITS_MASK 0x7
-#define CQE_ERROR_BITMAP_DIF_ERR_BITS_SHIFT 0
-#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_MASK 0x1
-#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_SHIFT 3
-#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_MASK 0x1
-#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_SHIFT 4
-#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_MASK 0x1
-#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_SHIFT 5
-#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_MASK 0x1
-#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_SHIFT 6
-#define CQE_ERROR_BITMAP_RESERVED2_MASK 0x1
-#define CQE_ERROR_BITMAP_RESERVED2_SHIFT 7
+#define CQE_ERROR_BITMAP_DIF_ERR_BITS_MASK 0x7
+#define CQE_ERROR_BITMAP_DIF_ERR_BITS_SHIFT 0
+#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_MASK 0x1
+#define CQE_ERROR_BITMAP_DATA_DIGEST_ERR_SHIFT 3
+#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_MASK 0x1
+#define CQE_ERROR_BITMAP_RCV_ON_INVALID_CONN_SHIFT 4
+#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_MASK 0x1
+#define CQE_ERROR_BITMAP_DATA_TRUNCATED_ERR_SHIFT 5
+#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_MASK 0x1
+#define CQE_ERROR_BITMAP_UNDER_RUN_ERR_SHIFT 6
+#define CQE_ERROR_BITMAP_RESERVED2_MASK 0x1
+#define CQE_ERROR_BITMAP_RESERVED2_SHIFT 7
};
union cqe_error_status {
@@ -126,86 +128,72 @@ union cqe_error_status {
struct cqe_error_bitmap error_bits;
};
+/* iSCSI Login Response PDU header */
struct data_hdr {
__le32 data[12];
};
-struct iscsi_async_msg_hdr {
- __le16 reserved0;
- u8 flags_attr;
-#define ISCSI_ASYNC_MSG_HDR_RSRV_MASK 0x7F
-#define ISCSI_ASYNC_MSG_HDR_RSRV_SHIFT 0
-#define ISCSI_ASYNC_MSG_HDR_CONST1_MASK 0x1
-#define ISCSI_ASYNC_MSG_HDR_CONST1_SHIFT 7
- u8 opcode;
- __le32 hdr_second_dword;
-#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_SHIFT 24
- struct regpair lun;
- __le32 all_ones;
- __le32 reserved1;
- __le32 stat_sn;
- __le32 exp_cmd_sn;
- __le32 max_cmd_sn;
- __le16 param1_rsrv;
- u8 async_vcode;
- u8 async_event;
- __le16 param3_rsrv;
- __le16 param2_rsrv;
- __le32 reserved7;
+/* Union of data/r2t sequence number */
+union iscsi_seq_num {
+ __le16 data_sn;
+ __le16 r2t_sn;
};
-struct iscsi_cmd_hdr {
- __le16 reserved1;
- u8 flags_attr;
-#define ISCSI_CMD_HDR_ATTR_MASK 0x7
-#define ISCSI_CMD_HDR_ATTR_SHIFT 0
-#define ISCSI_CMD_HDR_RSRV_MASK 0x3
-#define ISCSI_CMD_HDR_RSRV_SHIFT 3
-#define ISCSI_CMD_HDR_WRITE_MASK 0x1
-#define ISCSI_CMD_HDR_WRITE_SHIFT 5
-#define ISCSI_CMD_HDR_READ_MASK 0x1
-#define ISCSI_CMD_HDR_READ_SHIFT 6
-#define ISCSI_CMD_HDR_FINAL_MASK 0x1
-#define ISCSI_CMD_HDR_FINAL_SHIFT 7
- u8 hdr_first_byte;
-#define ISCSI_CMD_HDR_OPCODE_MASK 0x3F
-#define ISCSI_CMD_HDR_OPCODE_SHIFT 0
-#define ISCSI_CMD_HDR_IMM_MASK 0x1
-#define ISCSI_CMD_HDR_IMM_SHIFT 6
-#define ISCSI_CMD_HDR_RSRV1_MASK 0x1
-#define ISCSI_CMD_HDR_RSRV1_SHIFT 7
- __le32 hdr_second_dword;
-#define ISCSI_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_CMD_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_SHIFT 24
- struct regpair lun;
- __le32 itt;
- __le32 expected_transfer_length;
- __le32 cmd_sn;
- __le32 exp_stat_sn;
- __le32 cdb[4];
+/* iSCSI DIF flags */
+struct iscsi_dif_flags {
+ u8 flags;
+#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
+#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
+#define ISCSI_DIF_FLAGS_DIF_TO_PEER_MASK 0x1
+#define ISCSI_DIF_FLAGS_DIF_TO_PEER_SHIFT 4
+#define ISCSI_DIF_FLAGS_HOST_INTERFACE_MASK 0x7
+#define ISCSI_DIF_FLAGS_HOST_INTERFACE_SHIFT 5
};
+/* The iscsi storm task context of Ystorm */
+struct ystorm_iscsi_task_state {
+ struct scsi_cached_sges data_desc;
+ struct scsi_sgl_params sgl_params;
+ __le32 exp_r2t_sn;
+ __le32 buffer_offset;
+ union iscsi_seq_num seq_num;
+ struct iscsi_dif_flags dif_flags;
+ u8 flags;
+#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_MASK 0x1
+#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_SHIFT 0
+#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_MASK 0x1
+#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_SHIFT 1
+#define YSTORM_ISCSI_TASK_STATE_RESERVED0_MASK 0x3F
+#define YSTORM_ISCSI_TASK_STATE_RESERVED0_SHIFT 2
+};
+
+/* The iscsi storm task context of Ystorm */
+struct ystorm_iscsi_task_rxmit_opt {
+ __le32 fast_rxmit_sge_offset;
+ __le32 scan_start_buffer_offset;
+ __le32 fast_rxmit_buffer_offset;
+ u8 scan_start_sgl_index;
+ u8 fast_rxmit_sgl_index;
+ __le16 reserved;
+};
+
+/* iSCSI Common PDU header */
struct iscsi_common_hdr {
u8 hdr_status;
u8 hdr_response;
u8 hdr_flags;
u8 hdr_first_byte;
-#define ISCSI_COMMON_HDR_OPCODE_MASK 0x3F
-#define ISCSI_COMMON_HDR_OPCODE_SHIFT 0
-#define ISCSI_COMMON_HDR_IMM_MASK 0x1
-#define ISCSI_COMMON_HDR_IMM_SHIFT 6
-#define ISCSI_COMMON_HDR_RSRV_MASK 0x1
-#define ISCSI_COMMON_HDR_RSRV_SHIFT 7
+#define ISCSI_COMMON_HDR_OPCODE_MASK 0x3F
+#define ISCSI_COMMON_HDR_OPCODE_SHIFT 0
+#define ISCSI_COMMON_HDR_IMM_MASK 0x1
+#define ISCSI_COMMON_HDR_IMM_SHIFT 6
+#define ISCSI_COMMON_HDR_RSRV_MASK 0x1
+#define ISCSI_COMMON_HDR_RSRV_SHIFT 7
__le32 hdr_second_dword;
-#define ISCSI_COMMON_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_COMMON_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_COMMON_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_COMMON_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_COMMON_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun_reserved;
__le32 itt;
__le32 ttt;
@@ -215,86 +203,60 @@ struct iscsi_common_hdr {
__le32 data[3];
};
-struct iscsi_conn_offload_params {
- struct regpair sq_pbl_addr;
- struct regpair r2tq_pbl_addr;
- struct regpair xhq_pbl_addr;
- struct regpair uhq_pbl_addr;
- __le32 initial_ack;
- __le16 physical_q0;
- __le16 physical_q1;
- u8 flags;
-#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_MASK 0x1
-#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_SHIFT 0
-#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_MASK 0x1
-#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_SHIFT 1
-#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_MASK 0x1
-#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_SHIFT 2
-#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_MASK 0x1F
-#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_SHIFT 3
- u8 pbl_page_size_log;
- u8 pbe_page_size_log;
- u8 default_cq;
- __le32 stat_sn;
-};
-
-struct iscsi_slow_path_hdr {
- u8 op_code;
- u8 flags;
-#define ISCSI_SLOW_PATH_HDR_RESERVED0_MASK 0xF
-#define ISCSI_SLOW_PATH_HDR_RESERVED0_SHIFT 0
-#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_MASK 0x7
-#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_SHIFT 4
-#define ISCSI_SLOW_PATH_HDR_RESERVED1_MASK 0x1
-#define ISCSI_SLOW_PATH_HDR_RESERVED1_SHIFT 7
-};
-
-struct iscsi_conn_update_ramrod_params {
- struct iscsi_slow_path_hdr hdr;
- __le16 conn_id;
- __le32 fw_cid;
- u8 flags;
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_SHIFT 0
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_SHIFT 1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_SHIFT 2
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_SHIFT 3
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_SHIFT 4
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_MASK 0x1
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_SHIFT 5
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_MASK 0x3
-#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_SHIFT 6
- u8 reserved0[3];
- __le32 max_seq_size;
- __le32 max_send_pdu_length;
- __le32 max_recv_pdu_length;
- __le32 first_seq_length;
+/* iSCSI Command PDU header */
+struct iscsi_cmd_hdr {
+ __le16 reserved1;
+ u8 flags_attr;
+#define ISCSI_CMD_HDR_ATTR_MASK 0x7
+#define ISCSI_CMD_HDR_ATTR_SHIFT 0
+#define ISCSI_CMD_HDR_RSRV_MASK 0x3
+#define ISCSI_CMD_HDR_RSRV_SHIFT 3
+#define ISCSI_CMD_HDR_WRITE_MASK 0x1
+#define ISCSI_CMD_HDR_WRITE_SHIFT 5
+#define ISCSI_CMD_HDR_READ_MASK 0x1
+#define ISCSI_CMD_HDR_READ_SHIFT 6
+#define ISCSI_CMD_HDR_FINAL_MASK 0x1
+#define ISCSI_CMD_HDR_FINAL_SHIFT 7
+ u8 hdr_first_byte;
+#define ISCSI_CMD_HDR_OPCODE_MASK 0x3F
+#define ISCSI_CMD_HDR_OPCODE_SHIFT 0
+#define ISCSI_CMD_HDR_IMM_MASK 0x1
+#define ISCSI_CMD_HDR_IMM_SHIFT 6
+#define ISCSI_CMD_HDR_RSRV1_MASK 0x1
+#define ISCSI_CMD_HDR_RSRV1_SHIFT 7
+ __le32 hdr_second_dword;
+#define ISCSI_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_CMD_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_CMD_HDR_TOTAL_AHS_LEN_SHIFT 24
+ struct regpair lun;
+ __le32 itt;
+ __le32 expected_transfer_length;
+ __le32 cmd_sn;
__le32 exp_stat_sn;
+ __le32 cdb[4];
};
+/* iSCSI Command PDU header with Extended CDB (Initiator Mode) */
struct iscsi_ext_cdb_cmd_hdr {
__le16 reserved1;
u8 flags_attr;
-#define ISCSI_EXT_CDB_CMD_HDR_ATTR_MASK 0x7
-#define ISCSI_EXT_CDB_CMD_HDR_ATTR_SHIFT 0
-#define ISCSI_EXT_CDB_CMD_HDR_RSRV_MASK 0x3
-#define ISCSI_EXT_CDB_CMD_HDR_RSRV_SHIFT 3
-#define ISCSI_EXT_CDB_CMD_HDR_WRITE_MASK 0x1
-#define ISCSI_EXT_CDB_CMD_HDR_WRITE_SHIFT 5
-#define ISCSI_EXT_CDB_CMD_HDR_READ_MASK 0x1
-#define ISCSI_EXT_CDB_CMD_HDR_READ_SHIFT 6
-#define ISCSI_EXT_CDB_CMD_HDR_FINAL_MASK 0x1
-#define ISCSI_EXT_CDB_CMD_HDR_FINAL_SHIFT 7
+#define ISCSI_EXT_CDB_CMD_HDR_ATTR_MASK 0x7
+#define ISCSI_EXT_CDB_CMD_HDR_ATTR_SHIFT 0
+#define ISCSI_EXT_CDB_CMD_HDR_RSRV_MASK 0x3
+#define ISCSI_EXT_CDB_CMD_HDR_RSRV_SHIFT 3
+#define ISCSI_EXT_CDB_CMD_HDR_WRITE_MASK 0x1
+#define ISCSI_EXT_CDB_CMD_HDR_WRITE_SHIFT 5
+#define ISCSI_EXT_CDB_CMD_HDR_READ_MASK 0x1
+#define ISCSI_EXT_CDB_CMD_HDR_READ_SHIFT 6
+#define ISCSI_EXT_CDB_CMD_HDR_FINAL_MASK 0x1
+#define ISCSI_EXT_CDB_CMD_HDR_FINAL_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_MASK 0xFF
-#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_SHIFT 24
+#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_EXT_CDB_CMD_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_MASK 0xFF
+#define ISCSI_EXT_CDB_CMD_HDR_CDB_SIZE_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 expected_transfer_length;
@@ -303,26 +265,27 @@ struct iscsi_ext_cdb_cmd_hdr {
struct scsi_sge cdb_sge;
};
+/* iSCSI login request PDU header */
struct iscsi_login_req_hdr {
u8 version_min;
u8 version_max;
u8 flags_attr;
-#define ISCSI_LOGIN_REQ_HDR_NSG_MASK 0x3
-#define ISCSI_LOGIN_REQ_HDR_NSG_SHIFT 0
-#define ISCSI_LOGIN_REQ_HDR_CSG_MASK 0x3
-#define ISCSI_LOGIN_REQ_HDR_CSG_SHIFT 2
-#define ISCSI_LOGIN_REQ_HDR_RSRV_MASK 0x3
-#define ISCSI_LOGIN_REQ_HDR_RSRV_SHIFT 4
-#define ISCSI_LOGIN_REQ_HDR_C_MASK 0x1
-#define ISCSI_LOGIN_REQ_HDR_C_SHIFT 6
-#define ISCSI_LOGIN_REQ_HDR_T_MASK 0x1
-#define ISCSI_LOGIN_REQ_HDR_T_SHIFT 7
+#define ISCSI_LOGIN_REQ_HDR_NSG_MASK 0x3
+#define ISCSI_LOGIN_REQ_HDR_NSG_SHIFT 0
+#define ISCSI_LOGIN_REQ_HDR_CSG_MASK 0x3
+#define ISCSI_LOGIN_REQ_HDR_CSG_SHIFT 2
+#define ISCSI_LOGIN_REQ_HDR_RSRV_MASK 0x3
+#define ISCSI_LOGIN_REQ_HDR_RSRV_SHIFT 4
+#define ISCSI_LOGIN_REQ_HDR_C_MASK 0x1
+#define ISCSI_LOGIN_REQ_HDR_C_SHIFT 6
+#define ISCSI_LOGIN_REQ_HDR_T_MASK 0x1
+#define ISCSI_LOGIN_REQ_HDR_T_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_LOGIN_REQ_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_LOGIN_REQ_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 isid_tabc;
__le16 tsih;
__le16 isid_d;
@@ -334,6 +297,7 @@ struct iscsi_login_req_hdr {
__le32 reserved2[4];
};
+/* iSCSI logout request PDU header */
struct iscsi_logout_req_hdr {
__le16 reserved0;
u8 reason_code;
@@ -348,13 +312,14 @@ struct iscsi_logout_req_hdr {
__le32 reserved4[4];
};
+/* iSCSI Data-out PDU header */
struct iscsi_data_out_hdr {
__le16 reserved1;
u8 flags_attr;
-#define ISCSI_DATA_OUT_HDR_RSRV_MASK 0x7F
-#define ISCSI_DATA_OUT_HDR_RSRV_SHIFT 0
-#define ISCSI_DATA_OUT_HDR_FINAL_MASK 0x1
-#define ISCSI_DATA_OUT_HDR_FINAL_SHIFT 7
+#define ISCSI_DATA_OUT_HDR_RSRV_MASK 0x7F
+#define ISCSI_DATA_OUT_HDR_RSRV_SHIFT 0
+#define ISCSI_DATA_OUT_HDR_FINAL_MASK 0x1
+#define ISCSI_DATA_OUT_HDR_FINAL_SHIFT 7
u8 opcode;
__le32 reserved2;
struct regpair lun;
@@ -368,22 +333,23 @@ struct iscsi_data_out_hdr {
__le32 reserved5;
};
+/* iSCSI Data-in PDU header */
struct iscsi_data_in_hdr {
u8 status_rsvd;
u8 reserved1;
u8 flags;
-#define ISCSI_DATA_IN_HDR_STATUS_MASK 0x1
-#define ISCSI_DATA_IN_HDR_STATUS_SHIFT 0
-#define ISCSI_DATA_IN_HDR_UNDERFLOW_MASK 0x1
-#define ISCSI_DATA_IN_HDR_UNDERFLOW_SHIFT 1
-#define ISCSI_DATA_IN_HDR_OVERFLOW_MASK 0x1
-#define ISCSI_DATA_IN_HDR_OVERFLOW_SHIFT 2
-#define ISCSI_DATA_IN_HDR_RSRV_MASK 0x7
-#define ISCSI_DATA_IN_HDR_RSRV_SHIFT 3
-#define ISCSI_DATA_IN_HDR_ACK_MASK 0x1
-#define ISCSI_DATA_IN_HDR_ACK_SHIFT 6
-#define ISCSI_DATA_IN_HDR_FINAL_MASK 0x1
-#define ISCSI_DATA_IN_HDR_FINAL_SHIFT 7
+#define ISCSI_DATA_IN_HDR_STATUS_MASK 0x1
+#define ISCSI_DATA_IN_HDR_STATUS_SHIFT 0
+#define ISCSI_DATA_IN_HDR_UNDERFLOW_MASK 0x1
+#define ISCSI_DATA_IN_HDR_UNDERFLOW_SHIFT 1
+#define ISCSI_DATA_IN_HDR_OVERFLOW_MASK 0x1
+#define ISCSI_DATA_IN_HDR_OVERFLOW_SHIFT 2
+#define ISCSI_DATA_IN_HDR_RSRV_MASK 0x7
+#define ISCSI_DATA_IN_HDR_RSRV_SHIFT 3
+#define ISCSI_DATA_IN_HDR_ACK_MASK 0x1
+#define ISCSI_DATA_IN_HDR_ACK_SHIFT 6
+#define ISCSI_DATA_IN_HDR_FINAL_MASK 0x1
+#define ISCSI_DATA_IN_HDR_FINAL_SHIFT 7
u8 opcode;
__le32 reserved2;
struct regpair lun;
@@ -397,6 +363,7 @@ struct iscsi_data_in_hdr {
__le32 residual_count;
};
+/* iSCSI R2T PDU header */
struct iscsi_r2t_hdr {
u8 reserved0[3];
u8 opcode;
@@ -412,13 +379,14 @@ struct iscsi_r2t_hdr {
__le32 desired_data_trns_len;
};
+/* iSCSI NOP-out PDU header */
struct iscsi_nop_out_hdr {
__le16 reserved1;
u8 flags_attr;
-#define ISCSI_NOP_OUT_HDR_RSRV_MASK 0x7F
-#define ISCSI_NOP_OUT_HDR_RSRV_SHIFT 0
-#define ISCSI_NOP_OUT_HDR_CONST1_MASK 0x1
-#define ISCSI_NOP_OUT_HDR_CONST1_SHIFT 7
+#define ISCSI_NOP_OUT_HDR_RSRV_MASK 0x7F
+#define ISCSI_NOP_OUT_HDR_RSRV_SHIFT 0
+#define ISCSI_NOP_OUT_HDR_CONST1_MASK 0x1
+#define ISCSI_NOP_OUT_HDR_CONST1_SHIFT 7
u8 opcode;
__le32 reserved2;
struct regpair lun;
@@ -432,19 +400,20 @@ struct iscsi_nop_out_hdr {
__le32 reserved6;
};
+/* iSCSI NOP-in PDU header */
struct iscsi_nop_in_hdr {
__le16 reserved0;
u8 flags_attr;
-#define ISCSI_NOP_IN_HDR_RSRV_MASK 0x7F
-#define ISCSI_NOP_IN_HDR_RSRV_SHIFT 0
-#define ISCSI_NOP_IN_HDR_CONST1_MASK 0x1
-#define ISCSI_NOP_IN_HDR_CONST1_SHIFT 7
+#define ISCSI_NOP_IN_HDR_RSRV_MASK 0x7F
+#define ISCSI_NOP_IN_HDR_RSRV_SHIFT 0
+#define ISCSI_NOP_IN_HDR_CONST1_MASK 0x1
+#define ISCSI_NOP_IN_HDR_CONST1_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_NOP_IN_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_NOP_IN_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 ttt;
@@ -456,26 +425,27 @@ struct iscsi_nop_in_hdr {
__le32 reserved7;
};
+/* iSCSI Login Response PDU header */
struct iscsi_login_response_hdr {
u8 version_active;
u8 version_max;
u8 flags_attr;
-#define ISCSI_LOGIN_RESPONSE_HDR_NSG_MASK 0x3
-#define ISCSI_LOGIN_RESPONSE_HDR_NSG_SHIFT 0
-#define ISCSI_LOGIN_RESPONSE_HDR_CSG_MASK 0x3
-#define ISCSI_LOGIN_RESPONSE_HDR_CSG_SHIFT 2
-#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_MASK 0x3
-#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_SHIFT 4
-#define ISCSI_LOGIN_RESPONSE_HDR_C_MASK 0x1
-#define ISCSI_LOGIN_RESPONSE_HDR_C_SHIFT 6
-#define ISCSI_LOGIN_RESPONSE_HDR_T_MASK 0x1
-#define ISCSI_LOGIN_RESPONSE_HDR_T_SHIFT 7
+#define ISCSI_LOGIN_RESPONSE_HDR_NSG_MASK 0x3
+#define ISCSI_LOGIN_RESPONSE_HDR_NSG_SHIFT 0
+#define ISCSI_LOGIN_RESPONSE_HDR_CSG_MASK 0x3
+#define ISCSI_LOGIN_RESPONSE_HDR_CSG_SHIFT 2
+#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_MASK 0x3
+#define ISCSI_LOGIN_RESPONSE_HDR_RSRV_SHIFT 4
+#define ISCSI_LOGIN_RESPONSE_HDR_C_MASK 0x1
+#define ISCSI_LOGIN_RESPONSE_HDR_C_SHIFT 6
+#define ISCSI_LOGIN_RESPONSE_HDR_T_MASK 0x1
+#define ISCSI_LOGIN_RESPONSE_HDR_T_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_LOGIN_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_LOGIN_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 isid_tabc;
__le16 tsih;
__le16 isid_d;
@@ -490,16 +460,17 @@ struct iscsi_login_response_hdr {
__le32 reserved4[2];
};
+/* iSCSI Logout Response PDU header */
struct iscsi_logout_response_hdr {
u8 reserved1;
u8 response;
u8 flags;
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_LOGOUT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_LOGOUT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
__le32 reserved2[2];
__le32 itt;
__le32 reserved3;
@@ -512,21 +483,22 @@ struct iscsi_logout_response_hdr {
__le32 reserved5[1];
};
+/* iSCSI Text Request PDU header */
struct iscsi_text_request_hdr {
__le16 reserved0;
u8 flags_attr;
-#define ISCSI_TEXT_REQUEST_HDR_RSRV_MASK 0x3F
-#define ISCSI_TEXT_REQUEST_HDR_RSRV_SHIFT 0
-#define ISCSI_TEXT_REQUEST_HDR_C_MASK 0x1
-#define ISCSI_TEXT_REQUEST_HDR_C_SHIFT 6
-#define ISCSI_TEXT_REQUEST_HDR_F_MASK 0x1
-#define ISCSI_TEXT_REQUEST_HDR_F_SHIFT 7
+#define ISCSI_TEXT_REQUEST_HDR_RSRV_MASK 0x3F
+#define ISCSI_TEXT_REQUEST_HDR_RSRV_SHIFT 0
+#define ISCSI_TEXT_REQUEST_HDR_C_MASK 0x1
+#define ISCSI_TEXT_REQUEST_HDR_C_SHIFT 6
+#define ISCSI_TEXT_REQUEST_HDR_F_MASK 0x1
+#define ISCSI_TEXT_REQUEST_HDR_F_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_TEXT_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_TEXT_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 ttt;
@@ -535,21 +507,22 @@ struct iscsi_text_request_hdr {
__le32 reserved4[4];
};
+/* iSCSI Text Response PDU header */
struct iscsi_text_response_hdr {
__le16 reserved1;
u8 flags;
-#define ISCSI_TEXT_RESPONSE_HDR_RSRV_MASK 0x3F
-#define ISCSI_TEXT_RESPONSE_HDR_RSRV_SHIFT 0
-#define ISCSI_TEXT_RESPONSE_HDR_C_MASK 0x1
-#define ISCSI_TEXT_RESPONSE_HDR_C_SHIFT 6
-#define ISCSI_TEXT_RESPONSE_HDR_F_MASK 0x1
-#define ISCSI_TEXT_RESPONSE_HDR_F_SHIFT 7
+#define ISCSI_TEXT_RESPONSE_HDR_RSRV_MASK 0x3F
+#define ISCSI_TEXT_RESPONSE_HDR_RSRV_SHIFT 0
+#define ISCSI_TEXT_RESPONSE_HDR_C_MASK 0x1
+#define ISCSI_TEXT_RESPONSE_HDR_C_SHIFT 6
+#define ISCSI_TEXT_RESPONSE_HDR_F_MASK 0x1
+#define ISCSI_TEXT_RESPONSE_HDR_F_SHIFT 7
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_TEXT_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_TEXT_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 ttt;
@@ -559,15 +532,16 @@ struct iscsi_text_response_hdr {
__le32 reserved4[3];
};
+/* iSCSI TMF Request PDU header */
struct iscsi_tmf_request_hdr {
__le16 reserved0;
u8 function;
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_TMF_REQUEST_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_TMF_REQUEST_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 rtt;
@@ -584,10 +558,10 @@ struct iscsi_tmf_response_hdr {
u8 hdr_flags;
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_TMF_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_TMF_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair reserved0;
__le32 itt;
__le32 reserved1;
@@ -597,16 +571,17 @@ struct iscsi_tmf_response_hdr {
__le32 reserved4[3];
};
+/* iSCSI Response PDU header */
struct iscsi_response_hdr {
u8 hdr_status;
u8 hdr_response;
u8 hdr_flags;
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_RESPONSE_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_RESPONSE_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair lun;
__le32 itt;
__le32 snack_tag;
@@ -618,16 +593,17 @@ struct iscsi_response_hdr {
__le32 residual_count;
};
+/* iSCSI Reject PDU header */
struct iscsi_reject_hdr {
u8 reserved4;
u8 hdr_reason;
u8 hdr_flags;
u8 opcode;
__le32 hdr_second_dword;
-#define ISCSI_REJECT_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
-#define ISCSI_REJECT_HDR_DATA_SEG_LEN_SHIFT 0
-#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_MASK 0xFF
-#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_SHIFT 24
+#define ISCSI_REJECT_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_REJECT_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_REJECT_HDR_TOTAL_AHS_LEN_SHIFT 24
struct regpair reserved0;
__le32 all_ones;
__le32 reserved2;
@@ -638,6 +614,35 @@ struct iscsi_reject_hdr {
__le32 reserved3[2];
};
+/* iSCSI Asynchronous Message PDU header */
+struct iscsi_async_msg_hdr {
+ __le16 reserved0;
+ u8 flags_attr;
+#define ISCSI_ASYNC_MSG_HDR_RSRV_MASK 0x7F
+#define ISCSI_ASYNC_MSG_HDR_RSRV_SHIFT 0
+#define ISCSI_ASYNC_MSG_HDR_CONST1_MASK 0x1
+#define ISCSI_ASYNC_MSG_HDR_CONST1_SHIFT 7
+ u8 opcode;
+ __le32 hdr_second_dword;
+#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_MASK 0xFFFFFF
+#define ISCSI_ASYNC_MSG_HDR_DATA_SEG_LEN_SHIFT 0
+#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_MASK 0xFF
+#define ISCSI_ASYNC_MSG_HDR_TOTAL_AHS_LEN_SHIFT 24
+ struct regpair lun;
+ __le32 all_ones;
+ __le32 reserved1;
+ __le32 stat_sn;
+ __le32 exp_cmd_sn;
+ __le32 max_cmd_sn;
+ __le16 param1_rsrv;
+ u8 async_vcode;
+ u8 async_event;
+ __le16 param3_rsrv;
+ __le16 param2_rsrv;
+ __le32 reserved7;
+};
+
+/* PDU header part of Ystorm task context */
union iscsi_task_hdr {
struct iscsi_common_hdr common;
struct data_hdr data;
@@ -661,6 +666,329 @@ union iscsi_task_hdr {
struct iscsi_async_msg_hdr async_msg;
};
+/* The iscsi storm task context of Ystorm */
+struct ystorm_iscsi_task_st_ctx {
+ struct ystorm_iscsi_task_state state;
+ struct ystorm_iscsi_task_rxmit_opt rxmit_opt;
+ union iscsi_task_hdr pdu_hdr;
+};
+
+struct ystorm_iscsi_task_ag_ctx {
+ u8 reserved;
+ u8 byte1;
+ __le16 word0;
+ u8 flags0;
+#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
+#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
+#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
+#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
+#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
+ u8 flags1;
+#define YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
+#define YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
+#define YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
+#define YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
+#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
+#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
+#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
+#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
+ u8 flags2;
+#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
+ u8 byte2;
+ __le32 TTT;
+ u8 byte3;
+ u8 byte4;
+ __le16 word1;
+};
+
+struct mstorm_iscsi_task_ag_ctx {
+ u8 cdu_validation;
+ u8 byte1;
+ __le16 task_cid;
+ u8 flags0;
+#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
+#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
+ u8 flags1;
+#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
+#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
+#define MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
+#define MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
+#define MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
+#define MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
+#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
+#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
+ u8 flags2;
+#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
+ u8 byte2;
+ __le32 reg0;
+ u8 byte3;
+ u8 byte4;
+ __le16 word1;
+};
+
+struct ustorm_iscsi_task_ag_ctx {
+ u8 reserved;
+ u8 state;
+ __le16 icid;
+ u8 flags0;
+#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
+#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
+#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
+#define USTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
+#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
+ u8 flags1;
+#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
+#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
+#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
+#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
+#define USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
+#define USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
+#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
+#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
+ u8 flags2;
+#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
+#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
+#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
+#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
+#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
+#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
+#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
+#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
+ u8 flags3;
+#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
+#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
+#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
+#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
+#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
+#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
+#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
+ __le32 dif_err_intervals;
+ __le32 dif_error_1st_interval;
+ __le32 rcv_cont_len;
+ __le32 exp_cont_len;
+ __le32 total_data_acked;
+ __le32 exp_data_acked;
+ u8 next_tid_valid;
+ u8 byte3;
+ __le16 word1;
+ __le16 next_tid;
+ __le16 word3;
+ __le32 hdr_residual_count;
+ __le32 exp_r2t_sn;
+};
+
+/* The iscsi storm task context of Mstorm */
+struct mstorm_iscsi_task_st_ctx {
+ struct scsi_cached_sges data_desc;
+ struct scsi_sgl_params sgl_params;
+ __le32 rem_task_size;
+ __le32 data_buffer_offset;
+ u8 task_type;
+ struct iscsi_dif_flags dif_flags;
+ u8 reserved0[2];
+ struct regpair sense_db;
+ __le32 expected_itt;
+ __le32 reserved1;
+};
+
+struct iscsi_reg1 {
+ __le32 reg1_map;
+#define ISCSI_REG1_NUM_SGES_MASK 0xF
+#define ISCSI_REG1_NUM_SGES_SHIFT 0
+#define ISCSI_REG1_RESERVED1_MASK 0xFFFFFFF
+#define ISCSI_REG1_RESERVED1_SHIFT 4
+};
+
+/* The iscsi storm task context of Ustorm */
+struct ustorm_iscsi_task_st_ctx {
+ __le32 rem_rcv_len;
+ __le32 exp_data_transfer_len;
+ __le32 exp_data_sn;
+ struct regpair lun;
+ struct iscsi_reg1 reg1;
+ u8 flags2;
+#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_SHIFT 0
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_MASK 0x7F
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_SHIFT 1
+ struct iscsi_dif_flags dif_flags;
+ __le16 reserved3;
+ __le32 reserved4;
+ __le32 reserved5;
+ __le32 reserved6;
+ __le32 reserved7;
+ u8 task_type;
+ u8 error_flags;
+#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_SHIFT 0
+#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_SHIFT 1
+#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_SHIFT 2
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_MASK 0x1F
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_SHIFT 3
+ u8 flags;
+#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_MASK 0x3
+#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_SHIFT 0
+#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_SHIFT 2
+#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_SHIFT 3
+#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_SHIFT 4
+#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_SHIFT 5
+#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_SHIFT 6
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_MASK 0x1
+#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_SHIFT 7
+ u8 cq_rss_number;
+};
+
+/* iscsi task context */
+struct iscsi_task_context {
+ struct ystorm_iscsi_task_st_ctx ystorm_st_context;
+ struct ystorm_iscsi_task_ag_ctx ystorm_ag_context;
+ struct regpair ystorm_ag_padding[2];
+ struct tdif_task_context tdif_context;
+ struct mstorm_iscsi_task_ag_ctx mstorm_ag_context;
+ struct regpair mstorm_ag_padding[2];
+ struct ustorm_iscsi_task_ag_ctx ustorm_ag_context;
+ struct mstorm_iscsi_task_st_ctx mstorm_st_context;
+ struct ustorm_iscsi_task_st_ctx ustorm_st_context;
+ struct rdif_task_context rdif_context;
+};
+
+/* iSCSI connection offload params passed by driver to FW in ISCSI offload
+ * ramrod.
+ */
+struct iscsi_conn_offload_params {
+ struct regpair sq_pbl_addr;
+ struct regpair r2tq_pbl_addr;
+ struct regpair xhq_pbl_addr;
+ struct regpair uhq_pbl_addr;
+ __le32 initial_ack;
+ __le16 physical_q0;
+ __le16 physical_q1;
+ u8 flags;
+#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_MASK 0x1
+#define ISCSI_CONN_OFFLOAD_PARAMS_TCP_ON_CHIP_1B_SHIFT 0
+#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_MASK 0x1
+#define ISCSI_CONN_OFFLOAD_PARAMS_TARGET_MODE_SHIFT 1
+#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_MASK 0x1
+#define ISCSI_CONN_OFFLOAD_PARAMS_RESTRICTED_MODE_SHIFT 2
+#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_MASK 0x1F
+#define ISCSI_CONN_OFFLOAD_PARAMS_RESERVED1_SHIFT 3
+ u8 pbl_page_size_log;
+ u8 pbe_page_size_log;
+ u8 default_cq;
+ __le32 stat_sn;
+};
+
+/* spe message header */
+struct iscsi_slow_path_hdr {
+ u8 op_code;
+ u8 flags;
+#define ISCSI_SLOW_PATH_HDR_RESERVED0_MASK 0xF
+#define ISCSI_SLOW_PATH_HDR_RESERVED0_SHIFT 0
+#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_MASK 0x7
+#define ISCSI_SLOW_PATH_HDR_LAYER_CODE_SHIFT 4
+#define ISCSI_SLOW_PATH_HDR_RESERVED1_MASK 0x1
+#define ISCSI_SLOW_PATH_HDR_RESERVED1_SHIFT 7
+};
+
+/* iSCSI connection update params passed by driver to FW in ISCSI update
+ *ramrod.
+ */
+struct iscsi_conn_update_ramrod_params {
+ struct iscsi_slow_path_hdr hdr;
+ __le16 conn_id;
+ __le32 fw_cid;
+ u8 flags;
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_HD_EN_SHIFT 0
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DD_EN_SHIFT 1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_INITIAL_R2T_SHIFT 2
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_IMMEDIATE_DATA_SHIFT 3
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_BLOCK_SIZE_SHIFT 4
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_MASK 0x1
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_DIF_ON_HOST_EN_SHIFT 5
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_MASK 0x3
+#define ISCSI_CONN_UPDATE_RAMROD_PARAMS_RESERVED1_SHIFT 6
+ u8 reserved0[3];
+ __le32 max_seq_size;
+ __le32 max_send_pdu_length;
+ __le32 max_recv_pdu_length;
+ __le32 first_seq_length;
+ __le32 exp_stat_sn;
+};
+
+/* iSCSI CQ element */
struct iscsi_cqe_common {
__le16 conn_id;
u8 cqe_type;
@@ -669,6 +997,7 @@ struct iscsi_cqe_common {
union iscsi_task_hdr iscsi_hdr;
};
+/* iSCSI CQ element */
struct iscsi_cqe_solicited {
__le16 conn_id;
u8 cqe_type;
@@ -682,6 +1011,7 @@ struct iscsi_cqe_solicited {
union iscsi_task_hdr iscsi_hdr;
};
+/* iSCSI CQ element */
struct iscsi_cqe_unsolicited {
__le16 conn_id;
u8 cqe_type;
@@ -693,12 +1023,14 @@ struct iscsi_cqe_unsolicited {
union iscsi_task_hdr iscsi_hdr;
};
+/* iSCSI CQ element */
union iscsi_cqe {
struct iscsi_cqe_common cqe_common;
struct iscsi_cqe_solicited cqe_solicited;
struct iscsi_cqe_unsolicited cqe_unsolicited;
};
+/* iSCSI CQE type */
enum iscsi_cqes_type {
ISCSI_CQE_TYPE_SOLICITED = 1,
ISCSI_CQE_TYPE_UNSOLICITED,
@@ -708,6 +1040,7 @@ enum iscsi_cqes_type {
MAX_ISCSI_CQES_TYPE
};
+/* iSCSI CQE type */
enum iscsi_cqe_unsolicited_type {
ISCSI_CQE_UNSOLICITED_NONE,
ISCSI_CQE_UNSOLICITED_SINGLE,
@@ -717,37 +1050,28 @@ enum iscsi_cqe_unsolicited_type {
MAX_ISCSI_CQE_UNSOLICITED_TYPE
};
-
+/* iscsi debug modes */
struct iscsi_debug_modes {
u8 flags;
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_SHIFT 0
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_SHIFT 1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_SHIFT 2
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_SHIFT 3
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_SHIFT 4
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_SHIFT 5
-#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_SHIFT 6
-#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_MASK 0x1
-#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_SHIFT 7
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RX_CONN_ERROR_SHIFT 0
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_RESET_SHIFT 1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_FIN_SHIFT 2
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_CLEANUP_SHIFT 3
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_REJECT_OR_ASYNC_SHIFT 4
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_RECV_NOP_SHIFT 5
+#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_DATA_DIGEST_ERROR_SHIFT 6
+#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_MASK 0x1
+#define ISCSI_DEBUG_MODES_ASSERT_IF_DIF_ERROR_SHIFT 7
};
-struct iscsi_dif_flags {
- u8 flags;
-#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF
-#define ISCSI_DIF_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0
-#define ISCSI_DIF_FLAGS_DIF_TO_PEER_MASK 0x1
-#define ISCSI_DIF_FLAGS_DIF_TO_PEER_SHIFT 4
-#define ISCSI_DIF_FLAGS_HOST_INTERFACE_MASK 0x7
-#define ISCSI_DIF_FLAGS_HOST_INTERFACE_SHIFT 5
-};
-
+/* iSCSI kernel completion queue IDs */
enum iscsi_eqe_opcode {
ISCSI_EVENT_TYPE_INIT_FUNC = 0,
ISCSI_EVENT_TYPE_DESTROY_FUNC,
@@ -772,6 +1096,7 @@ enum iscsi_eqe_opcode {
MAX_ISCSI_EQE_OPCODE
};
+/* iSCSI EQE and CQE completion status */
enum iscsi_error_types {
ISCSI_STATUS_NONE = 0,
ISCSI_CQE_ERROR_UNSOLICITED_RCV_ON_INVALID_CONN = 1,
@@ -823,7 +1148,7 @@ enum iscsi_error_types {
MAX_ISCSI_ERROR_TYPES
};
-
+/* iSCSI Ramrod Command IDs */
enum iscsi_ramrod_cmd_id {
ISCSI_RAMROD_CMD_ID_UNUSED = 0,
ISCSI_RAMROD_CMD_ID_INIT_FUNC = 1,
@@ -836,19 +1161,7 @@ enum iscsi_ramrod_cmd_id {
MAX_ISCSI_RAMROD_CMD_ID
};
-struct iscsi_reg1 {
- __le32 reg1_map;
-#define ISCSI_REG1_NUM_SGES_MASK 0xF
-#define ISCSI_REG1_NUM_SGES_SHIFT 0
-#define ISCSI_REG1_RESERVED1_MASK 0xFFFFFFF
-#define ISCSI_REG1_RESERVED1_SHIFT 4
-};
-
-union iscsi_seq_num {
- __le16 data_sn;
- __le16 r2t_sn;
-};
-
+/* iSCSI connection termination request */
struct iscsi_spe_conn_mac_update {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
@@ -859,6 +1172,9 @@ struct iscsi_spe_conn_mac_update {
u8 reserved0[2];
};
+/* iSCSI and TCP connection (Option 1) offload params passed by driver to FW in
+ * iSCSI offload ramrod.
+ */
struct iscsi_spe_conn_offload {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
@@ -867,6 +1183,9 @@ struct iscsi_spe_conn_offload {
struct tcp_offload_params tcp;
};
+/* iSCSI and TCP connection(Option 2) offload params passed by driver to FW in
+ * iSCSI offload ramrod.
+ */
struct iscsi_spe_conn_offload_option2 {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
@@ -875,6 +1194,7 @@ struct iscsi_spe_conn_offload_option2 {
struct tcp_offload_params_opt2 tcp;
};
+/* iSCSI connection termination request */
struct iscsi_spe_conn_termination {
struct iscsi_slow_path_hdr hdr;
__le16 conn_id;
@@ -885,12 +1205,14 @@ struct iscsi_spe_conn_termination {
struct regpair query_params_addr;
};
+/* iSCSI firmware function destroy parameters */
struct iscsi_spe_func_dstry {
struct iscsi_slow_path_hdr hdr;
__le16 reserved0;
__le32 reserved1;
};
+/* iSCSI firmware function init parameters */
struct iscsi_spe_func_init {
struct iscsi_slow_path_hdr hdr;
__le16 half_way_close_timeout;
@@ -908,273 +1230,7 @@ struct iscsi_spe_func_init {
struct scsi_init_func_queues q_params;
};
-struct ystorm_iscsi_task_state {
- struct scsi_cached_sges data_desc;
- struct scsi_sgl_params sgl_params;
- __le32 exp_r2t_sn;
- __le32 buffer_offset;
- union iscsi_seq_num seq_num;
- struct iscsi_dif_flags dif_flags;
- u8 flags;
-#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_MASK 0x1
-#define YSTORM_ISCSI_TASK_STATE_LOCAL_COMP_SHIFT 0
-#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_MASK 0x1
-#define YSTORM_ISCSI_TASK_STATE_SLOW_IO_SHIFT 1
-#define YSTORM_ISCSI_TASK_STATE_RESERVED0_MASK 0x3F
-#define YSTORM_ISCSI_TASK_STATE_RESERVED0_SHIFT 2
-};
-
-struct ystorm_iscsi_task_rxmit_opt {
- __le32 fast_rxmit_sge_offset;
- __le32 scan_start_buffer_offset;
- __le32 fast_rxmit_buffer_offset;
- u8 scan_start_sgl_index;
- u8 fast_rxmit_sgl_index;
- __le16 reserved;
-};
-
-struct ystorm_iscsi_task_st_ctx {
- struct ystorm_iscsi_task_state state;
- struct ystorm_iscsi_task_rxmit_opt rxmit_opt;
- union iscsi_task_hdr pdu_hdr;
-};
-
-struct ystorm_iscsi_task_ag_ctx {
- u8 reserved;
- u8 byte1;
- __le16 word0;
- u8 flags0;
-#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
-#define YSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define YSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
- u8 flags1;
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 0
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
-#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_MASK 0x3
-#define YSTORM_ISCSI_TASK_AG_CTX_CF2SPECIAL_SHIFT 4
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 6
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
- u8 flags2;
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define YSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
- u8 byte2;
- __le32 TTT;
- u8 byte3;
- u8 byte4;
- __le16 word1;
-};
-
-struct mstorm_iscsi_task_ag_ctx {
- u8 cdu_validation;
- u8 byte1;
- __le16 task_cid;
- u8 flags0;
-#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define MSTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define MSTORM_ISCSI_TASK_AG_CTX_VALID_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_VALID_SHIFT 6
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_FLAG_SHIFT 7
- u8 flags1;
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_MASK 0x3
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_SHIFT 0
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 2
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 4
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_TASK_CLEANUP_CF_EN_SHIFT 6
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 7
- u8 flags2;
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 0
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 2
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 3
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 4
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 5
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 6
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define MSTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 7
- u8 byte2;
- __le32 reg0;
- u8 byte3;
- u8 byte4;
- __le16 word1;
-};
-
-struct ustorm_iscsi_task_ag_ctx {
- u8 reserved;
- u8 state;
- __le16 icid;
- u8 flags0;
-#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF
-#define USTORM_ISCSI_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4
-#define USTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_SHIFT 6
- u8 flags1;
-#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_RESERVED1_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_SHIFT 2
-#define USTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 4
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6
- u8 flags2;
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_HQ_SCANNED_CF_EN_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_DISABLE_DATA_ACKED_SHIFT 1
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_R2T2RECV_EN_SHIFT 2
-#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 3
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_DATA_TOTAL_EXP_EN_SHIFT 5
-#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 6
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_CMP_CONT_RCV_EXP_EN_SHIFT 7
- u8 flags3;
-#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 0
-#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 2
-#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_MASK 0x1
-#define USTORM_ISCSI_TASK_AG_CTX_RULE6EN_SHIFT 3
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF
-#define USTORM_ISCSI_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4
- __le32 dif_err_intervals;
- __le32 dif_error_1st_interval;
- __le32 rcv_cont_len;
- __le32 exp_cont_len;
- __le32 total_data_acked;
- __le32 exp_data_acked;
- u8 next_tid_valid;
- u8 byte3;
- __le16 word1;
- __le16 next_tid;
- __le16 word3;
- __le32 hdr_residual_count;
- __le32 exp_r2t_sn;
-};
-
-struct mstorm_iscsi_task_st_ctx {
- struct scsi_cached_sges data_desc;
- struct scsi_sgl_params sgl_params;
- __le32 rem_task_size;
- __le32 data_buffer_offset;
- u8 task_type;
- struct iscsi_dif_flags dif_flags;
- u8 reserved0[2];
- struct regpair sense_db;
- __le32 expected_itt;
- __le32 reserved1;
-};
-
-struct ustorm_iscsi_task_st_ctx {
- __le32 rem_rcv_len;
- __le32 exp_data_transfer_len;
- __le32 exp_data_sn;
- struct regpair lun;
- struct iscsi_reg1 reg1;
- u8 flags2;
-#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_AHS_EXIST_SHIFT 0
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_MASK 0x7F
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED1_SHIFT 1
- struct iscsi_dif_flags dif_flags;
- __le16 reserved3;
- __le32 reserved4;
- __le32 reserved5;
- __le32 reserved6;
- __le32 reserved7;
- u8 task_type;
- u8 error_flags;
-#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_DATA_DIGEST_ERROR_SHIFT 0
-#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_DATA_TRUNCATED_ERROR_SHIFT 1
-#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_UNDER_RUN_ERROR_SHIFT 2
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_MASK 0x1F
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED8_SHIFT 3
- u8 flags;
-#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_MASK 0x3
-#define USTORM_ISCSI_TASK_ST_CTX_CQE_WRITE_SHIFT 0
-#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_LOCAL_COMP_SHIFT 2
-#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_Q0_R2TQE_WRITE_SHIFT 3
-#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_TOTAL_DATA_ACKED_DONE_SHIFT 4
-#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_HQ_SCANNED_DONE_SHIFT 5
-#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_R2T2RECV_DONE_SHIFT 6
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_MASK 0x1
-#define USTORM_ISCSI_TASK_ST_CTX_RESERVED0_SHIFT 7
- u8 cq_rss_number;
-};
-
-struct iscsi_task_context {
- struct ystorm_iscsi_task_st_ctx ystorm_st_context;
- struct ystorm_iscsi_task_ag_ctx ystorm_ag_context;
- struct regpair ystorm_ag_padding[2];
- struct tdif_task_context tdif_context;
- struct mstorm_iscsi_task_ag_ctx mstorm_ag_context;
- struct regpair mstorm_ag_padding[2];
- struct ustorm_iscsi_task_ag_ctx ustorm_ag_context;
- struct mstorm_iscsi_task_st_ctx mstorm_st_context;
- struct ustorm_iscsi_task_st_ctx ustorm_st_context;
- struct rdif_task_context rdif_context;
-};
-
+/* iSCSI task type */
enum iscsi_task_type {
ISCSI_TASK_TYPE_INITIATOR_WRITE,
ISCSI_TASK_TYPE_INITIATOR_READ,
@@ -1189,50 +1245,53 @@ enum iscsi_task_type {
MAX_ISCSI_TASK_TYPE
};
+/* iSCSI DesiredDataTransferLength/ttt union */
union iscsi_ttt_txlen_union {
__le32 desired_tx_len;
__le32 ttt;
};
+/* iSCSI uHQ element */
struct iscsi_uhqe {
__le32 reg1;
-#define ISCSI_UHQE_PDU_PAYLOAD_LEN_MASK 0xFFFFF
-#define ISCSI_UHQE_PDU_PAYLOAD_LEN_SHIFT 0
-#define ISCSI_UHQE_LOCAL_COMP_MASK 0x1
-#define ISCSI_UHQE_LOCAL_COMP_SHIFT 20
-#define ISCSI_UHQE_TOGGLE_BIT_MASK 0x1
-#define ISCSI_UHQE_TOGGLE_BIT_SHIFT 21
-#define ISCSI_UHQE_PURE_PAYLOAD_MASK 0x1
-#define ISCSI_UHQE_PURE_PAYLOAD_SHIFT 22
-#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_MASK 0x1
-#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_SHIFT 23
-#define ISCSI_UHQE_TASK_ID_HI_MASK 0xFF
-#define ISCSI_UHQE_TASK_ID_HI_SHIFT 24
+#define ISCSI_UHQE_PDU_PAYLOAD_LEN_MASK 0xFFFFF
+#define ISCSI_UHQE_PDU_PAYLOAD_LEN_SHIFT 0
+#define ISCSI_UHQE_LOCAL_COMP_MASK 0x1
+#define ISCSI_UHQE_LOCAL_COMP_SHIFT 20
+#define ISCSI_UHQE_TOGGLE_BIT_MASK 0x1
+#define ISCSI_UHQE_TOGGLE_BIT_SHIFT 21
+#define ISCSI_UHQE_PURE_PAYLOAD_MASK 0x1
+#define ISCSI_UHQE_PURE_PAYLOAD_SHIFT 22
+#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_MASK 0x1
+#define ISCSI_UHQE_LOGIN_RESPONSE_PDU_SHIFT 23
+#define ISCSI_UHQE_TASK_ID_HI_MASK 0xFF
+#define ISCSI_UHQE_TASK_ID_HI_SHIFT 24
__le32 reg2;
-#define ISCSI_UHQE_BUFFER_OFFSET_MASK 0xFFFFFF
-#define ISCSI_UHQE_BUFFER_OFFSET_SHIFT 0
-#define ISCSI_UHQE_TASK_ID_LO_MASK 0xFF
-#define ISCSI_UHQE_TASK_ID_LO_SHIFT 24
+#define ISCSI_UHQE_BUFFER_OFFSET_MASK 0xFFFFFF
+#define ISCSI_UHQE_BUFFER_OFFSET_SHIFT 0
+#define ISCSI_UHQE_TASK_ID_LO_MASK 0xFF
+#define ISCSI_UHQE_TASK_ID_LO_SHIFT 24
};
-
+/* iSCSI WQ element */
struct iscsi_wqe {
__le16 task_id;
u8 flags;
-#define ISCSI_WQE_WQE_TYPE_MASK 0x7
-#define ISCSI_WQE_WQE_TYPE_SHIFT 0
-#define ISCSI_WQE_NUM_SGES_MASK 0xF
-#define ISCSI_WQE_NUM_SGES_SHIFT 3
-#define ISCSI_WQE_RESPONSE_MASK 0x1
-#define ISCSI_WQE_RESPONSE_SHIFT 7
+#define ISCSI_WQE_WQE_TYPE_MASK 0x7
+#define ISCSI_WQE_WQE_TYPE_SHIFT 0
+#define ISCSI_WQE_NUM_SGES_MASK 0xF
+#define ISCSI_WQE_NUM_SGES_SHIFT 3
+#define ISCSI_WQE_RESPONSE_MASK 0x1
+#define ISCSI_WQE_RESPONSE_SHIFT 7
struct iscsi_dif_flags prot_flags;
__le32 contlen_cdbsize;
-#define ISCSI_WQE_CONT_LEN_MASK 0xFFFFFF
-#define ISCSI_WQE_CONT_LEN_SHIFT 0
-#define ISCSI_WQE_CDB_SIZE_MASK 0xFF
-#define ISCSI_WQE_CDB_SIZE_SHIFT 24
+#define ISCSI_WQE_CONT_LEN_MASK 0xFFFFFF
+#define ISCSI_WQE_CONT_LEN_SHIFT 0
+#define ISCSI_WQE_CDB_SIZE_MASK 0xFF
+#define ISCSI_WQE_CDB_SIZE_SHIFT 24
};
+/* iSCSI wqe type */
enum iscsi_wqe_type {
ISCSI_WQE_TYPE_NORMAL,
ISCSI_WQE_TYPE_TASK_CLEANUP,
@@ -1244,6 +1303,7 @@ enum iscsi_wqe_type {
MAX_ISCSI_WQE_TYPE
};
+/* iSCSI xHQ element */
struct iscsi_xhqe {
union iscsi_ttt_txlen_union ttt_or_txlen;
__le32 exp_stat_sn;
@@ -1251,27 +1311,30 @@ struct iscsi_xhqe {
u8 total_ahs_length;
u8 opcode;
u8 flags;
-#define ISCSI_XHQE_FINAL_MASK 0x1
-#define ISCSI_XHQE_FINAL_SHIFT 0
-#define ISCSI_XHQE_STATUS_BIT_MASK 0x1
-#define ISCSI_XHQE_STATUS_BIT_SHIFT 1
-#define ISCSI_XHQE_NUM_SGES_MASK 0xF
-#define ISCSI_XHQE_NUM_SGES_SHIFT 2
-#define ISCSI_XHQE_RESERVED0_MASK 0x3
-#define ISCSI_XHQE_RESERVED0_SHIFT 6
+#define ISCSI_XHQE_FINAL_MASK 0x1
+#define ISCSI_XHQE_FINAL_SHIFT 0
+#define ISCSI_XHQE_STATUS_BIT_MASK 0x1
+#define ISCSI_XHQE_STATUS_BIT_SHIFT 1
+#define ISCSI_XHQE_NUM_SGES_MASK 0xF
+#define ISCSI_XHQE_NUM_SGES_SHIFT 2
+#define ISCSI_XHQE_RESERVED0_MASK 0x3
+#define ISCSI_XHQE_RESERVED0_SHIFT 6
union iscsi_seq_num seq_num;
__le16 reserved1;
};
+/* Per PF iSCSI receive path statistics - mStorm RAM structure */
struct mstorm_iscsi_stats_drv {
struct regpair iscsi_rx_dropped_pdus_task_not_valid;
};
+/* Per PF iSCSI transmit path statistics - pStorm RAM structure */
struct pstorm_iscsi_stats_drv {
struct regpair iscsi_tx_bytes_cnt;
struct regpair iscsi_tx_packet_cnt;
};
+/* Per PF iSCSI receive path statistics - tStorm RAM structure */
struct tstorm_iscsi_stats_drv {
struct regpair iscsi_rx_bytes_cnt;
struct regpair iscsi_rx_packet_cnt;
@@ -1281,17 +1344,20 @@ struct tstorm_iscsi_stats_drv {
__le32 iscsi_immq_threshold_cnt;
};
+/* Per PF iSCSI receive path statistics - uStorm RAM structure */
struct ustorm_iscsi_stats_drv {
struct regpair iscsi_rx_data_pdu_cnt;
struct regpair iscsi_rx_r2t_pdu_cnt;
struct regpair iscsi_rx_total_pdu_cnt;
};
+/* Per PF iSCSI transmit path statistics - xStorm RAM structure */
struct xstorm_iscsi_stats_drv {
struct regpair iscsi_tx_go_to_slow_start_event_cnt;
struct regpair iscsi_tx_fast_retransmit_event_cnt;
};
+/* Per PF iSCSI transmit path statistics - yStorm RAM structure */
struct ystorm_iscsi_stats_drv {
struct regpair iscsi_tx_data_pdu_cnt;
struct regpair iscsi_tx_r2t_pdu_cnt;
@@ -1303,68 +1369,68 @@ struct tstorm_iscsi_task_ag_ctx {
u8 byte1;
__le16 word0;
u8 flags0;
-#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
-#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
+#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_MASK 0xF
+#define TSTORM_ISCSI_TASK_AG_CTX_NIBBLE0_SHIFT 0
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT0_SHIFT 4
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT1_SHIFT 5
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT2_SHIFT 6
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT3_SHIFT 7
u8 flags1;
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT4_SHIFT 0
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_BIT5_SHIFT 1
+#define TSTORM_ISCSI_TASK_AG_CTX_CF0_MASK 0x3
+#define TSTORM_ISCSI_TASK_AG_CTX_CF0_SHIFT 2
+#define TSTORM_ISCSI_TASK_AG_CTX_CF1_MASK 0x3
+#define TSTORM_ISCSI_TASK_AG_CTX_CF1_SHIFT 4
+#define TSTORM_ISCSI_TASK_AG_CTX_CF2_MASK 0x3
+#define TSTORM_ISCSI_TASK_AG_CTX_CF2_SHIFT 6
u8 flags2;
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
+#define TSTORM_ISCSI_TASK_AG_CTX_CF3_MASK 0x3
+#define TSTORM_ISCSI_TASK_AG_CTX_CF3_SHIFT 0
+#define TSTORM_ISCSI_TASK_AG_CTX_CF4_MASK 0x3
+#define TSTORM_ISCSI_TASK_AG_CTX_CF4_SHIFT 2
+#define TSTORM_ISCSI_TASK_AG_CTX_CF5_MASK 0x3
+#define TSTORM_ISCSI_TASK_AG_CTX_CF5_SHIFT 4
+#define TSTORM_ISCSI_TASK_AG_CTX_CF6_MASK 0x3
+#define TSTORM_ISCSI_TASK_AG_CTX_CF6_SHIFT 6
u8 flags3;
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
+#define TSTORM_ISCSI_TASK_AG_CTX_CF7_MASK 0x3
+#define TSTORM_ISCSI_TASK_AG_CTX_CF7_SHIFT 0
+#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_CF0EN_SHIFT 2
+#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_CF1EN_SHIFT 3
+#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_CF2EN_SHIFT 4
+#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_CF3EN_SHIFT 5
+#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_CF4EN_SHIFT 6
+#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_CF5EN_SHIFT 7
u8 flags4;
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
-#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
+#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_CF6EN_SHIFT 0
+#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_CF7EN_SHIFT 1
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE0EN_SHIFT 2
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE1EN_SHIFT 3
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE2EN_SHIFT 4
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE3EN_SHIFT 5
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE4EN_SHIFT 6
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_MASK 0x1
+#define TSTORM_ISCSI_TASK_AG_CTX_RULE5EN_SHIFT 7
u8 byte2;
__le16 word1;
__le32 reg0;
@@ -1376,18 +1442,20 @@ struct tstorm_iscsi_task_ag_ctx {
__le32 reg1;
__le32 reg2;
};
+
+/* iSCSI doorbell data */
struct iscsi_db_data {
u8 params;
-#define ISCSI_DB_DATA_DEST_MASK 0x3
-#define ISCSI_DB_DATA_DEST_SHIFT 0
-#define ISCSI_DB_DATA_AGG_CMD_MASK 0x3
-#define ISCSI_DB_DATA_AGG_CMD_SHIFT 2
-#define ISCSI_DB_DATA_BYPASS_EN_MASK 0x1
-#define ISCSI_DB_DATA_BYPASS_EN_SHIFT 4
-#define ISCSI_DB_DATA_RESERVED_MASK 0x1
-#define ISCSI_DB_DATA_RESERVED_SHIFT 5
-#define ISCSI_DB_DATA_AGG_VAL_SEL_MASK 0x3
-#define ISCSI_DB_DATA_AGG_VAL_SEL_SHIFT 6
+#define ISCSI_DB_DATA_DEST_MASK 0x3
+#define ISCSI_DB_DATA_DEST_SHIFT 0
+#define ISCSI_DB_DATA_AGG_CMD_MASK 0x3
+#define ISCSI_DB_DATA_AGG_CMD_SHIFT 2
+#define ISCSI_DB_DATA_BYPASS_EN_MASK 0x1
+#define ISCSI_DB_DATA_BYPASS_EN_SHIFT 4
+#define ISCSI_DB_DATA_RESERVED_MASK 0x1
+#define ISCSI_DB_DATA_RESERVED_SHIFT 5
+#define ISCSI_DB_DATA_AGG_VAL_SEL_MASK 0x3
+#define ISCSI_DB_DATA_AGG_VAL_SEL_SHIFT 6
u8 agg_flags;
__le16 sq_prod;
};
diff --git a/include/linux/qed/iwarp_common.h b/include/linux/qed/iwarp_common.h
index b8b3e1c..c6cfd39 100644
--- a/include/linux/qed/iwarp_common.h
+++ b/include/linux/qed/iwarp_common.h
@@ -29,9 +29,12 @@
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
+
#ifndef __IWARP_COMMON__
#define __IWARP_COMMON__
+
#include <linux/qed/rdma_common.h>
+
/************************/
/* IWARP FW CONSTANTS */
/************************/
@@ -40,14 +43,14 @@
#define IWARP_PASSIVE_MODE 1
#define IWARP_SHARED_QUEUE_PAGE_SIZE (0x8000)
-#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_OFFSET (0x4000)
-#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE (0x1000)
-#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_OFFSET (0x5000)
-#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE (0x3000)
+#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_OFFSET (0x4000)
+#define IWARP_SHARED_QUEUE_PAGE_RQ_PBL_MAX_SIZE (0x1000)
+#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_OFFSET (0x5000)
+#define IWARP_SHARED_QUEUE_PAGE_SQ_PBL_MAX_SIZE (0x3000)
-#define IWARP_REQ_MAX_INLINE_DATA_SIZE (128)
-#define IWARP_REQ_MAX_SINGLE_SQ_WQE_SIZE (176)
+#define IWARP_REQ_MAX_INLINE_DATA_SIZE (128)
+#define IWARP_REQ_MAX_SINGLE_SQ_WQE_SIZE (176)
-#define IWARP_MAX_QPS (64 * 1024)
+#define IWARP_MAX_QPS (64 * 1024)
#endif /* __IWARP_COMMON__ */
diff --git a/include/linux/qed/qed_if.h b/include/linux/qed/qed_if.h
index cc646ca..0301499 100644
--- a/include/linux/qed/qed_if.h
+++ b/include/linux/qed/qed_if.h
@@ -316,16 +316,16 @@ enum qed_int_mode {
};
struct qed_sb_info {
- struct status_block *sb_virt;
- dma_addr_t sb_phys;
- u32 sb_ack; /* Last given ack */
- u16 igu_sb_id;
- void __iomem *igu_addr;
- u8 flags;
-#define QED_SB_INFO_INIT 0x1
-#define QED_SB_INFO_SETUP 0x2
+ struct status_block *sb_virt;
+ dma_addr_t sb_phys;
+ u32 sb_ack; /* Last given ack */
+ u16 igu_sb_id;
+ void __iomem *igu_addr;
+ u8 flags;
+#define QED_SB_INFO_INIT 0x1
+#define QED_SB_INFO_SETUP 0x2
- struct qed_dev *cdev;
+ struct qed_dev *cdev;
};
enum qed_dev_type {
diff --git a/include/linux/qed/rdma_common.h b/include/linux/qed/rdma_common.h
index a9b3050..c1a446e 100644
--- a/include/linux/qed/rdma_common.h
+++ b/include/linux/qed/rdma_common.h
@@ -32,28 +32,29 @@
#ifndef __RDMA_COMMON__
#define __RDMA_COMMON__
+
/************************/
/* RDMA FW CONSTANTS */
/************************/
-#define RDMA_RESERVED_LKEY (0)
-#define RDMA_RING_PAGE_SIZE (0x1000)
+#define RDMA_RESERVED_LKEY (0)
+#define RDMA_RING_PAGE_SIZE (0x1000)
-#define RDMA_MAX_SGE_PER_SQ_WQE (4)
-#define RDMA_MAX_SGE_PER_RQ_WQE (4)
+#define RDMA_MAX_SGE_PER_SQ_WQE (4)
+#define RDMA_MAX_SGE_PER_RQ_WQE (4)
#define RDMA_MAX_DATA_SIZE_IN_WQE (0x80000000)
-#define RDMA_REQ_RD_ATOMIC_ELM_SIZE (0x50)
-#define RDMA_RESP_RD_ATOMIC_ELM_SIZE (0x20)
+#define RDMA_REQ_RD_ATOMIC_ELM_SIZE (0x50)
+#define RDMA_RESP_RD_ATOMIC_ELM_SIZE (0x20)
-#define RDMA_MAX_CQS (64 * 1024)
-#define RDMA_MAX_TIDS (128 * 1024 - 1)
-#define RDMA_MAX_PDS (64 * 1024)
+#define RDMA_MAX_CQS (64 * 1024)
+#define RDMA_MAX_TIDS (128 * 1024 - 1)
+#define RDMA_MAX_PDS (64 * 1024)
-#define RDMA_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
-#define RDMA_NUM_STATISTIC_COUNTERS_K2 MAX_NUM_VPORTS_K2
-#define RDMA_NUM_STATISTIC_COUNTERS_BB MAX_NUM_VPORTS_BB
+#define RDMA_NUM_STATISTIC_COUNTERS MAX_NUM_VPORTS
+#define RDMA_NUM_STATISTIC_COUNTERS_K2 MAX_NUM_VPORTS_K2
+#define RDMA_NUM_STATISTIC_COUNTERS_BB MAX_NUM_VPORTS_BB
#define RDMA_TASK_TYPE (PROTOCOLID_ROCE)
diff --git a/include/linux/qed/roce_common.h b/include/linux/qed/roce_common.h
index fe6a33e..e15e0da 100644
--- a/include/linux/qed/roce_common.h
+++ b/include/linux/qed/roce_common.h
@@ -33,13 +33,18 @@
#ifndef __ROCE_COMMON__
#define __ROCE_COMMON__
-#define ROCE_REQ_MAX_INLINE_DATA_SIZE (256)
-#define ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE (288)
+/************************/
+/* ROCE FW CONSTANTS */
+/************************/
-#define ROCE_MAX_QPS (32 * 1024)
-#define ROCE_DCQCN_NP_MAX_QPS (64)
-#define ROCE_DCQCN_RP_MAX_QPS (64)
+#define ROCE_REQ_MAX_INLINE_DATA_SIZE (256)
+#define ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE (288)
+#define ROCE_MAX_QPS (32 * 1024)
+#define ROCE_DCQCN_NP_MAX_QPS (64)
+#define ROCE_DCQCN_RP_MAX_QPS (64)
+
+/* Affiliated asynchronous events / errors enumeration */
enum roce_async_events_type {
ROCE_ASYNC_EVENT_NONE = 0,
ROCE_ASYNC_EVENT_COMM_EST = 1,
diff --git a/include/linux/qed/storage_common.h b/include/linux/qed/storage_common.h
index 08df82a..f8c7b40 100644
--- a/include/linux/qed/storage_common.h
+++ b/include/linux/qed/storage_common.h
@@ -33,43 +33,53 @@
#ifndef __STORAGE_COMMON__
#define __STORAGE_COMMON__
-#define NUM_OF_CMDQS_CQS (NUM_OF_GLOBAL_QUEUES / 2)
-#define BDQ_NUM_RESOURCES (4)
+/*********************/
+/* SCSI CONSTANTS */
+/*********************/
-#define BDQ_ID_RQ (0)
-#define BDQ_ID_IMM_DATA (1)
-#define BDQ_NUM_IDS (2)
+#define NUM_OF_CMDQS_CQS (NUM_OF_GLOBAL_QUEUES / 2)
+#define BDQ_NUM_RESOURCES (4)
-#define SCSI_NUM_SGES_SLOW_SGL_THR 8
+#define BDQ_ID_RQ (0)
+#define BDQ_ID_IMM_DATA (1)
+#define BDQ_NUM_IDS (2)
-#define BDQ_MAX_EXTERNAL_RING_SIZE (1 << 15)
+#define SCSI_NUM_SGES_SLOW_SGL_THR 8
+#define BDQ_MAX_EXTERNAL_RING_SIZE BIT(15)
+
+/* SCSI buffer descriptor */
struct scsi_bd {
struct regpair address;
struct regpair opaque;
};
+/* Scsi Drv BDQ struct */
struct scsi_bdq_ram_drv_data {
__le16 external_producer;
__le16 reserved0[3];
};
+/* SCSI SGE entry */
struct scsi_sge {
struct regpair sge_addr;
__le32 sge_len;
__le32 reserved;
};
+/* Cached SGEs section */
struct scsi_cached_sges {
struct scsi_sge sge[4];
};
+/* Scsi Drv CMDQ struct */
struct scsi_drv_cmdq {
__le16 cmdq_cons;
__le16 reserved0;
__le32 reserved1;
};
+/* Common SCSI init params passed by driver to FW in function init ramrod */
struct scsi_init_func_params {
__le16 num_tasks;
u8 log_page_size;
@@ -77,6 +87,7 @@ struct scsi_init_func_params {
u8 reserved2[12];
};
+/* SCSI RQ/CQ/CMDQ firmware function init parameters */
struct scsi_init_func_queues {
struct regpair glbl_q_params_addr;
__le16 rq_buffer_size;
@@ -84,14 +95,14 @@ struct scsi_init_func_queues {
__le16 cmdq_num_entries;
u8 bdq_resource_id;
u8 q_validity;
-#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_MASK 0x1
-#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_SHIFT 0
-#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_MASK 0x1
-#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_SHIFT 1
-#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_MASK 0x1
-#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_SHIFT 2
-#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_MASK 0x1F
-#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_SHIFT 3
+#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_MASK 0x1
+#define SCSI_INIT_FUNC_QUEUES_RQ_VALID_SHIFT 0
+#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_MASK 0x1
+#define SCSI_INIT_FUNC_QUEUES_IMM_DATA_VALID_SHIFT 1
+#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_MASK 0x1
+#define SCSI_INIT_FUNC_QUEUES_CMD_VALID_SHIFT 2
+#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_MASK 0x1F
+#define SCSI_INIT_FUNC_QUEUES_RESERVED_VALID_SHIFT 3
u8 num_queues;
u8 queue_relative_offset;
u8 cq_sb_pi;
@@ -107,16 +118,19 @@ struct scsi_init_func_queues {
__le32 reserved1;
};
+/* Scsi Drv BDQ Data struct (2 BDQ IDs: 0 - RQ, 1 - Immediate Data) */
struct scsi_ram_per_bdq_resource_drv_data {
struct scsi_bdq_ram_drv_data drv_data_per_bdq_id[BDQ_NUM_IDS];
};
+/* SCSI SGL types */
enum scsi_sgl_mode {
SCSI_TX_SLOW_SGL,
SCSI_FAST_SGL,
MAX_SCSI_SGL_MODE
};
+/* SCSI SGL parameters */
struct scsi_sgl_params {
struct regpair sgl_addr;
__le32 sgl_total_length;
@@ -126,6 +140,7 @@ struct scsi_sgl_params {
u8 reserved;
};
+/* SCSI terminate connection params */
struct scsi_terminate_extra_params {
__le16 unsolicited_cq_count;
__le16 cmdq_count;
diff --git a/include/linux/qed/tcp_common.h b/include/linux/qed/tcp_common.h
index dbf7a43..65b95fd 100644
--- a/include/linux/qed/tcp_common.h
+++ b/include/linux/qed/tcp_common.h
@@ -33,8 +33,13 @@
#ifndef __TCP_COMMON__
#define __TCP_COMMON__
-#define TCP_INVALID_TIMEOUT_VAL -1
+/********************/
+/* TCP FW CONSTANTS */
+/********************/
+#define TCP_INVALID_TIMEOUT_VAL -1
+
+/* OOO opaque data received from LL2 */
struct ooo_opaque {
__le32 cid;
u8 drop_isle;
@@ -43,25 +48,29 @@ struct ooo_opaque {
u8 ooo_isle;
};
+/* tcp connect mode enum */
enum tcp_connect_mode {
TCP_CONNECT_ACTIVE,
TCP_CONNECT_PASSIVE,
MAX_TCP_CONNECT_MODE
};
+/* tcp function init parameters */
struct tcp_init_params {
__le32 two_msl_timer;
__le16 tx_sws_timer;
- u8 maxfinrt;
+ u8 max_fin_rt;
u8 reserved[9];
};
+/* tcp IPv4/IPv6 enum */
enum tcp_ip_version {
TCP_IPV4,
TCP_IPV6,
MAX_TCP_IP_VERSION
};
+/* tcp offload parameters */
struct tcp_offload_params {
__le16 local_mac_addr_lo;
__le16 local_mac_addr_mid;
@@ -71,22 +80,22 @@ struct tcp_offload_params {
__le16 remote_mac_addr_hi;
__le16 vlan_id;
u8 flags;
-#define TCP_OFFLOAD_PARAMS_TS_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_TS_EN_SHIFT 0
-#define TCP_OFFLOAD_PARAMS_DA_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_DA_EN_SHIFT 1
-#define TCP_OFFLOAD_PARAMS_KA_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_KA_EN_SHIFT 2
-#define TCP_OFFLOAD_PARAMS_NAGLE_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_NAGLE_EN_SHIFT 3
-#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_SHIFT 4
-#define TCP_OFFLOAD_PARAMS_FIN_SENT_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_FIN_SENT_SHIFT 5
-#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_SHIFT 6
-#define TCP_OFFLOAD_PARAMS_RESERVED0_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_RESERVED0_SHIFT 7
+#define TCP_OFFLOAD_PARAMS_TS_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_TS_EN_SHIFT 0
+#define TCP_OFFLOAD_PARAMS_DA_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_DA_EN_SHIFT 1
+#define TCP_OFFLOAD_PARAMS_KA_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_KA_EN_SHIFT 2
+#define TCP_OFFLOAD_PARAMS_NAGLE_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_NAGLE_EN_SHIFT 3
+#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_DA_CNT_EN_SHIFT 4
+#define TCP_OFFLOAD_PARAMS_FIN_SENT_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_FIN_SENT_SHIFT 5
+#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_FIN_RECEIVED_SHIFT 6
+#define TCP_OFFLOAD_PARAMS_RESERVED0_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_RESERVED0_SHIFT 7
u8 ip_version;
__le32 remote_ip[4];
__le32 local_ip[4];
@@ -132,6 +141,7 @@ struct tcp_offload_params {
__le32 reserved3[2];
};
+/* tcp offload parameters */
struct tcp_offload_params_opt2 {
__le16 local_mac_addr_lo;
__le16 local_mac_addr_mid;
@@ -141,14 +151,14 @@ struct tcp_offload_params_opt2 {
__le16 remote_mac_addr_hi;
__le16 vlan_id;
u8 flags;
-#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_SHIFT 0
-#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_SHIFT 1
-#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_MASK 0x1
-#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_SHIFT 2
-#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_MASK 0x1F
-#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_SHIFT 3
+#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_OPT2_TS_EN_SHIFT 0
+#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_OPT2_DA_EN_SHIFT 1
+#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_MASK 0x1
+#define TCP_OFFLOAD_PARAMS_OPT2_KA_EN_SHIFT 2
+#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_MASK 0x1F
+#define TCP_OFFLOAD_PARAMS_OPT2_RESERVED0_SHIFT 3
u8 ip_version;
__le32 remote_ip[4];
__le32 local_ip[4];
@@ -166,6 +176,7 @@ struct tcp_offload_params_opt2 {
__le32 reserved1[22];
};
+/* tcp IPv4/IPv6 enum */
enum tcp_seg_placement_event {
TCP_EVENT_ADD_PEN,
TCP_EVENT_ADD_NEW_ISLE,
@@ -177,40 +188,41 @@ enum tcp_seg_placement_event {
MAX_TCP_SEG_PLACEMENT_EVENT
};
+/* tcp init parameters */
struct tcp_update_params {
__le16 flags;
-#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_SHIFT 0
-#define TCP_UPDATE_PARAMS_MSS_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_MSS_CHANGED_SHIFT 1
-#define TCP_UPDATE_PARAMS_TTL_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_TTL_CHANGED_SHIFT 2
-#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_SHIFT 3
-#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 4
-#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_SHIFT 5
-#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_SHIFT 6
-#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_SHIFT 7
-#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 8
-#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_SHIFT 9
-#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_SHIFT 10
-#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_MASK 0x1
-#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_SHIFT 11
-#define TCP_UPDATE_PARAMS_KA_EN_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_EN_SHIFT 12
-#define TCP_UPDATE_PARAMS_NAGLE_EN_MASK 0x1
-#define TCP_UPDATE_PARAMS_NAGLE_EN_SHIFT 13
-#define TCP_UPDATE_PARAMS_KA_RESTART_MASK 0x1
-#define TCP_UPDATE_PARAMS_KA_RESTART_SHIFT 14
-#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_MASK 0x1
-#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_SHIFT 15
+#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_REMOTE_MAC_ADDR_CHANGED_SHIFT 0
+#define TCP_UPDATE_PARAMS_MSS_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_MSS_CHANGED_SHIFT 1
+#define TCP_UPDATE_PARAMS_TTL_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_TTL_CHANGED_SHIFT 2
+#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_TOS_OR_TC_CHANGED_SHIFT 3
+#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_TIMEOUT_CHANGED_SHIFT 4
+#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_INTERVAL_CHANGED_SHIFT 5
+#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_MAX_RT_TIME_CHANGED_SHIFT 6
+#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_FLOW_LABEL_CHANGED_SHIFT 7
+#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_INITIAL_RCV_WND_CHANGED_SHIFT 8
+#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_MAX_PROBE_CNT_CHANGED_SHIFT 9
+#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_EN_CHANGED_SHIFT 10
+#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_MASK 0x1
+#define TCP_UPDATE_PARAMS_NAGLE_EN_CHANGED_SHIFT 11
+#define TCP_UPDATE_PARAMS_KA_EN_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_EN_SHIFT 12
+#define TCP_UPDATE_PARAMS_NAGLE_EN_MASK 0x1
+#define TCP_UPDATE_PARAMS_NAGLE_EN_SHIFT 13
+#define TCP_UPDATE_PARAMS_KA_RESTART_MASK 0x1
+#define TCP_UPDATE_PARAMS_KA_RESTART_SHIFT 14
+#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_MASK 0x1
+#define TCP_UPDATE_PARAMS_RETRANSMIT_RESTART_SHIFT 15
__le16 remote_mac_addr_lo;
__le16 remote_mac_addr_mid;
__le16 remote_mac_addr_hi;
@@ -226,6 +238,7 @@ struct tcp_update_params {
u8 reserved1[7];
};
+/* toe upload parameters */
struct tcp_upload_params {
__le32 rcv_next;
__le32 snd_una;