drm/i915: Extract skl_calc_cdclk()
We have many places where we want to pick a suitable cdclk frequency for
skl based on the dotclock and lcpll vco. Split that code into a small
helper and call it from all over.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1463172100-24715-5-git-send-email-ville.syrjala@linux.intel.com
Reviewed-by: Imre Deak <imre.deak@intel.com>
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 964e964..78f3918 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5447,6 +5447,30 @@
broxton_set_cdclk(dev_priv, 19200);
}
+static int skl_calc_cdclk(int max_pixclk, int vco)
+{
+ if (vco == 8640) {
+ if (max_pixclk > 540000)
+ return 617140;
+ else if (max_pixclk > 432000)
+ return 540000;
+ else if (max_pixclk > 308570)
+ return 432000;
+ else
+ return 308570;
+ } else {
+ /* VCO 8100 */
+ if (max_pixclk > 540000)
+ return 675000;
+ else if (max_pixclk > 450000)
+ return 540000;
+ else if (max_pixclk > 337500)
+ return 450000;
+ else
+ return 337500;
+ }
+}
+
static const struct skl_cdclk_entry {
unsigned int freq;
unsigned int vco;
@@ -5477,15 +5501,10 @@
static void
skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
{
- int min_cdclk;
+ int min_cdclk = skl_calc_cdclk(0, vco);
u32 val;
/* select the minimum CDCLK before enabling DPLL 0 */
- if (vco == 8640)
- min_cdclk = 308570;
- else
- min_cdclk = 337500;
-
val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_cdclk);
I915_WRITE(CDCLK_CTL, val);
POSTING_READ(CDCLK_CTL);
@@ -5497,7 +5516,7 @@
* 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
* The modeset code is responsible for the selection of the exact link
* rate later on, with the constraint of choosing a frequency that
- * works with required_vco.
+ * works with vco.
*/
val = I915_READ(DPLL_CTRL1);
@@ -5626,7 +5645,7 @@
if (dev_priv->skl_vco_freq != 8640)
dev_priv->skl_vco_freq = 8100;
skl_dpll0_enable(dev_priv, dev_priv->skl_vco_freq);
- cdclk = ((dev_priv->skl_vco_freq == 8100) ? 337500 : 308570);
+ cdclk = skl_calc_cdclk(0, dev_priv->skl_vco_freq);
} else {
cdclk = dev_priv->cdclk_freq;
}
@@ -9650,34 +9669,14 @@
struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
struct drm_i915_private *dev_priv = to_i915(state->dev);
const int max_pixclk = ilk_max_pixel_rate(state);
+ int vco = intel_state->cdclk_pll_vco;
int cdclk;
/*
* FIXME should also account for plane ratio
* once 64bpp pixel formats are supported.
*/
-
- if (intel_state->cdclk_pll_vco == 8640) {
- /* vco 8640 */
- if (max_pixclk > 540000)
- cdclk = 617140;
- else if (max_pixclk > 432000)
- cdclk = 540000;
- else if (max_pixclk > 308570)
- cdclk = 432000;
- else
- cdclk = 308570;
- } else {
- /* VCO 8100 */
- if (max_pixclk > 540000)
- cdclk = 675000;
- else if (max_pixclk > 450000)
- cdclk = 540000;
- else if (max_pixclk > 337500)
- cdclk = 450000;
- else
- cdclk = 337500;
- }
+ cdclk = skl_calc_cdclk(max_pixclk, vco);
/*
* FIXME move the cdclk caclulation to
@@ -9691,9 +9690,7 @@
intel_state->cdclk = intel_state->dev_cdclk = cdclk;
if (!intel_state->active_crtcs)
- intel_state->dev_cdclk = ((intel_state->cdclk_pll_vco == 8640) ?
- 308570 : 337500);
-
+ intel_state->dev_cdclk = skl_calc_cdclk(0, vco);
return 0;
}