| commit | a967a289f16969527a8a41e261695c639a69bee4 | [log] [tgz] |
|---|---|---|
| author | Yash Shah <yash.shah@sifive.com> | Mon May 06 16:18:40 2019 +0530 |
| committer | Palmer Dabbelt <palmer@sifive.com> | Thu May 16 20:42:13 2019 -0700 |
| tree | eda00cc7ecc719a9ed5e9cb82d27b64fb929d4fa | |
| parent | 5545b6d1ba25ce4a3a339b1edb760e666e693599 [diff] |
RISC-V: sifive_l2_cache: Add L2 cache controller driver for SiFive SoCs The driver currently supports only SiFive FU540-C000 platform. The initial version of L2 cache controller driver includes: - Initial configuration reporting at boot up. - Support for ECC related functionality. Signed-off-by: Yash Shah <yash.shah@sifive.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>