tree 00bda32e2c6da757ada25afcb8abd81996d6e6d3
parent f4154e160aa2a40dccc963110768b63ce004fed9
author Liu Yu <yu.liu@freescale.com> 1295935333 +0800
committer Kumar Gala <galak@kernel.crashing.org> 1300201506 -0500

powerpc/85xx: Workaroudn e500 CPU erratum A005

This erratum can occur if a single-precision floating-point,
double-precision floating-point or vector floating-point instruction on a
mispredicted branch path signals one of the floating-point data interrupts
which are enabled by the SPEFSCR (FINVE, FDBZE, FUNFE or FOVFE bits).  This
interrupt must be recorded in a one-cycle window when the misprediction is
resolved.  If this extremely rare event should occur, the result could be:

The SPE Data Exception from the mispredicted path may be reported
erroneously if a single-precision floating-point, double-precision
floating-point or vector floating-point instruction is the second
instruction on the correct branch path.

According to errata description, some efp instructions which are not
supposed to trigger SPE exceptions can trigger the exceptions in this case.
However, as we haven't emulated these instructions here, a signal will
send to userspace, and userspace application would exit.

This patch re-issue the efp instruction that we haven't emulated,
so that hardware can properly execute it again if this case happen.

Signed-off-by: Liu Yu <yu.liu@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>