| commit | ae9ec62bdadc4cd3bf893d6baced80aa3a5dbbd6 | [log] [tgz] |
|---|---|---|
| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | Tue Mar 15 16:40:05 2016 +0200 |
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | Tue Apr 12 21:12:02 2016 +0300 |
| tree | 97329e1675016aa44a43ebb7eccbb378ff473e35 | |
| parent | f00b56896ec2443a33277f5411de0cbd13071cec [diff] [blame] |
drm/i915: Fix CHV DSI PLL refclk during state readout Use the proper refclock frequency (100MHz) when reading out the current DSI clock on CHV. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Link: http://patchwork.freedesktop.org/patch/msgid/1458052809-23426-13-git-send-email-ville.syrjala@linux.intel.com Reviewed-by: Jani Nikula <jani.nikula@intel.com>
diff --git a/drivers/gpu/drm/i915/intel_dsi_pll.c b/drivers/gpu/drm/i915/intel_dsi_pll.c index bd17465..7ad59d1 100644 --- a/drivers/gpu/drm/i915/intel_dsi_pll.c +++ b/drivers/gpu/drm/i915/intel_dsi_pll.c
@@ -258,7 +258,7 @@ u32 dsi_clock, pclk; u32 pll_ctl, pll_div; u32 m = 0, p = 0, n; - int refclk = 25000; + int refclk = IS_CHERRYVIEW(dev_priv) ? 100000 : 25000; int i; DRM_DEBUG_KMS("\n");