PCI: designware: Require config accesses to be naturally aligned
Add sanity checks on "addr" input parameter in dw_pcie_cfg_read() and
dw_pcie_cfg_write(). These checks make sure that accesses are aligned on
their size, e.g., a 4-byte config access is aligned on a 4-byte boundary.
[bhelgaas: changelog, set *val = 0 in failure case]
Signed-off-by: Gabriele Paoloni <gabriele.paoloni@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Pratyush Anand <pratyush.anand@gmail.com>
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c
index 759cd0a..b77535f 100644
--- a/drivers/pci/host/pcie-designware.c
+++ b/drivers/pci/host/pcie-designware.c
@@ -82,6 +82,11 @@
int dw_pcie_cfg_read(void __iomem *addr, int size, u32 *val)
{
+ if ((uintptr_t)addr & (size - 1)) {
+ *val = 0;
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+ }
+
if (size == 4)
*val = readl(addr);
else if (size == 2)
@@ -98,6 +103,9 @@
int dw_pcie_cfg_write(void __iomem *addr, int size, u32 val)
{
+ if ((uintptr_t)addr & (size - 1))
+ return PCIBIOS_BAD_REGISTER_NUMBER;
+
if (size == 4)
writel(val, addr);
else if (size == 2)