| commit | b9490350f751e5d17a24d0ae5af1f9e7f55c7c31 | [log] [tgz] |
|---|---|---|
| author | Christoph Hellwig <hch@lst.de> | Sat Aug 04 10:23:12 2018 +0200 |
| committer | Palmer Dabbelt <palmer@sifive.com> | Mon Aug 13 08:31:30 2018 -0700 |
| tree | fd0b8871c4c79a33885b709ed807fdcb29617952 | |
| parent | 5b5c2a2c44d7225ab3abbcc7e1881b97ea9872dd [diff] |
RISC-V: remove timer leftovers This code is currently unused and will be added back later in a different place with the real interrupt and clocksource support. Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>