tree 47dceef62f8f8fd2ae3777a1b76674f04a99bcaa
parent 6354a06cbaa8c49d8377a6cee3e7db399c23601c
author Nickey Yang <nickey.yang@rock-chips.com> 1505725537 +0800
committer Heiko Stuebner <heiko@sntech.de> 1505841910 +0200

arm64: dts: rockchip: Correct MIPI DPHY PLL clock on rk3399

There is a further gate in between the mipidphy reference clock and the
actual ref-clock input to the dsi host, making the clock hirarchy look like
clk_24m --> Gate11[14] --> clk_mipidphy_ref --> Gate21[0] --> clk_dphy_pll

Fix the clock reference so that the whole clock subtree gets enabled when
the dsi host needs it.

Signed-off-by: Nickey Yang <nickey.yang@rock-chips.com>
[amended commit message]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>