tree 92cdfa8bfd348cacb28b4cd70117afe5d762ec8d
parent a7ef1eaddbf4bd50bfee92d9dfbecadc61467bbf
author Kevin Cernekee <cernekee@gmail.com> 1413865678 -0700
committer Ralf Baechle <ralf@linux-mips.org> 1416811511 +0100

MIPS: BMIPS: Select the appropriate L1_CACHE_SHIFT for 438x and 5000 CPUs

BMIPS438x has a 64-byte D$ line size and BMIPS5000 has a 128-byte L2
line size.  If L1_CACHE_SHIFT is undersized, DMA buffers will not be
cacheline-aligned and terrible things will happen.

Signed-off-by: Kevin Cernekee <cernekee@gmail.com>
Cc: f.fainelli@gmail.com
Cc: mbizon@freebox.fr
Cc: jogo@openwrt.org
Cc: jfraser@broadcom.com
Cc: linux-mips@linux-mips.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/8164/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>