commit bc2481f313a05887f0b650555d289dcee5c46d8b
author Daniel Vetter <daniel.vetter@ffwll.ch> Tue May 08 15:18:32 2012 +0200
committer Daniel Vetter <daniel.vetter@ffwll.ch> Tue May 08 15:38:19 2012 +0200
tree 3a08ad20b08e7c587d0485dae97c336777e0d0f4
parent a3da1df7bd1697ff661f7fd310a893815fa52391

drm/i915: s/intel_infoframe/gm45_infoframe

These two functions are actually hw-specific and only valid for gm45
thru gen7. HSW completely changes how this works, so label them
accordingly.

v2: s/gm45/g4x/ like for the previous patch.

Acked-by: Paulo Zanoni <przanoni@gmail.com>
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

drivers/gpu/drm/i915/intel_hdmi.c

diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 4db8d74..e240d99 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -75,7 +75,7 @@
 	frame->checksum = 0x100 - sum;
 }
 
-static u32 intel_infoframe_index(struct dip_infoframe *frame)
+static u32 g4x_infoframe_index(struct dip_infoframe *frame)
 {
 	u32 flags = 0;
 
@@ -94,7 +94,7 @@
 	return flags;
 }
 
-static u32 intel_infoframe_enable(struct dip_infoframe *frame)
+static u32 g4x_infoframe_enable(struct dip_infoframe *frame)
 {
 	u32 flags = 0;
 
@@ -134,9 +134,9 @@
 		return;
 
 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
-	val |= intel_infoframe_index(frame);
+	val |= g4x_infoframe_index(frame);
 
-	val &= ~intel_infoframe_enable(frame);
+	val &= ~g4x_infoframe_enable(frame);
 	val |= VIDEO_DIP_ENABLE;
 
 	I915_WRITE(VIDEO_DIP_CTL, val);
@@ -146,7 +146,7 @@
 		data++;
 	}
 
-	val |= intel_infoframe_enable(frame);
+	val |= g4x_infoframe_enable(frame);
 	val &= ~VIDEO_DIP_FREQ_MASK;
 	val |= VIDEO_DIP_FREQ_VSYNC;
 
@@ -184,9 +184,9 @@
 	intel_wait_for_vblank(dev, intel_crtc->pipe);
 
 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
-	val |= intel_infoframe_index(frame);
+	val |= g4x_infoframe_index(frame);
 
-	val &= ~intel_infoframe_enable(frame);
+	val &= ~g4x_infoframe_enable(frame);
 	val |= VIDEO_DIP_ENABLE;
 
 	I915_WRITE(reg, val);
@@ -196,7 +196,7 @@
 		data++;
 	}
 
-	val |= intel_infoframe_enable(frame);
+	val |= g4x_infoframe_enable(frame);
 	val &= ~VIDEO_DIP_FREQ_MASK;
 	val |= VIDEO_DIP_FREQ_VSYNC;
 
@@ -218,14 +218,14 @@
 	intel_wait_for_vblank(dev, intel_crtc->pipe);
 
 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
-	val |= intel_infoframe_index(frame);
+	val |= g4x_infoframe_index(frame);
 
 	/* The DIP control register spec says that we need to update the AVI
 	 * infoframe without clearing its enable bit */
 	if (frame->type == DIP_TYPE_AVI)
 		val |= VIDEO_DIP_ENABLE_AVI;
 	else
-		val &= ~intel_infoframe_enable(frame);
+		val &= ~g4x_infoframe_enable(frame);
 
 	val |= VIDEO_DIP_ENABLE;
 
@@ -236,7 +236,7 @@
 		data++;
 	}
 
-	val |= intel_infoframe_enable(frame);
+	val |= g4x_infoframe_enable(frame);
 	val &= ~VIDEO_DIP_FREQ_MASK;
 	val |= VIDEO_DIP_FREQ_VSYNC;
 
@@ -258,9 +258,9 @@
 	intel_wait_for_vblank(dev, intel_crtc->pipe);
 
 	val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
-	val |= intel_infoframe_index(frame);
+	val |= g4x_infoframe_index(frame);
 
-	val &= ~intel_infoframe_enable(frame);
+	val &= ~g4x_infoframe_enable(frame);
 	val |= VIDEO_DIP_ENABLE;
 
 	I915_WRITE(reg, val);
@@ -270,7 +270,7 @@
 		data++;
 	}
 
-	val |= intel_infoframe_enable(frame);
+	val |= g4x_infoframe_enable(frame);
 	val &= ~VIDEO_DIP_FREQ_MASK;
 	val |= VIDEO_DIP_FREQ_VSYNC;