spi: sh-msiof: Add support for R-Car H2 and M2
Add support for the MSIOF variant in the R-Car H2 (r8a7790) and M2
(r8a7791) SoCs.
Binding documentation:
- Add future-proof "renesas,msiof-<soctype>" compatible values,
- The default for "renesas,rx-fifo-size" is 256 on R-Car H2 and M2,
- "renesas,tx-fifo-size" and "renesas,rx-fifo-size" are deprecated for
soctype-specific bindings,
- Add example bindings.
Implementation:
- MSIOF on R-Car H2 and M2 requires the transmission of dummy data if
data is being received only (cfr. "Set SICTR.TSCKE to 1" and "Write
dummy transmission data to SITFDR" in paragraph "Transmit and Receive
Procedures" of the Hardware User's Manual).
- As RX depends on TX, MSIOF on R-Car H2 and M2 also lacks the RSCR
register (Receive Clock Select Register), and some bits in the RMDR1
(Receive Mode Register 1) and TMDR2 (Transmit Mode Register 2)
registers.
- Use the recently introduced SPI_MASTER_MUST_TX flag to enable support
for dummy transmission in the SPI core, and to differentiate from other
MSIOF implementations in code paths that need this.
- New DT compatible values ("renesas,msiof-r8a7790" and
"renesas,msiof-r8a7791") are added, as well as new platform device
names ("spi_r8a7790_msiof" and "spi_r8a7791_msiof").
- The default RX FIFO size is 256 words on R-Car H2 and M2.
This is loosely based on a set of patches from Takashi Yoshii
<takasi-y@ops.dti.ne.jp>.
Signed-off-by: Geert Uytterhoeven <geert+renesas@linux-m68k.org>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Mark Brown <broonie@linaro.org>
diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 38d6b70..e7f4797 100644
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -35,6 +35,7 @@
struct sh_msiof_chipdata {
u16 tx_fifo_size;
u16 rx_fifo_size;
+ u16 master_flags;
};
struct sh_msiof_spi_priv {
@@ -215,7 +216,8 @@
k = min_t(int, k, ARRAY_SIZE(sh_msiof_spi_clk_table) - 1);
sh_msiof_write(p, TSCR, sh_msiof_spi_clk_table[k].scr);
- sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
+ if (!(p->chipdata->master_flags & SPI_MASTER_MUST_TX))
+ sh_msiof_write(p, RSCR, sh_msiof_spi_clk_table[k].scr);
}
static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p,
@@ -238,6 +240,10 @@
tmp |= !cs_high << MDR1_SYNCAC_SHIFT;
tmp |= lsb_first << MDR1_BITLSB_SHIFT;
sh_msiof_write(p, TMDR1, tmp | MDR1_TRMD | TMDR1_PCON);
+ if (p->chipdata->master_flags & SPI_MASTER_MUST_TX) {
+ /* These bits are reserved if RX needs TX */
+ tmp &= ~0x0000ffff;
+ }
sh_msiof_write(p, RMDR1, tmp);
tmp = 0;
@@ -258,7 +264,7 @@
{
u32 dr2 = MDR2_BITLEN1(bits) | MDR2_WDLEN1(words);
- if (tx_buf)
+ if (tx_buf || (p->chipdata->master_flags & SPI_MASTER_MUST_TX))
sh_msiof_write(p, TMDR2, dr2);
else
sh_msiof_write(p, TMDR2, dr2 | MDR2_GRPMASK1);
@@ -666,11 +672,20 @@
static const struct sh_msiof_chipdata sh_data = {
.tx_fifo_size = 64,
.rx_fifo_size = 64,
+ .master_flags = 0,
+};
+
+static const struct sh_msiof_chipdata r8a779x_data = {
+ .tx_fifo_size = 64,
+ .rx_fifo_size = 256,
+ .master_flags = SPI_MASTER_MUST_TX,
};
static const struct of_device_id sh_msiof_match[] = {
{ .compatible = "renesas,sh-msiof", .data = &sh_data },
{ .compatible = "renesas,sh-mobile-msiof", .data = &sh_data },
+ { .compatible = "renesas,msiof-r8a7790", .data = &r8a779x_data },
+ { .compatible = "renesas,msiof-r8a7791", .data = &r8a779x_data },
{},
};
MODULE_DEVICE_TABLE(of, sh_msiof_match);
@@ -790,7 +805,7 @@
/* init master and bitbang code */
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
master->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE;
- master->flags = 0;
+ master->flags = p->chipdata->master_flags;
master->bus_num = pdev->id;
master->dev.of_node = pdev->dev.of_node;
master->num_chipselect = p->info->num_chipselect;
@@ -833,6 +848,8 @@
static struct platform_device_id spi_driver_ids[] = {
{ "spi_sh_msiof", (kernel_ulong_t)&sh_data },
+ { "spi_r8a7790_msiof", (kernel_ulong_t)&r8a779x_data },
+ { "spi_r8a7791_msiof", (kernel_ulong_t)&r8a779x_data },
{},
};
MODULE_DEVICE_TABLE(platform, spi_driver_ids);