| commit | bf83fd6402a856eeb9a22c364c50ccf9bbdf9b17 | [log] [tgz] |
|---|---|---|
| author | Qipan Li <Qipan.Li@csr.com> | Mon Apr 14 14:30:01 2014 +0800 |
| committer | Mark Brown <broonie@linaro.org> | Mon Apr 14 21:04:59 2014 +0100 |
| tree | 905fe272f9d08fff5e4483294b8e96c6b26e59e6 | |
| parent | d77ec5df47696300b9498e6973dcc34b40de8d27 [diff] |
spi: sirf: fix spi full-duplex DMA transferring issue sometimes t->tx can be equal with t->rx. for example, spidev will make tx and rx point to spidev->buffer at the same time. currently, for this case, we map the buffer BIDIRECTION to fix the cache consistency. Signed-off-by: Qipan Li <Qipan.Li@csr.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Mark Brown <broonie@linaro.org>