tree 539d40f333d17c6d1789504297d95fe505e192b1
parent b0103747094b62231fc951dfaca4897f67670874
author Roy Spliet <r.spliet@student.tudelft.nl> 1322232742 +0100
committer Ben Skeggs <bskeggs@redhat.com> 1331622386 +1000

drm/nouveau/pm: improve memory timing generation

- Rename several VBIOS entries to closer match the real world
- Add the missing 0x100238 and 0x100240 register values
- Parse bit 14 of the VBIOS timing table
- "Magic value" -> tCWL, fixing some minor bugs in the process
- Also name a few more by their name rather than their number.
- Some values seem to be dependent on the memory type. Fix

Edits by Martin Peres <martin.peres@labri.fr>:
- this is a squash commit
- reworked for fixing some style issues

Signed-off-by: Roy Spliet <r.spliet@student.tudelft.nl>
Signed-off-by: Martin Peres <martin.peres@labri.fr>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>