tree 30bfdeed6283bfb603cad43a5519a09c75570dc4
parent 43e36a9646ec7d0180d638c095cca36484cc6f82
author Thierry Reding <thierry.reding@gmail.com> 1383061872 +0100
committer Peter De Schrijver <pdeschrijver@nvidia.com> 1385484417 +0200

clk: tegra: Properly setup PWM clock on Tegra30

The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.

Signed-off-by: Thierry Reding <treding@nvidia.com>