tree a0b178eef5c305881beaf0e76c8e82a03b74772d
parent dbee90b7f90df6398f0877cd38dfaa76addb0619
author Atsushi Nemoto <anemo@mba.ocn.ne.jp> 1138898041 +0900
committer Ralf Baechle <ralf@linux-mips.org> 1139319026 +0000

[MIPS] TX49 MFC0 bug workaround
    
If mfc0 $12 follows store and the mfc0 is last instruction of a
page and fetching the next instruction causes TLB miss, the result
of the mfc0 might wrongly contain EXL bit.
    
ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
    
Workaround: mask EXL bit of the result or place a nop before mfc0.  It
doesn't harm to always clear those bits, so we change the code to do so.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>