tree 0f957ea927d32ea9691dee48a663581d7ca341c3
parent 33ca29c99e8680b4c921c6eafb9fc1603c5b9779
author Tony Lindgren <tony@atomide.com> 1426554260 -0700
committer Tero Kristo <t-kristo@ti.com> 1427221565 +0200

clk: ti: Implement FAPLL set_rate for the synthesizer

We can pretty much get any rate out of the FAPLL because of the fractional
divider. Let's first try just adjusting the post divider, and if that is
not enough, then reprogram both the fractional divider and the post divider.

Let's also add a define for the fixed SYNTH_PHASE_K instead of using 8.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Matthijs van Duin <matthijsvanduin@gmail.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>