| commit | ce8f407a3cc7fc58804b9135e7c8780f0f8c2a8d | [log] [tgz] |
|---|---|---|
| author | Hariprasad Shenai <hariprasad@chelsio.com> | Fri Nov 07 17:06:30 2014 +0530 |
| committer | David S. Miller <davem@davemloft.net> | Mon Nov 10 14:15:03 2014 -0500 |
| tree | adaef931f4064d2969ca78d987dccace85607d3a | |
| parent | 65f6ecc93e7cca888a96a68cf6b5292dff1982b6 [diff] |
cxgb4/cxgb4vf: For T5 use Packing and Padding Boundaries for SGE DMA transfers T5 introduces the ability to have separate Packing and Padding Boundaries for SGE DMA transfers from the chip to Host Memory. This change set takes advantage of that to set up a smaller Padding Boundary to conserve PCI Link and Memory Bandwidth with T5. Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>