tree fd06434007fcccbcb3bb81ceb134671e0d461a2a
parent fa9f3a526459ef33f1ca54aad231c5a23071f37f
author Alim Akhtar <alim.akhtar@samsung.com> 1440559842 +0530
committer Sylwester Nawrocki <s.nawrocki@samsung.com> 1442307568 +0200

clk: samsung: exynos7: Fix CMU TOP1 block

As per UM, sclk_mmc2 is bit 16 of SEL_TOP1_FSYS0. Also the DIV
and the GATE clocks are at bit 16 in their respective registers.
For mmc1 and mmc0 clock MUXs are in TOP1_FSYS11 instead of TOP1_FSYS1.
And their DIV and GATE clks are in xxx_TOP1_FSYS11 instead of TOP1_FSYS1.
This patch corrects it.
This also adds xxx_FSYS11 to be saved/restore during s2r cycles.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>