tree ba6286ba53298271070c217492f39bdb259681e4
parent 736561a01f11114146b1b7f82d486fa9c95828ef
author Steve Hodgson <shodgson@solarflare.com> 1300823203 +0000
committer Ben Hutchings <bhutchings@solarflare.com> 1300844115 +0000

sfc: Siena: Disable write-combining when SR-IOV is enabled

If SR-IOV is enabled by firmware, even if it is not enabled in the PCI
capability, TX pushes using write-combining may be corrupted.

We want to know whether it is enabled before mapping the NIC
registers, and even if PCI extended capabilities are not accessible.
Therefore, we look for the MSI capability, which is removed if SR-IOV
is enabled.

Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>