| commit | d927daf5c81c9b6bf2d6a83dc4c8c60268930ee5 | [log] [tgz] |
|---|---|---|
| author | Pawel Moll <pawel.moll@arm.com> | Tue Jun 12 16:14:03 2012 +0100 |
| committer | Pawel Moll <pawel.moll@arm.com> | Thu Jul 12 16:16:56 2012 +0100 |
| tree | e0a45cf8833d54d2b811b1b5a9635b3b8c844084 | |
| parent | ef5911966d2312478a74e93d993cd623a869ab10 [diff] |
ARM: vexpress: Check master site in daughterboard's sysctl operations With recent enough motherboard firmware, core tile can be fitted in either of the two daughterboard sites. The non-DT tile code for V2P-CA9 did not check that when configuring DVI output nor setting CLCD pixel clock. Fixed now, providing "get master site" API in motherboard's code. Signed-off-by: Pawel Moll <pawel.moll@arm.com>