ARM: 6184/2: ux500: use neutral PRCMU base
The MTU wallclock timing fix-up patch was hardwired to the DB8500
causing a regression. This makes it work on the DB5500 as well.
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index fe84b90..0a1318f 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -131,7 +131,7 @@
*/
static unsigned long clk_mtu_get_rate(struct clk *clk)
{
- void __iomem *addr = __io_address(U8500_PRCMU_BASE)
+ void __iomem *addr = __io_address(UX500_PRCMU_BASE)
+ PRCM_TCR;
u32 tcr = readl(addr);
int mtu = (int) clk->data;