drm/bridge/sii8620: simplify MHL3 mode setting
It is not necessary to set REG_COC_CTL0, REG_MHL_COC_CTL1 registers.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Archit Taneja <architt@codeaurora.org>
Link: http://patchwork.freedesktop.org/patch/msgid/1485935272-17337-2-git-send-email-a.hajda@samsung.com
diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c
index b2c267d..68cdf63 100644
--- a/drivers/gpu/drm/bridge/sil-sii8620.c
+++ b/drivers/gpu/drm/bridge/sil-sii8620.c
@@ -974,12 +974,8 @@
);
break;
case CM_MHL3:
- sii8620_write_seq_static(ctx,
- REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE,
- REG_COC_CTL0, 0x40,
- REG_MHL_COC_CTL1, 0x07
- );
- break;
+ sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE);
+ return;
case CM_DISCONNECTED:
break;
default: