ARM: l2c: move L2 cache register saving to a more sensible location
Move the L2 cache register saving to a more sensible location - after
the cache has been enabled, and fixups have been run. We move the
saving of the auxiliary control register into the ->save function as
well which makes everything operate in a sane and maintainable way.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
diff --git a/arch/arm/mm/cache-l2x0.c b/arch/arm/mm/cache-l2x0.c
index 790343b..3a34db5 100644
--- a/arch/arm/mm/cache-l2x0.c
+++ b/arch/arm/mm/cache-l2x0.c
@@ -202,6 +202,11 @@
raw_spin_unlock_irqrestore(&l2x0_lock, flags);
}
+static void l2c_save(void __iomem *base)
+{
+ l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
+}
+
/*
* L2C-210 specific code.
*
@@ -295,6 +300,7 @@
.way_size_0 = SZ_8K,
.num_lock = 1,
.enable = l2c_enable,
+ .save = l2c_save,
.outer_cache = {
.inv_range = l2c210_inv_range,
.clean_range = l2c210_clean_range,
@@ -439,6 +445,7 @@
.way_size_0 = SZ_8K,
.num_lock = 1,
.enable = l2c_enable,
+ .save = l2c_save,
.outer_cache = {
.inv_range = l2c220_inv_range,
.clean_range = l2c220_clean_range,
@@ -575,6 +582,8 @@
{
unsigned revision;
+ l2c_save(base);
+
l2x0_saved_regs.tag_latency = readl_relaxed(base +
L310_TAG_LATENCY_CTRL);
l2x0_saved_regs.data_latency = readl_relaxed(base +
@@ -712,13 +721,6 @@
unsigned way_size_bits, ways;
u32 aux;
- /*
- * It is strange to save the register state before initialisation,
- * but hey, this is what the DT implementations decided to do.
- */
- if (data->save)
- data->save(l2x0_base);
-
aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
aux &= aux_mask;
@@ -777,14 +779,18 @@
if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN))
data->enable(l2x0_base, aux, data->num_lock);
+ outer_cache = fns;
+
+ /*
+ * It is strange to save the register state before initialisation,
+ * but hey, this is what the DT implementations decided to do.
+ */
+ if (data->save)
+ data->save(l2x0_base);
+
/* Re-read it in case some bits are reserved. */
aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
- /* Save the value for resuming. */
- l2x0_saved_regs.aux_ctrl = aux;
-
- outer_cache = fns;
-
pr_info("%s cache controller enabled, %d ways, %d kB\n",
data->type, ways, l2x0_size >> 10);
pr_info("%s: CACHE_ID 0x%08x, AUX_CTRL 0x%08x\n",
@@ -865,6 +871,7 @@
.num_lock = 1,
.of_parse = l2x0_of_parse,
.enable = l2c_enable,
+ .save = l2c_save,
.outer_cache = {
.inv_range = l2c210_inv_range,
.clean_range = l2c210_clean_range,
@@ -882,6 +889,7 @@
.num_lock = 1,
.of_parse = l2x0_of_parse,
.enable = l2c_enable,
+ .save = l2c_save,
.outer_cache = {
.inv_range = l2c220_inv_range,
.clean_range = l2c220_clean_range,
@@ -1296,6 +1304,8 @@
static void __init tauros3_save(void __iomem *base)
{
+ l2c_save(base);
+
l2x0_saved_regs.aux2_ctrl =
readl_relaxed(base + TAUROS3_AUX2_CTRL);
l2x0_saved_regs.prefetch_ctrl =