nvidiafb: access CRT registers safely
Use Read/WriteCrtc() to access CRTC registers in nv_i2c.c. These are safer
because it uses the correct CRTC base (0x3bx or 0x3dx).
Signed-off-by: Antonino Daplas <adaplas@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
diff --git a/drivers/video/nvidia/nv_i2c.c b/drivers/video/nvidia/nv_i2c.c
index 4fc7118..afe4567 100644
--- a/drivers/video/nvidia/nv_i2c.c
+++ b/drivers/video/nvidia/nv_i2c.c
@@ -30,16 +30,14 @@
struct nvidia_par *par = chan->par;
u32 val;
- VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
- val = VGA_RD08(par->PCIO, 0x3d5) & 0xf0;
+ val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
if (state)
val |= 0x20;
else
val &= ~0x20;
- VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
- VGA_WR08(par->PCIO, 0x3d5, val | 0x1);
+ NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
}
static void nvidia_gpio_setsda(void *data, int state)
@@ -48,16 +46,14 @@
struct nvidia_par *par = chan->par;
u32 val;
- VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
- val = VGA_RD08(par->PCIO, 0x3d5) & 0xf0;
+ val = NVReadCrtc(par, chan->ddc_base + 1) & 0xf0;
if (state)
val |= 0x10;
else
val &= ~0x10;
- VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base + 1);
- VGA_WR08(par->PCIO, 0x3d5, val | 0x1);
+ NVWriteCrtc(par, chan->ddc_base + 1, val | 0x01);
}
static int nvidia_gpio_getscl(void *data)
@@ -66,8 +62,7 @@
struct nvidia_par *par = chan->par;
u32 val = 0;
- VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base);
- if (VGA_RD08(par->PCIO, 0x3d5) & 0x04)
+ if (NVReadCrtc(par, chan->ddc_base) & 0x04)
val = 1;
return val;
@@ -79,8 +74,7 @@
struct nvidia_par *par = chan->par;
u32 val = 0;
- VGA_WR08(par->PCIO, 0x3d4, chan->ddc_base);
- if (VGA_RD08(par->PCIO, 0x3d5) & 0x08)
+ if (NVReadCrtc(par, chan->ddc_base) & 0x08)
val = 1;
return val;