drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfs
when cat pp_od_clk_voltage it show
OD_SCLK:
0: 300Mhz 800 mV
1: 466Mhz 818 mV
2: 751Mhz 824 mV
3: 1019Mhz 987 mV
4: 1074Mhz 1037 mV
5: 1126Mhz 1087 mV
6: 1169Mhz 1137 mV
7: 1206Mhz 1150 mV
OD_MCLK:
0: 300Mhz 800 mV
1: 1650Mhz 1000 mV
echo "s/m level clock voltage" to change
sclk/mclk's clock and voltage
echo "r" to restore default value.
echo "c" to commit the user setting.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
index 986f1d5..4b5755e 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.h
@@ -374,6 +374,10 @@ enum amdgpu_pcie_gen {
((adev)->powerplay.pp_funcs->set_power_profile_mode(\
(adev)->powerplay.pp_handle, parameter, size))
+#define amdgpu_dpm_odn_edit_dpm_table(adev, type, parameter, size) \
+ ((adev)->powerplay.pp_funcs->odn_edit_dpm_table(\
+ (adev)->powerplay.pp_handle, type, parameter, size))
+
struct amdgpu_dpm {
struct amdgpu_ps *ps;
/* number of valid power states */