tree 3aa5e2666bf5fccf0e4c61cf50030c839d7ef1b7
parent 1a748d2bc5061b72588013a720645661345c0e65
author Boris BREZILLON <b.brezillon@overkiz.com> 1381481483 +0200
committer Nicolas Ferre <nicolas.ferre@atmel.com> 1385994683 +0100

clk: at91: add PMC master clock

This patch adds new at91 master clock implementation using common clk
framework.

The master clock layout describe the MCKR register layout.
There are 2 master clock layouts:
- at91rm9200
- at91sam9x5

Master clocks are given characteristics:
- min/max clock output rate

These characteristics are checked during rate change to avoid
over/underclocking.

These characteristics are described in atmel's SoC datasheet in
"Electrical Characteristics" paragraph.

Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>