Merge "defconfig: gen3auto: add qseecom driver support"
diff --git a/android/GKI_VERSION b/android/GKI_VERSION
index 6e74fe0..7d9ecc8 100644
--- a/android/GKI_VERSION
+++ b/android/GKI_VERSION
@@ -1 +1 @@
-LTS_5.4.61_5327444e834f
+LTS_5.4.61_364ec3d27d09
diff --git a/android/abi_gki_aarch64_unisoc b/android/abi_gki_aarch64_unisoc
index e71275e..0ca6e1b 100644
--- a/android/abi_gki_aarch64_unisoc
+++ b/android/abi_gki_aarch64_unisoc
@@ -30,6 +30,7 @@
bpf_trace_run4
__breadahead
bus_register
+ bus_set_iommu
bus_unregister
call_rcu
cancel_delayed_work
@@ -110,6 +111,7 @@
device_destroy
device_initialize
device_init_wakeup
+ device_link_add
device_match_fwnode
device_match_name
device_property_present
@@ -180,6 +182,10 @@
drm_dev_register
drm_err
drm_ioctl
+ drm_mm_init
+ drm_mm_insert_node_in_range
+ drm_mm_remove_node
+ drm_mm_takedown
drm_mode_config_cleanup
drm_mode_config_init
drm_open
@@ -281,7 +287,11 @@
iommu_alloc_resv_region
iommu_attach_device
iommu_detach_device
+ iommu_device_link
iommu_device_register
+ iommu_device_sysfs_add
+ iommu_device_sysfs_remove
+ iommu_device_unlink
iommu_device_unregister
iommu_dma_get_resv_regions
iommu_domain_alloc
@@ -292,6 +302,7 @@
iommu_fwspec_free
iommu_get_dma_cookie
iommu_get_domain_for_dev
+ iommu_group_alloc
iommu_group_get
iommu_group_get_for_dev
iommu_group_get_iommudata
@@ -995,6 +1006,7 @@
skb_checksum_help
strim
xfrm_lookup
+ completion_done
# required by kfifo_buf.ko
devres_add
@@ -1144,6 +1156,7 @@
# required by pvrsrvkm.ko
autoremove_wake_function
+ bpf_trace_run6
bpf_trace_run7
bpf_trace_run8
cache_line_size
@@ -1196,6 +1209,7 @@
get_unused_fd_flags
idr_preload
idr_replace
+ ion_query_heaps_kernel
kill_pid
ksize
kthread_freezable_should_stop
@@ -1207,6 +1221,7 @@
of_modalias_node
on_each_cpu
prepare_to_wait
+ proc_remove
put_unused_fd
_raw_read_lock_bh
_raw_read_unlock_bh
@@ -1222,6 +1237,7 @@
strsep
sync_file_create
sync_file_get_fence
+ __task_pid_nr_ns
trace_print_symbols_seq
trace_set_clr_event
unmap_mapping_range
@@ -1993,6 +2009,7 @@
# required by usb_f_mtp.ko
usb_os_desc_prepare_interf_dir
usb_string_id
+ config_group_init_type_name
# required by usbserial.ko
device_del
@@ -2549,3 +2566,7 @@
kobject_init_and_add
sched_setscheduler_nocheck
strpbrk
+
+# required by sprd_wdf.ko
+ kstrtoull_from_user
+ smpboot_register_percpu_thread
diff --git a/arch/arm/configs/vendor/monaco.config b/arch/arm/configs/vendor/monaco.config
index 45f63ca..341800f 100644
--- a/arch/arm/configs/vendor/monaco.config
+++ b/arch/arm/configs/vendor/monaco.config
@@ -437,3 +437,4 @@
CONFIG_QFMT_V2=y
# CONFIG_QFMT_V1 is not set
CONFIG_MSM_ADSPRPC=y
+CONFIG_QSEECOM=y
diff --git a/arch/arm/configs/vendor/sdxlemur-debug.config b/arch/arm/configs/vendor/sdxlemur-debug.config
index de73a47..f2d80c5 100644
--- a/arch/arm/configs/vendor/sdxlemur-debug.config
+++ b/arch/arm/configs/vendor/sdxlemur-debug.config
@@ -23,6 +23,7 @@
CONFIG_IOMMU_TESTS=y
CONFIG_IOMMU_TLBSYNC_DEBUG=y
CONFIG_DEBUG_PANIC_ON_OOM=y
+CONFIG_QCOM_MEMORY_DUMP_V2=y
CONFIG_OF_RESERVED_MEM_CHECK=y
CONFIG_CORESIGHT_SOURCE_ETM3X=y
# CONFIG_CORESIGHT_CTI_SAVE_DISABLE is not set
@@ -37,3 +38,4 @@
CONFIG_BUG_ON_DATA_CORRUPTION=y
CONFIG_DEBUG_CREDENTIALS=y
CONFIG_QCOM_MEMORY_DUMP_V2=y
+CONFIG_LKDTM=m
diff --git a/arch/arm/configs/vendor/sdxlemur.config b/arch/arm/configs/vendor/sdxlemur.config
index 1e755dd..baabfd6 100644
--- a/arch/arm/configs/vendor/sdxlemur.config
+++ b/arch/arm/configs/vendor/sdxlemur.config
@@ -51,6 +51,7 @@
CONFIG_CNSS_QCA6490=y
CONFIG_CNSS_UTILS=y
CONFIG_CNSS_GENL=y
+CONFIG_QCOM_MEMORY_DUMP_V2=y
CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
diff --git a/arch/arm/configs/vendor/sdxnightjar-debug.config b/arch/arm/configs/vendor/sdxnightjar-debug.config
index e2ec558a..973db28 100644
--- a/arch/arm/configs/vendor/sdxnightjar-debug.config
+++ b/arch/arm/configs/vendor/sdxnightjar-debug.config
@@ -867,3 +867,5 @@
CONFIG_CORESIGHT_FUSE=y
CONFIG_RTC_DRV_PM8XXX=y
CONFIG_PWM_QTI_LPG=y
+CONFIG_QTI_TZ_LOG=y
+CONFIG_QSEECOM=y
diff --git a/arch/arm/configs/vendor/sdxnightjar.config b/arch/arm/configs/vendor/sdxnightjar.config
index b512d11..9cd1f2a 100644
--- a/arch/arm/configs/vendor/sdxnightjar.config
+++ b/arch/arm/configs/vendor/sdxnightjar.config
@@ -894,3 +894,7 @@
CONFIG_USB_GADGET_VBUS_DRAW=900
CONFIG_ENABLE_SFE=y
CONFIG_INPUT_QPNP_POWER_ON=y
+CONFIG_QTI_TZ_LOG=y
+CONFIG_QSEECOM=y
+CONFIG_SERIAL_MSM=y
+CONFIG_SERIAL_MSM_CONSOLE=y
diff --git a/arch/arm64/configs/vendor/gen3auto_GKI.config b/arch/arm64/configs/vendor/gen3auto_GKI.config
index f717ff1..b0b8d06 100644
--- a/arch/arm64/configs/vendor/gen3auto_GKI.config
+++ b/arch/arm64/configs/vendor/gen3auto_GKI.config
@@ -128,3 +128,4 @@
CONFIG_MSM_ADSPRPC=m
CONFIG_MSM_CDSP_LOADER=m
CONFIG_QCOM_SOCINFO=m
+CONFIG_MSM_BOOT_STATS=m
diff --git a/arch/arm64/configs/vendor/gen3auto_QGKI.config b/arch/arm64/configs/vendor/gen3auto_QGKI.config
index 5c03a7f..d9ef494 100644
--- a/arch/arm64/configs/vendor/gen3auto_QGKI.config
+++ b/arch/arm64/configs/vendor/gen3auto_QGKI.config
@@ -60,3 +60,4 @@
CONFIG_ADSPRPC_QGKI=y
CONFIG_QCOM_APCS_IPC=y
CONFIG_BLK_DEV_LOOP_MIN_COUNT=16
+CONFIG_MSM_BOOT_TIME_MARKER=y
diff --git a/arch/arm64/configs/vendor/quinvmauto_GKI.config b/arch/arm64/configs/vendor/quinvmauto_GKI.config
index 6500ceb..c09a0b1 100644
--- a/arch/arm64/configs/vendor/quinvmauto_GKI.config
+++ b/arch/arm64/configs/vendor/quinvmauto_GKI.config
@@ -44,3 +44,5 @@
CONFIG_PCI_MSM=m
CONFIG_QCOM_PDC=m
CONFIG_VIRTIO_I2C=m
+CONFIG_IPA3=m
+CONFIG_IPA_WDI_UNIFIED_API=y
diff --git a/arch/arm64/configs/vendor/quinvmauto_QGKI.config b/arch/arm64/configs/vendor/quinvmauto_QGKI.config
index a9a07e1..64c6568 100644
--- a/arch/arm64/configs/vendor/quinvmauto_QGKI.config
+++ b/arch/arm64/configs/vendor/quinvmauto_QGKI.config
@@ -28,3 +28,6 @@
CONFIG_IPC_LOGGING=y
CONFIG_MSM_HAB=y
CONFIG_RENAME_BLOCK_DEVICE=y
+CONFIG_DM_INIT=y
+CONFIG_BUILD_ARM64_UNCOMPRESSED_KERNEL=y
+# CONFIG_BUILD_ARM64_KERNEL_COMPRESSION_GZIP is not set
diff --git a/arch/arm64/configs/vendor/sdmsteppeauto_GKI.config b/arch/arm64/configs/vendor/sdmsteppeauto_GKI.config
index 99f5f77..26d7edf 100644
--- a/arch/arm64/configs/vendor/sdmsteppeauto_GKI.config
+++ b/arch/arm64/configs/vendor/sdmsteppeauto_GKI.config
@@ -84,3 +84,8 @@
CONFIG_QCOM_SCM=m
CONFIG_QCOM_RPMHPD=m
CONFIG_QCOM_DEVFREQ_ICC=m
+CONFIG_QCOM_LLCC=m
+CONFIG_QCOM_SM6150_LLCC=m
+CONFIG_MSM_SERVICE_LOCATOR=m
+CONFIG_MSM_SERVICE_NOTIFIER=m
+CONFIG_MSM_CORE_HANG_DETECT=m
diff --git a/arch/arm64/configs/vendor/sdmsteppeauto_QGKI.config b/arch/arm64/configs/vendor/sdmsteppeauto_QGKI.config
index 0e41f54..fd1ba51 100644
--- a/arch/arm64/configs/vendor/sdmsteppeauto_QGKI.config
+++ b/arch/arm64/configs/vendor/sdmsteppeauto_QGKI.config
@@ -33,3 +33,11 @@
CONFIG_QCOM_MINIDUMP=y
CONFIG_CPU_FREQ_GOV_USERSPACE=y
CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_QCOM_BIMC_BWMON=y
+CONFIG_ARM_MEMLAT_MON=y
+CONFIG_DEVFREQ_GOV_QCOM_BW_HWMON=y
+CONFIG_DEVFREQ_GOV_QCOM_CACHE_HWMON=y
+CONFIG_DEVFREQ_GOV_MEMLAT=y
+CONFIG_QCOM_DEVFREQ_ICC=y
+CONFIG_ARM_DSU_PMU=y
+CONFIG_QCOM_LLCC_PMU=y
diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 19128d9..e09faf0 100644
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -1015,7 +1015,10 @@ static int armv8pmu_probe_pmu(struct arm_pmu *cpu_pmu)
return probe.present ? 0 : -ENODEV;
}
-static int armv8_pmu_init(struct arm_pmu *cpu_pmu)
+static int armv8_pmu_init(struct arm_pmu *cpu_pmu, char *name,
+ int (*map_event)(struct perf_event *event),
+ const struct attribute_group *events,
+ const struct attribute_group *format)
{
int ret = armv8pmu_probe_pmu(cpu_pmu);
if (ret)
@@ -1034,144 +1037,127 @@ static int armv8_pmu_init(struct arm_pmu *cpu_pmu)
cpu_pmu->set_event_filter = armv8pmu_set_event_filter;
cpu_pmu->filter_match = armv8pmu_filter_match;
+ cpu_pmu->name = name;
+ cpu_pmu->map_event = map_event;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = events ?
+ events : &armv8_pmuv3_events_attr_group;
+ cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = format ?
+ format : &armv8_pmuv3_format_attr_group;
+
return 0;
}
static int armv8_pmuv3_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
+ return armv8_pmu_init(cpu_pmu, "armv8_pmuv3",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
- cpu_pmu->name = "armv8_pmuv3";
- cpu_pmu->map_event = armv8_pmuv3_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+static int armv8_a34_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a34",
+ armv8_pmuv3_map_event, NULL, NULL);
}
static int armv8_a35_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_cortex_a35";
- cpu_pmu->map_event = armv8_a53_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a35",
+ armv8_a53_map_event, NULL, NULL);
}
static int armv8_a53_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a53",
+ armv8_a53_map_event, NULL, NULL);
+}
- cpu_pmu->name = "armv8_cortex_a53";
- cpu_pmu->map_event = armv8_a53_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+static int armv8_a55_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a55",
+ armv8_pmuv3_map_event, NULL, NULL);
}
static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a57",
+ armv8_a57_map_event, NULL, NULL);
+}
- cpu_pmu->name = "armv8_cortex_a57";
- cpu_pmu->map_event = armv8_a57_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+static int armv8_a65_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a65",
+ armv8_pmuv3_map_event, NULL, NULL);
}
static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_cortex_a72";
- cpu_pmu->map_event = armv8_a57_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a72",
+ armv8_a57_map_event, NULL, NULL);
}
static int armv8_a73_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a73",
+ armv8_a73_map_event, NULL, NULL);
+}
- cpu_pmu->name = "armv8_cortex_a73";
- cpu_pmu->map_event = armv8_a73_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
+static int armv8_a75_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a75",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
- return 0;
+static int armv8_a76_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a76",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
+
+static int armv8_a77_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_cortex_a77",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
+
+static int armv8_e1_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_neoverse_e1",
+ armv8_pmuv3_map_event, NULL, NULL);
+}
+
+static int armv8_n1_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ return armv8_pmu_init(cpu_pmu, "armv8_neoverse_n1",
+ armv8_pmuv3_map_event, NULL, NULL);
}
static int armv8_thunder_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_cavium_thunder";
- cpu_pmu->map_event = armv8_thunder_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_cavium_thunder",
+ armv8_thunder_map_event, NULL, NULL);
}
static int armv8_vulcan_pmu_init(struct arm_pmu *cpu_pmu)
{
- int ret = armv8_pmu_init(cpu_pmu);
- if (ret)
- return ret;
-
- cpu_pmu->name = "armv8_brcm_vulcan";
- cpu_pmu->map_event = armv8_vulcan_map_event;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] =
- &armv8_pmuv3_events_attr_group;
- cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] =
- &armv8_pmuv3_format_attr_group;
-
- return 0;
+ return armv8_pmu_init(cpu_pmu, "armv8_brcm_vulcan",
+ armv8_vulcan_map_event, NULL, NULL);
}
static const struct of_device_id armv8_pmu_of_device_ids[] = {
{.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init},
+ {.compatible = "arm,cortex-a34-pmu", .data = armv8_a34_pmu_init},
{.compatible = "arm,cortex-a35-pmu", .data = armv8_a35_pmu_init},
{.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init},
+ {.compatible = "arm,cortex-a55-pmu", .data = armv8_a55_pmu_init},
{.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init},
+ {.compatible = "arm,cortex-a65-pmu", .data = armv8_a65_pmu_init},
{.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init},
{.compatible = "arm,cortex-a73-pmu", .data = armv8_a73_pmu_init},
+ {.compatible = "arm,cortex-a75-pmu", .data = armv8_a75_pmu_init},
+ {.compatible = "arm,cortex-a76-pmu", .data = armv8_a76_pmu_init},
+ {.compatible = "arm,cortex-a77-pmu", .data = armv8_a77_pmu_init},
+ {.compatible = "arm,neoverse-e1-pmu", .data = armv8_e1_pmu_init},
+ {.compatible = "arm,neoverse-n1-pmu", .data = armv8_n1_pmu_init},
{.compatible = "cavium,thunder-pmu", .data = armv8_thunder_pmu_init},
{.compatible = "brcm,vulcan-pmu", .data = armv8_vulcan_pmu_init},
{},
diff --git a/drivers/android/vendor_hooks.c b/drivers/android/vendor_hooks.c
index d95612b..6686dbc 100644
--- a/drivers/android/vendor_hooks.c
+++ b/drivers/android/vendor_hooks.c
@@ -67,3 +67,5 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_show_regs);
EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_wq_lockup_pool);
EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_sysrq_crash);
EXPORT_TRACEPOINT_SYMBOL_GPL(android_rvh_find_busiest_group);
+EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_map_util_freq);
+EXPORT_TRACEPOINT_SYMBOL_GPL(android_vh_em_pd_energy);
diff --git a/drivers/cpufreq/qcom-cpufreq-hw-debug.c b/drivers/cpufreq/qcom-cpufreq-hw-debug.c
index 73698a6..7aa1266 100644
--- a/drivers/cpufreq/qcom-cpufreq-hw-debug.c
+++ b/drivers/cpufreq/qcom-cpufreq-hw-debug.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#define pr_fmt(fmt) "cpufreq_hw_debug: %s: " fmt, __func__
@@ -17,6 +17,8 @@ enum debug_hw_regs_data {
REG_PERF_STATE,
REG_CYCLE_CNTR,
REG_PSTATE_STATUS,
+ REG_EPSS_DEBUG_STATUS,
+ REG_EPSS_DEBUG_SRB,
REG_ARRAY_SIZE,
};
@@ -35,32 +37,39 @@ struct cpufreq_register_data {
static struct cpufreq_hwregs *hw_regs;
static const u16 *offsets;
-static const u16 cpufreq_qcom_std_data[REG_ARRAY_SIZE] = {
+static const u16 cpufreq_qcom_std_data[] = {
[REG_PERF_STATE] = 0x920,
[REG_CYCLE_CNTR] = 0x9c0,
[REG_PSTATE_STATUS] = 0x700,
};
-static const u16 cpufreq_qcom_std_epss_data[REG_ARRAY_SIZE] = {
+static const u16 cpufreq_qcom_std_epss_data[] = {
[REG_PERF_STATE] = 0x320,
[REG_CYCLE_CNTR] = 0x3c4,
[REG_PSTATE_STATUS] = 0x020,
+ [REG_EPSS_DEBUG_STATUS] = 0x01c,
+ [REG_EPSS_DEBUG_SRB] = 0x0bc,
};
static int print_cpufreq_hw_debug_regs(struct seq_file *s, void *unused)
{
- int i, j;
+ int i, j, size = ARRAY_SIZE(cpufreq_qcom_std_data);
u32 regval;
static struct cpufreq_register_data data[] = {
{"PERF_STATE_DESIRED", REG_PERF_STATE},
{"CYCLE_CNTR_VAL", REG_CYCLE_CNTR},
{"PSTATE_STATUS", REG_PSTATE_STATUS},
+ {"EPSS_DEBUG_STATUS", REG_EPSS_DEBUG_STATUS},
+ {"EPSS_DEBUG_SRB", REG_EPSS_DEBUG_SRB},
};
+ if (offsets == cpufreq_qcom_std_epss_data)
+ size = ARRAY_SIZE(cpufreq_qcom_std_epss_data);
+
for (i = 0; i < hw_regs->domain_cnt; i++) {
seq_printf(s, "FREQUENCY DOMAIN %d\n", i);
- for (j = 0; j < ARRAY_SIZE(data); j++) {
+ for (j = 0; j < size; j++) {
regval = readl_relaxed(hw_regs->base[i] +
offsets[data[j].offset]);
seq_printf(s, "%25s: 0x%.8x\n", data[j].name, regval);
@@ -85,18 +94,23 @@ static const struct file_operations cpufreq_debug_register_fops = {
static int cpufreq_panic_callback(struct notifier_block *nfb,
unsigned long event, void *unused)
{
- int i, j;
+ int i, j, size = ARRAY_SIZE(cpufreq_qcom_std_data);
u32 regval;
static struct cpufreq_register_data data[] = {
{"PERF_STATE_DESIRED", REG_PERF_STATE},
{"CYCLE_CNTR_VAL", REG_CYCLE_CNTR},
{"PSTATE_STATUS", REG_PSTATE_STATUS},
+ {"EPSS_DEBUG_STATUS", REG_EPSS_DEBUG_STATUS},
+ {"EPSS_DEBUG_SRB", REG_EPSS_DEBUG_SRB},
};
+ if (offsets == cpufreq_qcom_std_epss_data)
+ size = ARRAY_SIZE(cpufreq_qcom_std_epss_data);
+
for (i = 0; i < hw_regs->domain_cnt; i++) {
pr_err("FREQUENCY DOMAIN %d\n", i);
- for (j = 0; j < ARRAY_SIZE(data); j++) {
+ for (j = 0; j < size; j++) {
regval = readl_relaxed(hw_regs->base[i] +
offsets[data[j].offset]);
pr_err("%25s: 0x%.8x\n", data[j].name, regval);
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index cfe983d..7ab51b0 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -267,6 +267,16 @@
Qualcomm Technologies, Inc. "Secure Channel Manager"
interface.
+config QCOM_SCM_QCPE
+ bool "Para-Virtualized Secure Channel Manager (SCM) support over QCPE"
+ depends on QCOM_SCM
+ default n
+ help
+ To enable Secure Channel Mananger(SCM) support for SoC
+ in virtualized Linux, where SCM backend is QCPE (QCOM Protected
+ environment). The SCM channel will use QCOM HAB interface for
+ front-end to back-end communication.
+
config QTEE_SHM_BRIDGE
bool "QTI TEE shared memory bridge"
depends on QCOM_SCM
diff --git a/drivers/firmware/qcom_scm-smc.c b/drivers/firmware/qcom_scm-smc.c
index 3d736c7..c4253f2 100644
--- a/drivers/firmware/qcom_scm-smc.c
+++ b/drivers/firmware/qcom_scm-smc.c
@@ -22,6 +22,8 @@
#define CREATE_TRACE_POINTS
#include <trace/events/scm.h>
+#include <linux/habmm.h>
+
#define MAX_QCOM_SCM_ARGS 10
#define MAX_QCOM_SCM_RETS 3
@@ -168,19 +170,251 @@ static struct qcom_scm_entry qcom_scm_wb[] = {
{ .flag = QCOM_SCM_FLAG_WARMBOOT_CPU3 },
};
-static void __qcom_scm_call_do_quirk(const struct arm_smccc_args *smc,
- struct arm_smccc_res *res)
+
+#if IS_ENABLED(CONFIG_QCOM_SCM_QCPE)
+
+#ifdef CONFIG_GHS_VMM
+struct scm_extra_arg {
+ union {
+ u32 args32[N_EXT_SCM_ARGS];
+ u64 args64[N_EXT_SCM_ARGS];
+ };
+};
+#endif
+
+struct smc_params_s {
+ uint64_t fn_id;
+ uint64_t arginfo;
+ uint64_t args[MAX_SCM_ARGS];
+} __packed;
+
+static u32 handle;
+static bool opened;
+
+static int scm_qcpe_hab_open(void)
{
- unsigned long a0 = smc->a[0];
+ int ret;
+
+ if (!opened) {
+ ret = habmm_socket_open(&handle, MM_QCPE_VM1, 0, 0);
+ if (ret) {
+ pr_err("habmm_socket_open failed with ret = %d\n", ret);
+ return ret;
+ }
+ opened = true;
+ }
+
+ return 0;
+}
+
+static void scm_qcpe_hab_close(void)
+{
+ if (opened) {
+ habmm_socket_close(handle);
+ opened = false;
+ handle = 0;
+ }
+}
+
+/* Send SMC over HAB, receive the response. Both operations are blocking. */
+/* This is meant to be called from non-atomic context. */
+static int scm_qcpe_hab_send_receive(struct smc_params_s *smc_params,
+ u32 *size_bytes)
+{
+ int ret;
+
+ ret = habmm_socket_send(handle, smc_params, sizeof(*smc_params), 0);
+ if (ret) {
+ pr_err("habmm_socket_send failed, ret= 0x%x\n", ret);
+ return ret;
+ }
+
+ memset(smc_params, 0x0, sizeof(*smc_params));
+
+ do {
+ *size_bytes = sizeof(*smc_params);
+ ret = habmm_socket_recv(handle, smc_params, size_bytes, 0,
+ HABMM_SOCKET_RECV_FLAGS_UNINTERRUPTIBLE);
+ } while (-EINTR == ret);
+
+ if (ret) {
+ pr_err("habmm_socket_recv failed, ret= 0x%x\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+/* Send SMC over HAB, receive the response, in non-blocking mode. */
+/* This is meant to be called from atomic context. */
+static int scm_qcpe_hab_send_receive_atomic(struct smc_params_s *smc_params,
+ u32 *size_bytes)
+{
+ int ret;
+ unsigned long delay;
+
+ delay = jiffies + (HZ); /* 1 second delay for send */
+
+ do {
+ ret = habmm_socket_send(handle,
+ smc_params, sizeof(*smc_params),
+ HABMM_SOCKET_SEND_FLAGS_NON_BLOCKING);
+ } while ((-EAGAIN == ret) && time_before(jiffies, delay));
+
+ if (ret) {
+ pr_err("HAB send failed, non-blocking, ret= 0x%x\n", ret);
+ return ret;
+ }
+
+ memset(smc_params, 0x0, sizeof(*smc_params));
+
+ delay = jiffies + (HZ); /* 1 second delay for receive */
+
+ do {
+ *size_bytes = sizeof(*smc_params);
+ ret = habmm_socket_recv(handle, smc_params, size_bytes, 0,
+ HABMM_SOCKET_RECV_FLAGS_NON_BLOCKING);
+ } while ((-EAGAIN == ret) && time_before(jiffies, delay) &&
+ (*size_bytes == 0));
+
+ if (ret) {
+ pr_err("HAB recv failed, non-blocking, ret= 0x%x\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+
+static int scm_call_qcpe(const struct arm_smccc_args *smc,
+ struct arm_smccc_res *res, const bool atomic)
+{
+ u32 size_bytes;
+ struct smc_params_s smc_params = {0,};
+ int ret;
+#ifdef CONFIG_GHS_VMM
+ int i;
+ uint64_t arglen = smc->a[1] & 0xf;
+ struct ion_handle *ihandle = NULL;
+#endif
+
+ pr_info("SCM IN [QCPE]: 0x%x, 0x%x, 0x%llx, 0x%llx, 0x%llx, 0x%llx, 0x%llx\n",
+ smc->a[0], smc->a[1], smc->a[2], smc->a[3], smc->a[4], smc->a[5],
+ smc->a[5]);
+
+ if (!opened) {
+ if (!atomic) {
+ if (scm_qcpe_hab_open()) {
+ pr_err("HAB channel re-open failed\n");
+ return -ENODEV;
+ }
+ } else {
+ pr_err("HAB channel is not opened\n");
+ return -ENODEV;
+ }
+ }
+
+ smc_params.fn_id = smc->a[0];
+ smc_params.arginfo = smc->a[1];
+ smc_params.args[0] = smc->a[2];
+ smc_params.args[1] = smc->a[3];
+ smc_params.args[2] = smc->a[4];
+
+#ifdef CONFIG_GHS_VMM
+ if (arglen <= N_REGISTER_ARGS) {
+ smc_params.args[FIRST_EXT_ARG_IDX] = smc->a[5];
+ } else {
+ struct scm_extra_arg *argbuf =
+ (struct scm_extra_arg *)desc->extra_arg_buf;
+ int j = 0;
+
+ if (scm_version == SMC_CONVENTION_ARM_64)
+ for (i = FIRST_EXT_ARG_IDX; i < MAX_QCOM_SCM_ARGS; i++)
+ smc_params.args[i] = argbuf->args64[j++];
+ else
+ for (i = FIRST_EXT_ARG_IDX; i < MAX_QCOM_SCM_ARGS; i++)
+ smc_params.args[i] = argbuf->args32[j++];
+ }
+
+ ret = ionize_buffers(smc->a[0] & (~SMC64_MASK), &smc_params, &ihandle);
+ if (ret)
+ return ret;
+#else
+ smc_params.args[3] = smc->a[5];
+ smc_params.args[4] = 0;
+#endif
+
+ if (!atomic) {
+ ret = scm_qcpe_hab_send_receive(&smc_params, &size_bytes);
+ if (ret) {
+ pr_err("send/receive failed, non-atomic, ret= 0x%x\n",
+ ret);
+ goto err_ret;
+ }
+ } else {
+ ret = scm_qcpe_hab_send_receive_atomic(&smc_params,
+ &size_bytes);
+ if (ret) {
+ pr_err("send/receive failed, ret= 0x%x\n", ret);
+ goto err_ret;
+ }
+ }
+
+ if (size_bytes != sizeof(smc_params)) {
+ pr_err("habmm_socket_recv expected size: %lu, actual=%u\n",
+ sizeof(smc_params),
+ size_bytes);
+ ret = QCOM_SCM_ERROR;
+ goto err_ret;
+ }
+
+ res->a1 = smc_params.args[1];
+ res->a2 = smc_params.args[2];
+ res->a3 = smc_params.args[3];
+ res->a0 = smc_params.args[0];
+ pr_info("SCM OUT [QCPE]: 0x%llx, 0x%llx, 0x%llx, 0x%llx\n",
+ res->a0, res->a1, res->a2, res->a3);
+ goto no_err;
+
+err_ret:
+ if (!atomic) {
+ /* In case of an error, try to recover the hab connection
+ * for next time. This can only be done if called in
+ * non-atomic context.
+ */
+ scm_qcpe_hab_close();
+ if (scm_qcpe_hab_open())
+ pr_err("scm_qcpe_hab_open failed\n");
+ }
+
+no_err:
+#ifdef CONFIG_GHS_VMM
+ if (ihandle)
+ free_ion_buffers(ihandle);
+#endif
+ return res->a0;
+}
+
+#endif /* CONFIG_QCOM_SCM_QCPE */
+
+static void __qcom_scm_call_do_quirk(const struct arm_smccc_args *smc,
+ struct arm_smccc_res *res,
+ const bool atomic)
+{
ktime_t time;
const bool trace = trace_scm_call_enabled();
+#if !(IS_ENABLED(CONFIG_QCOM_SCM_QCPE))
+ unsigned long a0 = smc->a[0];
struct arm_smccc_quirk quirk = { .id = ARM_SMCCC_QUIRK_QCOM_A6 };
quirk.state.a6 = 0;
-
+#endif
if (trace)
time = ktime_get();
+#if IS_ENABLED(CONFIG_QCOM_SCM_QCPE)
+ scm_call_qcpe(smc, res, atomic);
+#else
do {
arm_smccc_smc_quirk(a0, smc->a[1], smc->a[2], smc->a[3],
smc->a[4], smc->a[5], quirk.state.a6,
@@ -190,7 +424,7 @@ static void __qcom_scm_call_do_quirk(const struct arm_smccc_args *smc,
a0 = res->a0;
} while (res->a0 == QCOM_SCM_INTERRUPTED);
-
+#endif
if (trace)
trace_scm_call(smc->a, res, ktime_us_delta(ktime_get(), time));
}
@@ -266,13 +500,13 @@ static int qcom_scm_call_smccc(struct device *dev,
}
if (atomic) {
- __qcom_scm_call_do_quirk(&smc, &res);
+ __qcom_scm_call_do_quirk(&smc, &res, true);
} else {
int retry_count = 0;
do {
mutex_lock(&qcom_scm_lock);
- __qcom_scm_call_do_quirk(&smc, &res);
+ __qcom_scm_call_do_quirk(&smc, &res, false);
mutex_unlock(&qcom_scm_lock);
if (res.a0 == QCOM_SCM_V2_EBUSY) {
@@ -2169,5 +2403,21 @@ int __init scm_mem_protection_init_do(struct device *dev)
void __qcom_scm_init(void)
{
+
+#if IS_ENABLED(CONFIG_QCOM_SCM_QCPE)
+/**
+ * The HAB connection should be opened before first SMC call.
+ * If not, there could be errors that might cause the
+ * system to crash.
+ */
+ scm_qcpe_hab_open();
+#endif
__query_convention();
}
+
+#if IS_ENABLED(CONFIG_QCOM_SCM_QCPE)
+void __qcom_scm_qcpe_exit(void)
+{
+ scm_qcpe_hab_close();
+}
+#endif
diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c
index 33b3c18..106cc160 100644
--- a/drivers/firmware/qcom_scm.c
+++ b/drivers/firmware/qcom_scm.c
@@ -1213,6 +1213,9 @@ early_initcall(scm_mem_protection_init);
#if IS_MODULE(CONFIG_QCOM_SCM)
static void __exit qcom_scm_exit(void)
{
+#if IS_ENABLED(CONFIG_QCOM_SCM_QCPE)
+ __qcom_scm_qcpe_exit();
+#endif
platform_driver_unregister(&qcom_scm_driver);
qtee_shmbridge_driver_exit();
}
diff --git a/drivers/iommu/arm-smmu.c b/drivers/iommu/arm-smmu.c
index 9e44524..1fa59c6 100644
--- a/drivers/iommu/arm-smmu.c
+++ b/drivers/iommu/arm-smmu.c
@@ -3023,7 +3023,6 @@ static int __bus_lookup_iommu_group(struct device *dev, void *priv)
}
data->group = group;
- iommu_group_put(group);
return 1;
}
@@ -3703,6 +3702,9 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev)
int i, idx;
group = of_get_device_group(dev);
+ if (group)
+ goto finish;
+
for_each_cfg_sme(fwspec, i, idx) {
if (group && smmu->s2crs[idx].group &&
group != smmu->s2crs[idx].group) {
@@ -3729,6 +3731,7 @@ static struct iommu_group *arm_smmu_device_group(struct device *dev)
return NULL;
}
+finish:
if (smmu->impl && smmu->impl->device_group &&
smmu->impl->device_group(dev, group)) {
iommu_group_put(group);
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 9544076..13b5809 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -3154,11 +3154,6 @@ void mmc_rescan(struct work_struct *work)
if (host->bus_ops && !host->bus_dead)
host->bus_ops->detect(host);
-#if defined(CONFIG_SDC_QTI)
- if (host->corrupted_card)
- return;
-#endif
-
host->detect_change = 0;
/*
@@ -3180,6 +3175,11 @@ void mmc_rescan(struct work_struct *work)
*/
mmc_bus_put(host);
+#if defined(CONFIG_SDC_QTI)
+ if (host->corrupted_card)
+ goto out;
+#endif
+
mmc_claim_host(host);
if (mmc_card_is_removable(host) && host->ops->get_cd &&
host->ops->get_cd(host) == 0) {
diff --git a/drivers/mtd/devices/msm_qpic_nand.c b/drivers/mtd/devices/msm_qpic_nand.c
index 80b20c9c..306e81e 100644
--- a/drivers/mtd/devices/msm_qpic_nand.c
+++ b/drivers/mtd/devices/msm_qpic_nand.c
@@ -1986,6 +1986,8 @@ static int msm_nand_read_pagescope(struct mtd_info *mtd, loff_t from,
while (rw_params.page_count-- > 0) {
+ uint32_t cw_desc_cnt = 1;
+ struct sps_command_element *curr_ce, *start_ce;
erased_page = false;
data.addr0 = (rw_params.page << 16) | rw_params.oob_col;
data.addr1 = (rw_params.page >> 16) & 0xff;
@@ -1998,6 +2000,15 @@ static int msm_nand_read_pagescope(struct mtd_info *mtd, loff_t from,
msm_nand_prep_read_cmd_desc_pagescope(ops, &rw_params,
&data, info,
cmd_list, 0);
+ start_ce = &cmd_list->cw_desc[cw_desc_cnt].ce[0];
+ curr_ce = start_ce;
+ cmd_list->cw_desc[cw_desc_cnt].flags = CMD | INT_UNLCK;
+ cmd_list->count++;
+ msm_nand_prep_ce(curr_ce, MSM_NAND_AUTO_STATUS_EN(info),
+ WRITE, flash_cmd);
+ curr_ce++;
+ cmd_list->cw_desc[cw_desc_cnt].num_ce = curr_ce - start_ce;
+
dma_buffer->xfer.iovec_count = cmd_list->count;
dma_buffer->xfer.iovec = dma_buffer->cmd_iovec;
dma_buffer->xfer.iovec_phys = msm_virt_to_dma(chip,
@@ -2092,31 +2103,7 @@ static int msm_nand_read_pagescope(struct mtd_info *mtd, loff_t from,
(info->sps.data_prod_stat.index), err);
goto put_dev;
}
- /*
- * There is a H/W BUG in qpic 2.0. You should unlock the command
- * pipe only after all the status descriptors are collected on
- * status descriptor pipe (pipe#3).
- */
- /* Unlock the command pipe now */
- msm_nand_prep_single_desc(sps_cmd,
- MSM_NAND_AUTO_STATUS_EN(info),
- WRITE, flash_cmd, INT_UNLCK);
- err = sps_transfer_one(info->sps.cmd_pipe.handle,
- msm_virt_to_dma(chip, &sps_cmd->ce),
- sizeof(struct sps_command_element),
- NULL, sps_cmd->flags);
- if (err) {
- pr_err("Failed to unlock cmd desc. pipe: %d\n", err);
- goto put_dev;
- }
- err = msm_nand_sps_get_iovec(info->sps.cmd_pipe.handle,
- info->sps.cmd_pipe.index, 1, &iovec_temp);
- if (err) {
- pr_err("Failed to get iovec for cmd desc. err:%d\n",
- err);
- goto put_dev;
- }
err = msm_nand_put_device(chip->dev);
mutex_unlock(&info->lock);
if (err)
@@ -4480,7 +4467,10 @@ static int msm_nand_probe(struct platform_device *pdev)
goto free_bam;
}
info->nand_chip.qpic_version = qpic_version.qpic_major;
- if (info->nand_chip.qpic_version >= 2) {
+ info->nand_chip.qpic_min_version = qpic_version.qpic_minor;
+ if (info->nand_chip.qpic_version >= 2 &&
+ info->nand_chip.qpic_min_version >= 1) {
+ info->nand_chip.caps = MSM_NAND_CAP_PAGE_SCOPE_READ;
mutex_lock(&info->lock);
err = msm_nand_get_device(info->nand_chip.dev);
if (err) {
diff --git a/drivers/mtd/devices/msm_qpic_nand.h b/drivers/mtd/devices/msm_qpic_nand.h
index 06ff227..cc1df16 100644
--- a/drivers/mtd/devices/msm_qpic_nand.h
+++ b/drivers/mtd/devices/msm_qpic_nand.h
@@ -270,7 +270,8 @@ struct msm_nand_chip {
uint32_t ecc_buf_cfg;
uint32_t ecc_bch_cfg;
uint32_t ecc_cfg_raw;
- uint32_t qpic_version; /* To store the qpic controller version */
+ uint32_t qpic_version; /* To store the qpic controller major version */
+ uint16_t qpic_min_version; /* To store the qpic controller minor version */
uint32_t caps; /* General host capabilities */
#define MSM_NAND_CAP_PAGE_SCOPE_READ BIT(0)
#define MSM_NAND_CAP_MULTI_PAGE_READ BIT(1)
diff --git a/drivers/net/wireless/cnss2/pci.c b/drivers/net/wireless/cnss2/pci.c
index b513eb6..cdd18f7 100644
--- a/drivers/net/wireless/cnss2/pci.c
+++ b/drivers/net/wireless/cnss2/pci.c
@@ -1258,6 +1258,21 @@ int cnss_pci_link_down(struct device *dev)
}
EXPORT_SYMBOL(cnss_pci_link_down);
+int cnss_pci_get_reg_dump(struct device *dev, uint8_t *buffer, uint32_t len)
+{
+ struct pci_dev *pci_dev = to_pci_dev(dev);
+
+ if (!pci_dev) {
+ cnss_pr_err("pci_dev is NULL\n");
+ return -EINVAL;
+ }
+
+ cnss_pr_dbg("Get pci reg dump for hang data\n");
+
+ return msm_pcie_reg_dump(pci_dev, buffer, len);
+}
+EXPORT_SYMBOL(cnss_pci_get_reg_dump);
+
int cnss_pcie_is_device_down(struct cnss_pci_data *pci_priv)
{
struct cnss_plat_data *plat_priv;
diff --git a/drivers/pci/controller/pci-msm.c b/drivers/pci/controller/pci-msm.c
index 5308b0c..afb2c38 100644
--- a/drivers/pci/controller/pci-msm.c
+++ b/drivers/pci/controller/pci-msm.c
@@ -874,10 +874,6 @@ static u32 corr_counter_limit = 5;
/* CRC8 table for BDF to SID translation */
static u8 msm_pcie_crc8_table[CRC8_TABLE_SIZE];
-/* Table to track info of PCIe devices */
-static struct msm_pcie_device_info
- msm_pcie_dev_tbl[MAX_RC_NUM * MAX_DEVICE_NUM];
-
/* PCIe driver state */
static struct pcie_drv_sta {
u32 rc_num;
@@ -2933,20 +2929,13 @@ static void msm_pcie_save_shadow(struct msm_pcie_dev_t *dev,
u32 word_offset, u32 wr_val,
u32 bdf, bool rc)
{
- int i, j;
- u32 max_dev = MAX_RC_NUM * MAX_DEVICE_NUM;
+ int i;
if (rc) {
dev->rc_shadow[word_offset / 4] = wr_val;
} else {
for (i = 0; i < MAX_DEVICE_NUM; i++) {
if (!dev->pcidev_table[i].bdf) {
- for (j = 0; j < max_dev; j++) {
- if (!msm_pcie_dev_tbl[j].bdf) {
- msm_pcie_dev_tbl[j].bdf = bdf;
- break;
- }
- }
dev->pcidev_table[i].bdf = bdf;
if ((!dev->bridge_found) && (i > 0))
dev->bridge_found = true;
@@ -4617,27 +4606,18 @@ static void msm_pcie_config_ep_aer(struct msm_pcie_dev_t *dev,
readl_relaxed(ep_base + ep_dev_info->dev_ctrlstts_offset));
}
-static int msm_pcie_config_device_table(struct device *dev, void *pdev)
+static int msm_pcie_config_device_table(struct pci_dev *pcidev, void *pdev)
{
- struct pci_dev *pcidev = to_pci_dev(dev);
struct msm_pcie_dev_t *pcie_dev = (struct msm_pcie_dev_t *) pdev;
- struct msm_pcie_device_info *dev_table_t = pcie_dev->pcidev_table;
struct resource *axi_conf = pcie_dev->res[MSM_PCIE_RES_CONF].resource;
int ret = 0;
u32 rc_idx = pcie_dev->rc_idx;
- u32 i, index;
+ u32 i;
u32 bdf = 0;
u8 type;
u32 h_type;
u32 bme;
- if (!pcidev) {
- PCIE_ERR(pcie_dev,
- "PCIe: Did not find PCI device in list for RC%d.\n",
- pcie_dev->rc_idx);
- return -ENODEV;
- }
-
PCIE_DBG(pcie_dev,
"PCI device found: vendor-id:0x%x device-id:0x%x\n",
pcidev->vendor, pcidev->device);
@@ -4649,81 +4629,51 @@ static int msm_pcie_config_device_table(struct device *dev, void *pdev)
type = pcidev->bus->number == 1 ?
PCIE20_CTRL1_TYPE_CFG0 : PCIE20_CTRL1_TYPE_CFG1;
- for (i = 0; i < (MAX_RC_NUM * MAX_DEVICE_NUM); i++) {
- if (msm_pcie_dev_tbl[i].bdf == bdf &&
- !msm_pcie_dev_tbl[i].dev) {
- for (index = 0; index < MAX_DEVICE_NUM; index++) {
- if (dev_table_t[index].bdf == bdf) {
- msm_pcie_dev_tbl[i].dev = pcidev;
- msm_pcie_dev_tbl[i].domain = rc_idx;
- msm_pcie_dev_tbl[i].conf_base =
- pcie_dev->conf + index * SZ_4K;
- msm_pcie_dev_tbl[i].phy_address =
- axi_conf->start + index * SZ_4K;
+ for (i = 0; i < MAX_DEVICE_NUM; i++) {
+ struct msm_pcie_device_info *dev_table_t =
+ &pcie_dev->pcidev_table[i];
- dev_table_t[index].dev = pcidev;
- dev_table_t[index].domain = rc_idx;
- dev_table_t[index].conf_base =
- pcie_dev->conf + index * SZ_4K;
- dev_table_t[index].phy_address =
- axi_conf->start + index * SZ_4K;
+ if (dev_table_t->bdf != bdf)
+ continue;
- msm_pcie_iatu_config(pcie_dev, index,
- type,
- dev_table_t[index].phy_address,
- dev_table_t[index].phy_address
- + SZ_4K - 1,
- bdf);
+ dev_table_t->dev = pcidev;
+ dev_table_t->domain = rc_idx;
+ dev_table_t->conf_base = pcie_dev->conf + i * SZ_4K;
+ dev_table_t->phy_address = axi_conf->start + i * SZ_4K;
- h_type = readl_relaxed(
- dev_table_t[index].conf_base +
- PCIE20_HEADER_TYPE);
+ msm_pcie_iatu_config(pcie_dev, i, type,
+ dev_table_t->phy_address,
+ dev_table_t->phy_address + SZ_4K - 1, bdf);
- bme = readl_relaxed(
- dev_table_t[index].conf_base +
- PCIE20_COMMAND_STATUS);
+ h_type = readl_relaxed(dev_table_t->conf_base +
+ PCIE20_HEADER_TYPE);
- if (h_type & (1 << 16)) {
- pci_write_config_dword(pcidev,
- PCIE20_COMMAND_STATUS,
- bme | 0x06);
- } else {
- pcie_dev->num_ep++;
- dev_table_t[index].registered =
- false;
- }
+ bme = readl_relaxed(dev_table_t->conf_base +
+ PCIE20_COMMAND_STATUS);
- if (pcie_dev->num_ep > 1)
- pcie_dev->pending_ep_reg = true;
-
- if (pcie_dev->aer_enable)
- msm_pcie_config_ep_aer(pcie_dev,
- &dev_table_t[index]);
-
- break;
- }
- }
- if (index == MAX_DEVICE_NUM) {
- PCIE_ERR(pcie_dev,
- "RC%d PCI device table is full.\n",
- rc_idx);
- ret = index;
- } else {
- break;
- }
- } else if (msm_pcie_dev_tbl[i].bdf == bdf &&
- pcidev == msm_pcie_dev_tbl[i].dev) {
- break;
+ if (h_type & (1 << 16)) {
+ pci_write_config_dword(pcidev, PCIE20_COMMAND_STATUS,
+ bme | 0x06);
+ } else {
+ pcie_dev->num_ep++;
+ dev_table_t->registered = false;
}
+
+ if (pcie_dev->num_ep > 1)
+ pcie_dev->pending_ep_reg = true;
+
+ if (pcie_dev->aer_enable)
+ msm_pcie_config_ep_aer(pcie_dev, dev_table_t);
+
+ break;
}
- if (i == MAX_RC_NUM * MAX_DEVICE_NUM) {
+
+ if (i == MAX_DEVICE_NUM) {
PCIE_ERR(pcie_dev,
- "Global PCI device table is full: %d elements.\n",
- i);
- PCIE_ERR(pcie_dev,
- "Bus number is 0x%x\nDevice number is 0x%x\n",
- pcidev->bus->number, pcidev->devfn);
- ret = i;
+ "PCIe: RC%d: could not find device in the table: %02x:%02x:%01x\n",
+ pcie_dev->rc_idx, pcidev->bus->number,
+ PCI_SLOT(pcidev->devfn), PCI_FUNC(pcidev->devfn));
+ ret = -ENODEV;
}
return ret;
}
@@ -4803,7 +4753,7 @@ static void msm_pcie_config_sid(struct msm_pcie_dev_t *dev)
int msm_pcie_enumerate(u32 rc_idx)
{
- int ret = 0, bus_ret = 0;
+ int ret = 0;
struct msm_pcie_dev_t *dev = &msm_pcie_dev[rc_idx];
struct pci_dev *pcidev = NULL;
struct pci_host_bridge *bridge;
@@ -4925,14 +4875,7 @@ int msm_pcie_enumerate(u32 rc_idx)
goto out;
}
- bus_ret = bus_for_each_dev(&pci_bus_type, NULL, dev,
- &msm_pcie_config_device_table);
- if (bus_ret) {
- PCIE_ERR(dev, "PCIe: RC%d: Failed to set up device table\n",
- dev->rc_idx);
- ret = -ENODEV;
- goto out;
- }
+ pci_walk_bus(dev->dev->bus, msm_pcie_config_device_table, dev);
msm_pcie_check_l1ss_support_all(dev);
msm_pcie_config_link_pm(dev, true);
@@ -7010,18 +6953,6 @@ static int __init pcie_init(void)
INIT_WORK(&msm_pcie_dev[i].drv_enable_pc_work,
msm_pcie_drv_enable_pc);
}
- for (i = 0; i < MAX_RC_NUM * MAX_DEVICE_NUM; i++) {
- msm_pcie_dev_tbl[i].bdf = 0;
- msm_pcie_dev_tbl[i].dev = NULL;
- msm_pcie_dev_tbl[i].short_bdf = 0;
- msm_pcie_dev_tbl[i].sid = 0;
- msm_pcie_dev_tbl[i].domain = -1;
- msm_pcie_dev_tbl[i].conf_base = NULL;
- msm_pcie_dev_tbl[i].phy_address = 0;
- msm_pcie_dev_tbl[i].dev_ctrlstts_offset = 0;
- msm_pcie_dev_tbl[i].event_reg = NULL;
- msm_pcie_dev_tbl[i].registered = true;
- }
crc8_populate_msb(msm_pcie_crc8_table, MSM_PCIE_CRC8_POLYNOMIAL);
diff --git a/drivers/pci/switch/switch-qcom.c b/drivers/pci/switch/switch-qcom.c
index 99412c3..fce2d25 100644
--- a/drivers/pci/switch/switch-qcom.c
+++ b/drivers/pci/switch/switch-qcom.c
@@ -42,7 +42,7 @@ static int config_port_arbitration(struct device *dev, int parb_select,
struct pci_dev *pcidev = to_pci_dev(dev);
int i, pos, size;
int timeout = 100;
- u32 parb_offset, parb_phase, parb_size;
+ u32 parb_offset, parb_phase = 0, parb_size;
u32 val;
u16 status;
diff --git a/drivers/pinctrl/qcom/pinctrl-monaco.c b/drivers/pinctrl/qcom/pinctrl-monaco.c
index c4654ba..1260c7c 100644
--- a/drivers/pinctrl/qcom/pinctrl-monaco.c
+++ b/drivers/pinctrl/qcom/pinctrl-monaco.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/module.h>
@@ -119,8 +119,8 @@
}
-#define QUP_I3C_5_MODE_OFFSET 0x85000
-#define QUP_I3C_6_MODE_OFFSET 0x86000
+#define QUP_I3C_5_MODE_OFFSET 0x86000
+#define QUP_I3C_6_MODE_OFFSET 0x87000
static const struct pinctrl_pin_desc monaco_pins[] = {
PINCTRL_PIN(0, "GPIO_0"),
@@ -360,9 +360,6 @@ static const unsigned int sdc1_rclk_pins[] = { 112 };
static const unsigned int sdc1_clk_pins[] = { 113 };
static const unsigned int sdc1_cmd_pins[] = { 114 };
static const unsigned int sdc1_data_pins[] = { 115 };
-static const unsigned int sdc2_clk_pins[] = { 116 };
-static const unsigned int sdc2_cmd_pins[] = { 117 };
-static const unsigned int sdc2_data_pins[] = { 118 };
enum monaco_functions {
msm_mux_gpio,
@@ -381,7 +378,6 @@ enum monaco_functions {
msm_mux_GP_PDM1,
msm_mux_GP_PDM2,
msm_mux_JITTER_BIST,
- msm_mux_NAV_GPIO,
msm_mux_PA_INDICATOR,
msm_mux_PLL_BIST,
msm_mux_QUP0_L0,
@@ -453,6 +449,9 @@ enum monaco_functions {
msm_mux_m_voc,
msm_mux_mdp_vsync,
msm_mux_mpm_pwr,
+ msm_mux_nav_gpio0,
+ msm_mux_nav_gpio1,
+ msm_mux_nav_gpio2,
msm_mux_pbs0,
msm_mux_pbs1,
msm_mux_pbs10,
@@ -556,7 +555,7 @@ enum monaco_functions {
msm_mux_uim0_data,
msm_mux_uim0_present,
msm_mux_uim0_reset,
- msm_mux_usb_phy,
+ msm_mux_usb2phy_ac,
msm_mux_vfr_1,
msm_mux_vsense_trigger,
msm_mux_wci_uart,
@@ -629,10 +628,6 @@ static const char * const GP_PDM2_groups[] = {
static const char * const JITTER_BIST_groups[] = {
"gpio81", "gpio82",
};
-static const char * const NAV_GPIO_groups[] = {
- "gpio6", "gpio8", "gpio9", "gpio47", "gpio48", "gpio49", "gpio97",
- "gpio98", "gpio99",
-};
static const char * const PA_INDICATOR_groups[] = {
"gpio55",
};
@@ -846,6 +841,15 @@ static const char * const mdp_vsync_groups[] = {
static const char * const mpm_pwr_groups[] = {
"gpio1",
};
+static const char * const nav_gpio0_groups[] = {
+ "gpio47",
+};
+static const char * const nav_gpio1_groups[] = {
+ "gpio48",
+};
+static const char * const nav_gpio2_groups[] = {
+ "gpio49",
+};
static const char * const pbs0_groups[] = {
"gpio20",
};
@@ -1156,7 +1160,7 @@ static const char * const uim0_present_groups[] = {
static const char * const uim0_reset_groups[] = {
"gpio71",
};
-static const char * const usb_phy_groups[] = {
+static const char * const usb2phy_ac_groups[] = {
"gpio42",
};
static const char * const vfr_1_groups[] = {
@@ -1200,7 +1204,6 @@ static const struct msm_function monaco_functions[] = {
FUNCTION(atest_tsens),
FUNCTION(CRI_TRNG1),
FUNCTION(atest_tsens2),
- FUNCTION(NAV_GPIO),
FUNCTION(mdp_vsync),
FUNCTION(GCC_GP2),
FUNCTION(qdss_gpio3),
@@ -1321,7 +1324,7 @@ static const struct msm_function monaco_functions[] = {
FUNCTION(pwm_2),
FUNCTION(phase_flag23),
FUNCTION(dac_calib23),
- FUNCTION(usb_phy),
+ FUNCTION(usb2phy_ac),
FUNCTION(pwm_8),
FUNCTION(phase_flag24),
FUNCTION(dac_calib24),
@@ -1334,6 +1337,9 @@ static const struct msm_function monaco_functions[] = {
FUNCTION(pwm_9),
FUNCTION(phase_flag26),
FUNCTION(atest_char2),
+ FUNCTION(nav_gpio0),
+ FUNCTION(nav_gpio1),
+ FUNCTION(nav_gpio2),
FUNCTION(phase_flag27),
FUNCTION(atest_char3),
FUNCTION(phase_flag28),
@@ -1394,14 +1400,14 @@ static const struct msm_pingroup monaco_groups[] = {
NA, NA, NA, 0x70000, 2),
[5] = PINGROUP(5, qup00, CRI_TRNG1, NA, qdss_gpio2, atest_tsens2, NA,
NA, NA, NA, 0, -1),
- [6] = PINGROUP(6, qup00, NAV_GPIO, mdp_vsync, GCC_GP2, NA, qdss_gpio3,
- NA, NA, NA, 0x70000, 3),
+ [6] = PINGROUP(6, qup00, mdp_vsync, GCC_GP2, NA, qdss_gpio3, NA, NA,
+ NA, NA, 0x70000, 3),
[7] = PINGROUP(7, qup00, CCI_TIMER0, cci_async, GCC_GP3, NA,
qdss_gpio4, NA, NA, NA, 0x70000, 4),
- [8] = PINGROUP(8, qup02, NAV_GPIO, GCC_GP1, NA, phase_flag3,
- qdss_gpio3, atest_usb13, ddr_pxi1, NA, 0x70000, 5),
- [9] = PINGROUP(9, qup02, NAV_GPIO, GP_PDM0, NA, phase_flag4,
- qdss_gpio4, atest_usb1, ddr_pxi1, NA, 0x70000, 6),
+ [8] = PINGROUP(8, qup02, GCC_GP1, NA, phase_flag3, qdss_gpio3,
+ atest_usb13, ddr_pxi1, NA, NA, 0x70000, 5),
+ [9] = PINGROUP(9, qup02, GP_PDM0, NA, phase_flag4, qdss_gpio4,
+ atest_usb1, ddr_pxi1, NA, NA, 0x70000, 6),
[10] = PINGROUP(10, qup01, pll_clk, AGERA_PLL, dac_calib4, NA, NA, NA,
NA, NA, 0x70000, 7),
[11] = PINGROUP(11, qup01, AGERA_PLL, NA, NA, NA, NA, NA, NA, NA,
@@ -1422,50 +1428,50 @@ static const struct msm_pingroup monaco_groups[] = {
[19] = PINGROUP(19, qup03, mdp_vsync, GP_PDM2, qdss_cti, NA, NA, NA,
NA, NA, 0x70000, 13),
[20] = PINGROUP(20, qup04, NA, pbs0, phase_flag10, qdss_gpio10,
- dac_calib10, atest_usb20, NA, NA, 0x70010, 1),
+ dac_calib10, atest_usb20, NA, NA, 0x70010, 3),
[21] = PINGROUP(21, qup04, NA, pbs1, phase_flag11, qdss_gpio11,
- dac_calib11, atest_usb21, NA, NA, 0x70010, 2),
+ dac_calib11, atest_usb21, NA, NA, 0x70010, 4),
[22] = PINGROUP(22, qup04, NA, pbs2, phase_flag12, qdss_gpio12,
- dac_calib12, atest_usb22, NA, NA, 0x70010, 3),
+ dac_calib12, atest_usb22, NA, NA, 0x70010, 5),
[23] = PINGROUP(23, qup04, NA, pbs3, phase_flag13, qdss_gpio13,
- dac_calib13, atest_usb23, NA, NA, 0x70010, 4),
+ dac_calib13, atest_usb23, NA, NA, 0x70010, 6),
[24] = PINGROUP(24, qup06, pwm_3, NA, pbs4, phase_flag14, qdss_gpio14,
- atest_usb2, NA, NA, 0x70010, 5),
+ atest_usb2, NA, NA, 0x70010, 7),
[25] = PINGROUP(25, qup06, pwm_4, NA, pbs5, phase_flag15, qdss_gpio15,
- dac_calib15, NA, NA, 0x70010, 6),
+ dac_calib15, NA, NA, 0x70010, 8),
[26] = PINGROUP(26, qup05, NA, pbs6, phase_flag16, qdss_gpio9,
- dac_calib16, NA, NA, NA, 0x70010, 7),
+ dac_calib16, NA, NA, NA, 0x70010, 9),
[27] = PINGROUP(27, qup05, NA, pbs7, phase_flag17, qdss_gpio6,
dac_calib17, NA, NA, NA, 0, -1),
[28] = PINGROUP(28, qup05, NA, pbs8, phase_flag18, qdss_gpio7,
dac_calib18, NA, NA, NA, 0, -1),
[29] = PINGROUP(29, qup05, NA, pbs9, phase_flag19, qdss_gpio8,
- dac_calib19, NA, NA, NA, 0x70010, 8),
+ dac_calib19, NA, NA, NA, 0x70010, 10),
[30] = PINGROUP(30, qup06, tgu_ch0, NA, pbs10, phase_flag20,
qdss_gpio9, dac_calib20, NA, NA, 0, -1),
[31] = PINGROUP(31, qup06, tgu_ch1, NA, pbs11, phase_flag21,
- qdss_gpio10, dac_calib21, NA, NA, 0x70010, 9),
+ qdss_gpio10, dac_calib21, NA, NA, 0x70010, 11),
[32] = PINGROUP(32, cam_mclk, NA, pbs12, NA, NA, NA, NA, NA, NA, 0, -1),
[33] = PINGROUP(33, cam_mclk, GP_PDM2, adsp_ext, NA, pbs13, dac_calib9,
- NA, NA, NA, 0x70010, 10),
+ NA, NA, NA, 0x70010, 12),
[34] = PINGROUP(34, cam_mclk, CCI_TIMER2, pwm_1, NA, pbs14, NA, NA, NA,
- NA, 0x70010, 11),
+ NA, 0x70010, 13),
[35] = PINGROUP(35, qup05, SDC2_TB, pwm_0, CRI_TRNG, NA, pbs15,
qdss_gpio, dac_calib1, NA, 0, -1),
[36] = PINGROUP(36, qup05, CCI_TIMER1, SDC1_TB, GCC_GP1, NA, pbs_out,
- qdss_gpio, NA, NA, 0x70010, 12),
+ qdss_gpio, NA, NA, 0x70010, 14),
[37] = PINGROUP(37, cci_i2c, NA, pbs_out, dac_calib14, NA, NA, NA, NA,
NA, 0, -1),
[38] = PINGROUP(38, cci_i2c, NA, pbs_out, NA, NA, NA, NA, NA, NA,
0, -1),
[39] = PINGROUP(39, cci_i2c, NA, NA, NA, NA, NA, NA, NA, NA,
- 0x70010, 13),
+ 0x70010, 15),
[40] = PINGROUP(40, cci_i2c, tgu_ch3, NA, dac_calib6, NA, NA, NA, NA,
- NA, 0x70010, 14),
+ NA, 0x70014, 0),
[41] = PINGROUP(41, NA, CCI_TIMER3, pwm_2, NA, phase_flag23,
dac_calib23, NA, NA, NA, 0x7000C, 0),
- [42] = PINGROUP(42, NA, usb_phy, pwm_8, NA, phase_flag24, dac_calib24,
- NA, NA, NA, 0x7000C, 1),
+ [42] = PINGROUP(42, NA, usb2phy_ac, NA, pwm_8, NA, phase_flag24,
+ dac_calib24, NA, NA, 0x7000C, 1),
[43] = PINGROUP(43, NA, NA, phase_flag25, dac_calib25, atest_char, NA,
NA, NA, NA, 0, -1),
[44] = PINGROUP(44, NA, atest_char0, NA, NA, NA, NA, NA, NA, NA, 0, -1),
@@ -1473,11 +1479,11 @@ static const struct msm_pingroup monaco_groups[] = {
0x7000C, 2),
[46] = PINGROUP(46, NA, pwm_9, NA, phase_flag26, atest_char2, NA, NA,
NA, NA, 0, -1),
- [47] = PINGROUP(47, NA, NAV_GPIO, NA, NA, NA, NA, NA, NA, NA,
+ [47] = PINGROUP(47, nav_gpio0, NA, NA, NA, NA, NA, NA, NA, NA,
0x7000C, 3),
- [48] = PINGROUP(48, NA, NAV_GPIO, NA, NA, NA, NA, NA, NA, NA,
+ [48] = PINGROUP(48, nav_gpio1, NA, NA, NA, NA, NA, NA, NA, NA,
0x7000C, 4),
- [49] = PINGROUP(49, NA, NAV_GPIO, NA, NA, NA, NA, NA, NA, NA,
+ [49] = PINGROUP(49, nav_gpio2, NA, NA, NA, NA, NA, NA, NA, NA,
0x7000C, 5),
[50] = PINGROUP(50, NA, NA, phase_flag27, atest_char3, NA, NA, NA, NA,
NA, 0, -1),
@@ -1494,14 +1500,14 @@ static const struct msm_pingroup monaco_groups[] = {
[57] = PINGROUP(57, NA, gsm1_tx, prng_rosc0, NA, NA, NA, NA, NA, NA,
0, -1),
[58] = PINGROUP(58, NA, NA, NA, NA, NA, NA, NA, NA, NA, 0, -1),
- [59] = PINGROUP(59, NA, prng_rosc1, NA, NA, NA, NA, NA, NA, NA, 0, -1),
+ [59] = PINGROUP(59, NA, NA, prng_rosc1, NA, NA, NA, NA, NA, NA, 0, -1),
[60] = PINGROUP(60, NA, NA, NA, NA, NA, NA, NA, NA, NA, 0, -1),
[61] = PINGROUP(61, NA, prng_rosc2, NA, NA, NA, NA, NA, NA, NA,
0x7000C, 9),
[62] = PINGROUP(62, NA, NA, NA, NA, NA, NA, NA, NA, NA, 0x7000C, 10),
- [63] = PINGROUP(63, NA, SSBI_WTR1, prng_rosc3, NA, NA, NA, NA, NA, NA,
+ [63] = PINGROUP(63, NA, NA, SSBI_WTR1, prng_rosc3, NA, NA, NA, NA, NA,
0x7000C, 11),
- [64] = PINGROUP(64, NA, SSBI_WTR1, GCC_GP2, NA, NA, NA, NA, NA, NA,
+ [64] = PINGROUP(64, NA, NA, SSBI_WTR1, GCC_GP2, NA, NA, NA, NA, NA,
0x7000C, 12),
[65] = PINGROUP(65, NA, GCC_GP3, NA, NA, NA, NA, NA, NA, NA, 0, -1),
[66] = PINGROUP(66, NA, pll_bypassnl, NA, NA, NA, NA, NA, NA, NA,
@@ -1538,9 +1544,9 @@ static const struct msm_pingroup monaco_groups[] = {
atest_gpsadc_dtest1_native, wlan1_adc1, NA, NA, NA, NA,
0x70004, 5),
[83] = PINGROUP(83, NA, atest_bbrx1, NA, NA, NA, NA, NA, NA, NA,
- 0x70010, 15),
+ 0x70014, 1),
[84] = PINGROUP(84, NA, atest_bbrx0, NA, NA, NA, NA, NA, NA, NA,
- 0x70014, 0),
+ 0x70014, 2),
[85] = PINGROUP(85, NA, NA, NA, NA, NA, NA, NA, NA, NA, 0, -1),
[86] = PINGROUP(86, NA, NA, NA, NA, NA, NA, NA, NA, NA, 0x70004, 6),
[87] = PINGROUP(87, NA, NA, NA, NA, NA, NA, NA, NA, NA, 0x70004, 7),
@@ -1555,11 +1561,11 @@ static const struct msm_pingroup monaco_groups[] = {
0x70004, 10),
[96] = PINGROUP(96, qdss_cti, NA, NA, NA, NA, NA, NA, NA, NA,
0x70004, 11),
- [97] = PINGROUP(97, NAV_GPIO, qdss_cti, NA, NA, NA, NA, NA, NA, NA,
+ [97] = PINGROUP(97, qdss_cti, NA, NA, NA, NA, NA, NA, NA, NA,
0x70004, 12),
- [98] = PINGROUP(98, NAV_GPIO, qdss_cti, NA, NA, NA, NA, NA, NA, NA,
+ [98] = PINGROUP(98, qdss_cti, NA, NA, NA, NA, NA, NA, NA, NA,
0x70004, 13),
- [99] = PINGROUP(99, NAV_GPIO, NA, NA, NA, NA, NA, NA, NA, NA, 0, -1),
+ [99] = PINGROUP(99, NA, NA, NA, NA, NA, NA, NA, NA, NA, 0, -1),
[100] = PINGROUP(100, NA, NA, NA, NA, NA, NA, NA, NA, NA, 0x70004, 14),
[101] = PINGROUP(101, QUP0_L0, QUP0_L2, qdss_cti, NA, NA, NA, NA, NA,
NA, 0x70004, 15),
@@ -1578,7 +1584,7 @@ static const struct msm_pingroup monaco_groups[] = {
[110] = PINGROUP(110, NA, NA, NA, NA, NA, NA, NA, NA, NA, 0, -1),
[111] = PINGROUP(111, qdss_cti, NA, NA, NA, NA, NA, NA, NA, NA,
0x70008, 5),
- [112] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x75000, 15, 0),
+ [112] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x75004, 0, 0),
[113] = SDC_QDSD_PINGROUP(sdc1_clk, 0x75000, 13, 6),
[114] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x75000, 11, 3),
[115] = SDC_QDSD_PINGROUP(sdc1_data, 0x75000, 9, 0),
diff --git a/drivers/pinctrl/qcom/pinctrl-shima.c b/drivers/pinctrl/qcom/pinctrl-shima.c
index 62bf631..3ceb0a3 100644
--- a/drivers/pinctrl/qcom/pinctrl-shima.c
+++ b/drivers/pinctrl/qcom/pinctrl-shima.c
@@ -1843,7 +1843,7 @@ static const struct msm_pingroup shima_groups[] = {
[203] = PINGROUP(203, NA, NA, NA, NA, NA, NA, NA, NA, NA,
0, -1),
[204] = UFS_RESET(ufs_reset, 0x1db000),
- [205] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x1d0000, 15, 0),
+ [205] = SDC_QDSD_PINGROUP(sdc1_rclk, 0x1d0004, 0, 0),
[206] = SDC_QDSD_PINGROUP(sdc1_clk, 0x1d0000, 13, 6),
[207] = SDC_QDSD_PINGROUP(sdc1_cmd, 0x1d0000, 11, 3),
[208] = SDC_QDSD_PINGROUP(sdc1_data, 0x1d0000, 9, 0),
diff --git a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
index 7961e5c..1577111 100644
--- a/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
+++ b/drivers/pinctrl/qcom/pinctrl-spmi-gpio.c
@@ -1163,6 +1163,8 @@ static const struct of_device_id pmic_gpio_of_match[] = {
{ .compatible = "qcom,pm7325-gpio", .data = (void *) 10 },
{ .compatible = "qcom,pm7325b-gpio", .data = (void *) 8 },
{ .compatible = "qcom,pm2250-gpio", .data = (void *) 10 },
+ { .compatible = "qcom,pmi632-gpio", .data = (void *) 8 },
+ { .compatible = "qcom,pm6125-gpio", .data = (void *) 9 },
{ },
};
diff --git a/drivers/platform/msm/Kconfig b/drivers/platform/msm/Kconfig
index 462ecb8..810f57a 100644
--- a/drivers/platform/msm/Kconfig
+++ b/drivers/platform/msm/Kconfig
@@ -168,6 +168,21 @@
various use cases independent of radio technology. When this is
disabled Realtek R8125 driver switches to embedded software path.
+config AQFWD_IOSS
+ tristate "AQC glue driver for IOSS v2"
+ depends on AQFWD
+ depends on IOSS
+ select ATLFWD_FWD
+ help
+ Enables IPA Ethernet Offload path on atlantic-fwd driver. It is
+ designed to support generic HW processing of UL/DL IP packets for
+ various use cases to reduce the cpu load during E2E IP traffic.
+ When this is disabled, atlantic-fwd driver switches to embedded software path.
+
+ To compile this driver as a module, choose M here. Module will be called
+ aqc_ioss.
+ If unsure, say N.
+
config IPA_ETH
bool "IPA Ethernet Offload Sub-system support"
depends on IPA3
diff --git a/drivers/platform/msm/ipa_fmwk/ipa_fmwk.c b/drivers/platform/msm/ipa_fmwk/ipa_fmwk.c
index c64edf8..6663955 100644
--- a/drivers/platform/msm/ipa_fmwk/ipa_fmwk.c
+++ b/drivers/platform/msm/ipa_fmwk/ipa_fmwk.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/ipa_fmwk.h>
@@ -203,6 +203,14 @@ struct ipa_fmwk_contex {
int (*ipa_unregister_rmnet_ctl_cb)(void);
+ int (*ipa_add_hdr)(struct ipa_ioc_add_hdr *hdrs);
+
+ int (*ipa_del_hdr)(struct ipa_ioc_del_hdr *hdls);
+
+ int (*ipa_get_hdr)(struct ipa_ioc_get_hdr *lookup);
+
+ int (*ipa_deregister_intf)(const char *name);
+
/* ipa_usb APIs */
int (*ipa_usb_init_teth_prot)(enum ipa_usb_teth_prot teth_prot,
struct ipa_usb_teth_params *teth_params,
@@ -270,6 +278,23 @@ struct ipa_fmwk_contex {
int (*ipa_get_wdi_version)(void);
+ int (*ipa_enable_wdi_pipe)(u32 clnt_hdl);
+
+ int (*ipa_disable_wdi_pipe)(u32 clnt_hdl);
+
+ int (*ipa_resume_wdi_pipe)(u32 clnt_hdl);
+
+ int (*ipa_suspend_wdi_pipe)(u32 clnt_hdl);
+
+ int (*ipa_connect_wdi_pipe)(struct ipa_wdi_in_params *in,
+ struct ipa_wdi_out_params *out);
+
+ int (*ipa_disconnect_wdi_pipe)(u32 clnt_hdl);
+
+ int (*ipa_reg_uc_rdyCB)(struct ipa_wdi_uc_ready_params *param);
+
+ int (*ipa_dereg_uc_rdyCB)(void);
+
/* ipa_gsb APIs*/
int (*ipa_bridge_init)(struct ipa_bridge_init_params *params, u32 *hdl);
@@ -475,6 +500,10 @@ int ipa_fmwk_register_ipa(const struct ipa_core_data *in)
ipa_fmwk_ctx->ipa_add_rt_rule = in->ipa_add_rt_rule;
ipa_fmwk_ctx->ipa_put_rt_tbl = in->ipa_put_rt_tbl;
ipa_fmwk_ctx->ipa_register_intf = in->ipa_register_intf;
+ ipa_fmwk_ctx->ipa_deregister_intf = in->ipa_deregister_intf;
+ ipa_fmwk_ctx->ipa_add_hdr = in->ipa_add_hdr;
+ ipa_fmwk_ctx->ipa_del_hdr = in->ipa_del_hdr;
+ ipa_fmwk_ctx->ipa_get_hdr = in->ipa_get_hdr;
ipa_fmwk_ctx->ipa_set_aggr_mode = in->ipa_set_aggr_mode;
ipa_fmwk_ctx->ipa_set_qcncm_ndp_sig = in->ipa_set_qcncm_ndp_sig;
ipa_fmwk_ctx->ipa_set_single_ndp_per_mbim =
@@ -489,6 +518,14 @@ int ipa_fmwk_register_ipa(const struct ipa_core_data *in)
ipa_fmwk_ctx->ipa_unregister_rmnet_ctl_cb =
in->ipa_unregister_rmnet_ctl_cb;
ipa_fmwk_ctx->ipa_get_default_aggr_time_limit = in->ipa_get_default_aggr_time_limit;
+ ipa_fmwk_ctx->ipa_enable_wdi_pipe = in->ipa_enable_wdi_pipe;
+ ipa_fmwk_ctx->ipa_disable_wdi_pipe = in->ipa_disable_wdi_pipe;
+ ipa_fmwk_ctx->ipa_resume_wdi_pipe = in->ipa_resume_wdi_pipe;
+ ipa_fmwk_ctx->ipa_suspend_wdi_pipe = in->ipa_suspend_wdi_pipe;
+ ipa_fmwk_ctx->ipa_connect_wdi_pipe = in->ipa_connect_wdi_pipe;
+ ipa_fmwk_ctx->ipa_disconnect_wdi_pipe = in->ipa_disconnect_wdi_pipe;
+ ipa_fmwk_ctx->ipa_reg_uc_rdyCB = in->ipa_uc_reg_rdyCB;
+ ipa_fmwk_ctx->ipa_dereg_uc_rdyCB = in->ipa_uc_dereg_rdyCB;
ipa_fmwk_ctx->ipa_ready = true;
ipa_trigger_ipa_ready_cbs();
@@ -793,6 +830,46 @@ int ipa_register_intf(const char *name,
}
EXPORT_SYMBOL(ipa_register_intf);
+int ipa_deregister_intf(const char *name)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_deregister_intf, name);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_deregister_intf);
+
+int ipa_add_hdr(struct ipa_ioc_add_hdr *hdrs)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_add_hdr, hdrs);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_add_hdr);
+
+int ipa_del_hdr(struct ipa_ioc_del_hdr *hdls)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_del_hdr, hdls);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_del_hdr);
+
+int ipa_get_hdr(struct ipa_ioc_get_hdr *lookup)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_get_hdr, lookup);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_get_hdr);
+
int ipa_set_aggr_mode(enum ipa_aggr_mode mode)
{
int ret;
@@ -1212,6 +1289,87 @@ int ipa_get_wdi_version(void)
}
EXPORT_SYMBOL(ipa_get_wdi_version);
+int ipa_enable_wdi_pipe(u32 clnt_hdl)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_enable_wdi_pipe, clnt_hdl);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_enable_wdi_pipe);
+
+int ipa_disable_wdi_pipe(u32 clnt_hdl)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_disable_wdi_pipe, clnt_hdl);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_disable_wdi_pipe);
+
+int ipa_resume_wdi_pipe(u32 clnt_hdl)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_resume_wdi_pipe, clnt_hdl);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_resume_wdi_pipe);
+
+int ipa_suspend_wdi_pipe(u32 clnt_hdl)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_suspend_wdi_pipe, clnt_hdl);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_suspend_wdi_pipe);
+
+int ipa_connect_wdi_pipe(struct ipa_wdi_in_params *in,
+ struct ipa_wdi_out_params *out)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_connect_wdi_pipe, in, out);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_connect_wdi_pipe);
+
+int ipa_disconnect_wdi_pipe(u32 clnt_hdl)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_disconnect_wdi_pipe, clnt_hdl);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_disconnect_wdi_pipe);
+
+int ipa_reg_uc_rdyCB(struct ipa_wdi_uc_ready_params *param)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_reg_uc_rdyCB, param);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_reg_uc_rdyCB);
+
+int ipa_dereg_uc_rdyCB(void)
+{
+ int ret;
+
+ IPA_FMWK_DISPATCH_RETURN(ipa_dereg_uc_rdyCB);
+
+ return ret;
+}
+EXPORT_SYMBOL(ipa_dereg_uc_rdyCB);
+
int ipa_wdi_bw_monitor(struct ipa_wdi_bw_info *info)
{
int ret;
diff --git a/drivers/platform/msm/mhi_dev/mhi.c b/drivers/platform/msm/mhi_dev/mhi.c
index 7f3d706..5d5a1eb 100644
--- a/drivers/platform/msm/mhi_dev/mhi.c
+++ b/drivers/platform/msm/mhi_dev/mhi.c
@@ -2888,6 +2888,14 @@ int mhi_dev_read_channel(struct mhi_req *mreq)
mutex_lock(&ch->ch_lock);
do {
+ if (ch->state == MHI_DEV_CH_STOPPED) {
+ mhi_log(MHI_MSG_VERBOSE,
+ "channel (%d) already stopped\n",
+ mreq->chan);
+ bytes_read = -1;
+ goto exit;
+ }
+
el = &ring->ring_cache[ring->rd_offset];
mhi_log(MHI_MSG_VERBOSE, "evtptr : 0x%llx\n",
el->tre.data_buf_ptr);
@@ -2909,13 +2917,6 @@ int mhi_dev_read_channel(struct mhi_req *mreq)
goto exit;
}
- if (ch->state == MHI_DEV_CH_STOPPED) {
- mhi_log(MHI_MSG_VERBOSE,
- "channel (%d) already stopped\n",
- mreq->chan);
- bytes_read = -1;
- goto exit;
- }
ch->tre_loc = el->tre.data_buf_ptr;
ch->tre_size = el->tre.len;
diff --git a/drivers/platform/msm/mhi_dev/mhi_uci.c b/drivers/platform/msm/mhi_dev/mhi_uci.c
index f44e7d1..e4edf6f 100644
--- a/drivers/platform/msm/mhi_dev/mhi_uci.c
+++ b/drivers/platform/msm/mhi_dev/mhi_uci.c
@@ -279,9 +279,9 @@ static const struct chan_attr uci_chan_attr_table[] = {
mhi_uci_generic_client_cb,
NULL,
NULL,
- NULL,
false,
- true
+ true,
+ 50
},
{
MHI_CLIENT_ADB_IN,
@@ -291,9 +291,9 @@ static const struct chan_attr uci_chan_attr_table[] = {
mhi_uci_generic_client_cb,
"android_adb",
NULL,
- NULL,
false,
- false
+ true,
+ 50
},
};
@@ -935,8 +935,11 @@ static int open_client_mhi_channels(struct uci_client *uci_client)
{
int rc = 0;
- if (!mhi_uci_are_channels_connected(uci_client))
+ if (!mhi_uci_are_channels_connected(uci_client)) {
+ uci_log(UCI_DBG_ERROR, "%s:Channels are not connected\n",
+ __func__);
return -ENODEV;
+ }
uci_log(UCI_DBG_DBG,
"Starting channels %d %d.\n",
@@ -1067,12 +1070,20 @@ static int mhi_uci_client_release(struct inode *mhi_inode,
struct file *file_handle)
{
struct uci_client *uci_handle = file_handle->private_data;
- int count = 0;
+ const struct chan_attr *in_chan_attr;
+ int count = 0, i;
struct mhi_req *ureq;
if (!uci_handle)
return -EINVAL;
+ in_chan_attr = uci_handle->in_chan_attr;
+ if (!in_chan_attr) {
+ uci_log(UCI_DBG_ERROR, "Null channel attributes for chan %d\n",
+ uci_handle->in_chan);
+ return -EINVAL;
+ }
+
if (atomic_sub_return(1, &uci_handle->ref_count)) {
uci_log(UCI_DBG_DBG, "Client close chan %d, ref count 0x%x\n",
iminor(mhi_inode),
@@ -1131,6 +1142,12 @@ static int mhi_uci_client_release(struct inode *mhi_inode,
iminor(mhi_inode), count);
}
+ for (i = 0; i < (in_chan_attr->nr_trbs); i++) {
+ kfree(uci_handle->in_buf_list[i].addr);
+ uci_handle->in_buf_list[i].addr = NULL;
+ uci_handle->in_buf_list[i].buf_size = 0;
+ }
+
atomic_set(&uci_handle->read_data_ready, 0);
atomic_set(&uci_handle->write_data_ready, 0);
file_handle->private_data = NULL;
@@ -1247,6 +1264,12 @@ static int __mhi_uci_client_read(struct uci_client *uci_handle,
int ret_val = 0;
do {
+ if (!mhi_uci_are_channels_connected(uci_handle)) {
+ uci_log(UCI_DBG_ERROR,
+ "%s:Channels are not connected\n", __func__);
+ return -ENODEV;
+ }
+
if (!uci_handle->pkt_loc &&
!atomic_read(&uci_ctxt.mhi_disabled)) {
ret_val = uci_handle->read(uci_handle, bytes_avail);
@@ -1393,6 +1416,12 @@ static ssize_t mhi_uci_client_write(struct file *file,
return -EIO;
}
+ if (!mhi_uci_are_channels_connected(uci_handle)) {
+ uci_log(UCI_DBG_ERROR, "%s:Channels are not connected\n",
+ __func__);
+ return -ENODEV;
+ }
+
if (count > TRB_MAX_DATA_SIZE) {
uci_log(UCI_DBG_ERROR,
"Too big write size: %lu, max supported size is %d\n",
diff --git a/drivers/power/supply/qcom/qpnp-smb5.c b/drivers/power/supply/qcom/qpnp-smb5.c
index 597f5f4..fe8b99d 100644
--- a/drivers/power/supply/qcom/qpnp-smb5.c
+++ b/drivers/power/supply/qcom/qpnp-smb5.c
@@ -2340,7 +2340,7 @@ static int smb5_determine_initial_status(struct smb5 *chip)
chg->early_usb_attach = val.intval;
if (chg->iio_chan_list_qg)
- smblib_suspend_on_debug_battery(chg);
+ smblib_config_charger_on_debug_battery(chg);
smb5_usb_plugin_irq_handler(0, &irq_data);
smb5_dc_plugin_irq_handler(0, &irq_data);
diff --git a/drivers/power/supply/qcom/smb5-lib.c b/drivers/power/supply/qcom/smb5-lib.c
index ca2bb13..799c0bf 100644
--- a/drivers/power/supply/qcom/smb5-lib.c
+++ b/drivers/power/supply/qcom/smb5-lib.c
@@ -1358,7 +1358,7 @@ static void smblib_uusb_removal(struct smb_charger *chg)
smblib_update_usb_type(chg);
}
-void smblib_suspend_on_debug_battery(struct smb_charger *chg)
+void smblib_config_charger_on_debug_battery(struct smb_charger *chg)
{
int rc = 0, val;
@@ -1368,6 +1368,8 @@ void smblib_suspend_on_debug_battery(struct smb_charger *chg)
return;
}
+ vote(chg->bat_temp_irq_disable_votable, DEBUG_BOARD_VOTER, val, 0);
+
if (chg->suspend_input_on_debug_batt) {
vote(chg->usb_icl_votable, DEBUG_BOARD_VOTER, val, 0);
vote(chg->dc_suspend_votable, DEBUG_BOARD_VOTER, val, 0);
@@ -1854,6 +1856,27 @@ static int smblib_temp_change_irq_disable_vote_callback(struct votable *votable,
return 0;
}
+static int smblib_bat_temp_irq_disable_vote_callback(struct votable *votable,
+ void *data, int disable, const char *client)
+{
+ struct smb_charger *chg = data;
+
+ if (!chg->irq_info[BAT_TEMP_IRQ].irq)
+ return 0;
+
+ if (chg->irq_info[BAT_TEMP_IRQ].enabled && disable) {
+ disable_irq_wake(chg->irq_info[BAT_TEMP_IRQ].irq);
+ disable_irq_nosync(chg->irq_info[BAT_TEMP_IRQ].irq);
+ } else if (!chg->irq_info[BAT_TEMP_IRQ].enabled && !disable) {
+ enable_irq(chg->irq_info[BAT_TEMP_IRQ].irq);
+ enable_irq_wake(chg->irq_info[BAT_TEMP_IRQ].irq);
+ }
+
+ chg->irq_info[BAT_TEMP_IRQ].enabled = !disable;
+
+ return 0;
+}
+
/*******************
* VCONN REGULATOR *
* *****************/
@@ -7379,7 +7402,7 @@ static void bms_update_work(struct work_struct *work)
chg->iio_chan_list_qg = qg_list;
}
- smblib_suspend_on_debug_battery(chg);
+ smblib_config_charger_on_debug_battery(chg);
if (chg->batt_psy)
power_supply_changed(chg->batt_psy);
@@ -8173,6 +8196,15 @@ static int smblib_create_votables(struct smb_charger *chg)
return rc;
}
+ chg->bat_temp_irq_disable_votable = create_votable(
+ "BAT_TEMP_IRQ_DISABLE", VOTE_SET_ANY,
+ smblib_bat_temp_irq_disable_vote_callback, chg);
+ if (IS_ERR(chg->bat_temp_irq_disable_votable)) {
+ rc = PTR_ERR(chg->bat_temp_irq_disable_votable);
+ chg->bat_temp_irq_disable_votable = NULL;
+ return rc;
+ }
+
return rc;
}
@@ -8186,6 +8218,8 @@ static void smblib_destroy_votables(struct smb_charger *chg)
destroy_votable(chg->awake_votable);
if (chg->chg_disable_votable)
destroy_votable(chg->chg_disable_votable);
+ if (chg->bat_temp_irq_disable_votable)
+ destroy_votable(chg->bat_temp_irq_disable_votable);
}
static void smblib_iio_deinit(struct smb_charger *chg)
diff --git a/drivers/power/supply/qcom/smb5-lib.h b/drivers/power/supply/qcom/smb5-lib.h
index 14ca5c5..d53679e 100644
--- a/drivers/power/supply/qcom/smb5-lib.h
+++ b/drivers/power/supply/qcom/smb5-lib.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (c) 2018-2020 The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
*/
#ifndef __SMB5_CHARGER_H
@@ -456,6 +456,7 @@ struct smb_charger {
struct votable *limited_irq_disable_votable;
struct votable *hdc_irq_disable_votable;
struct votable *temp_change_irq_disable_votable;
+ struct votable *bat_temp_irq_disable_votable;
struct votable *qnovo_disable_votable;
/* work */
@@ -795,7 +796,7 @@ int smblib_set_prop_ship_mode(struct smb_charger *chg,
int val);
int smblib_set_prop_rechg_soc_thresh(struct smb_charger *chg,
int val);
-void smblib_suspend_on_debug_battery(struct smb_charger *chg);
+void smblib_config_charger_on_debug_battery(struct smb_charger *chg);
int smblib_rerun_apsd_if_required(struct smb_charger *chg);
void smblib_rerun_apsd(struct smb_charger *chg);
int smblib_get_prop_fcc_delta(struct smb_charger *chg,
diff --git a/drivers/slimbus/slim-msm-ngd.c b/drivers/slimbus/slim-msm-ngd.c
index e4ec93f..4ed5357 100644
--- a/drivers/slimbus/slim-msm-ngd.c
+++ b/drivers/slimbus/slim-msm-ngd.c
@@ -1541,10 +1541,10 @@ static int ngd_slim_enable(struct msm_slim_ctrl *dev, bool enable)
int ret = 0;
if (enable) {
+ enable_irq(dev->irq);
ret = msm_slim_qmi_init(dev, false);
/* controller state should be in sync with framework state */
if (!ret) {
- enable_irq(dev->irq);
complete(&dev->qmi.qmi_comp);
if (!pm_runtime_enabled(dev->dev) ||
!pm_runtime_suspended(dev->dev))
diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig
index 8f7002a..713614f 100644
--- a/drivers/soc/qcom/Kconfig
+++ b/drivers/soc/qcom/Kconfig
@@ -299,6 +299,17 @@
Moreover, the framework also notifies userspace of transitions
between these states via sysfs.
+config MSM_QUIN_SUBSYSTEM_NOTIF_VIRT
+ tristate "MSM QUIN Subsystem Notif Virt"
+ select MSM_SUBSYSTEM_RESTART
+ help
+ This option enables the virtual MSM subsystem notification
+ framework for the QUIN platform.
+
+ The virtual MSM subsystem notif framework provides support for
+ a subsystem to notify its clients of its state, when the clients
+ are in a different virtual machine domain than the subsystem.
+
config SETUP_SSR_NOTIF_TIMEOUTS
bool "Set timeouts on SSR sysmon notifications and notifier callbacks"
help
diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile
index b441052..51b5fa9 100644
--- a/drivers/soc/qcom/Makefile
+++ b/drivers/soc/qcom/Makefile
@@ -11,6 +11,7 @@
obj-$(CONFIG_MSM_SUBSYSTEM_RESTART) += subsystem_restart.o
obj-$(CONFIG_MSM_CDSP_LOADER) += qdsp6v2/
subsystem_restart-y := msm_subsystem_restart.o subsystem_notif.o ramdump.o sysmon-qmi.o
+obj-$(CONFIG_MSM_QUIN_SUBSYSTEM_NOTIF_VIRT) += subsystem_notif_virt.o
obj-$(CONFIG_MSM_PIL_SSR_GENERIC) += subsys-pil-tz.o
obj-$(CONFIG_MSM_PIL_MSS_QDSP6V5) += pil-q6v5.o pil-msa.o pil-q6v5-mss.o
obj-$(CONFIG_MSM_SERVICE_NOTIFIER) += service-notifier.o
diff --git a/drivers/soc/qcom/icnss2/debug.c b/drivers/soc/qcom/icnss2/debug.c
index b3dfbd5..588892f 100644
--- a/drivers/soc/qcom/icnss2/debug.c
+++ b/drivers/soc/qcom/icnss2/debug.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
*/
#include <linux/err.h>
#include <linux/seq_file.h>
@@ -14,6 +14,7 @@
void *icnss_ipc_log_context;
void *icnss_ipc_log_long_context;
+void *icnss_ipc_log_long1_context;
static ssize_t icnss_regwrite_write(struct file *fp,
const char __user *user_buf,
@@ -770,6 +771,12 @@ void icnss_debug_init(void)
"icnss_long", 0);
if (!icnss_ipc_log_long_context)
icnss_pr_err("Unable to create log long context\n");
+
+ icnss_ipc_log_long1_context = ipc_log_context_create(NUM_LOG_LONG_PAGES,
+ "icnss_long1", 0);
+ if (!icnss_ipc_log_long1_context)
+ icnss_pr_err("Unable to create log long context\n");
+
}
void icnss_debug_deinit(void)
@@ -783,4 +790,9 @@ void icnss_debug_deinit(void)
ipc_log_context_destroy(icnss_ipc_log_long_context);
icnss_ipc_log_long_context = NULL;
}
+ if (icnss_ipc_log_long1_context) {
+ ipc_log_context_destroy(icnss_ipc_log_long1_context);
+ icnss_ipc_log_long1_context = NULL;
+ }
+
}
diff --git a/drivers/soc/qcom/icnss2/debug.h b/drivers/soc/qcom/icnss2/debug.h
index ada100e..ae4b258 100644
--- a/drivers/soc/qcom/icnss2/debug.h
+++ b/drivers/soc/qcom/icnss2/debug.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#ifndef _ICNSS_DEBUG_H
@@ -14,6 +14,7 @@
extern void *icnss_ipc_log_context;
extern void *icnss_ipc_log_long_context;
+extern void *icnss_ipc_log_long1_context;
#define icnss_ipc_log_string(_x...) \
ipc_log_string(icnss_ipc_log_context, _x)
@@ -21,6 +22,9 @@ extern void *icnss_ipc_log_long_context;
#define icnss_ipc_log_long_string(_x...) \
ipc_log_string(icnss_ipc_log_long_context, _x)
+#define icnss_ipc_log_long1_string(_x...) \
+ ipc_log_string(icnss_ipc_log_long1_context, _x)
+
#define icnss_pr_err(_fmt, ...) do { \
printk("%s" pr_fmt(_fmt), KERN_ERR, ##__VA_ARGS__); \
icnss_ipc_log_string("%s" pr_fmt(_fmt), "", \
@@ -49,6 +53,12 @@ extern void *icnss_ipc_log_long_context;
pr_debug(_fmt, ##__VA_ARGS__); \
icnss_ipc_log_long_string(pr_fmt(_fmt), ##__VA_ARGS__); \
} while (0)
+
+#define icnss_pr_vdbg1(_fmt, ...) do { \
+ pr_debug(_fmt, ##__VA_ARGS__); \
+ icnss_ipc_log_long1_string(pr_fmt(_fmt), ##__VA_ARGS__); \
+ } while (0)
+
#elif defined(DEBUG)
#define icnss_pr_dbg(_fmt, ...) do { \
printk("%s" pr_fmt(_fmt), KERN_DEBUG, ##__VA_ARGS__); \
@@ -61,6 +71,13 @@ extern void *icnss_ipc_log_long_context;
icnss_ipc_log_long_string("%s" pr_fmt(_fmt), "", \
##__VA_ARGS__); \
} while (0)
+
+#define icnss_pr_vdbg1(_fmt, ...) do { \
+ pr_debug(_fmt, ##__VA_ARGS__); \
+ icnss_ipc_log_long1_string("%s" pr_fmt(_fmt), "", \
+ ##__VA_ARGS__); \
+ } while (0)
+
#else
#define icnss_pr_dbg(_fmt, ...) do { \
no_printk("%s" pr_fmt(_fmt), KERN_DEBUG, ##__VA_ARGS__); \
@@ -73,6 +90,13 @@ extern void *icnss_ipc_log_long_context;
icnss_ipc_log_long_string("%s" pr_fmt(_fmt), "", \
##__VA_ARGS__); \
} while (0)
+
+#define icnss_pr_vdbg1(_fmt, ...) do { \
+ no_printk("%s" pr_fmt(_fmt), KERN_DEBUG, ##__VA_ARGS__); \
+ icnss_ipc_log_long1_string("%s" pr_fmt(_fmt), "", \
+ ##__VA_ARGS__); \
+ } while (0)
+
#endif
#ifdef CONFIG_ICNSS2_DEBUG
diff --git a/drivers/soc/qcom/icnss2/main.c b/drivers/soc/qcom/icnss2/main.c
index 56c369b..82701ea 100644
--- a/drivers/soc/qcom/icnss2/main.c
+++ b/drivers/soc/qcom/icnss2/main.c
@@ -2124,9 +2124,9 @@ static int icnss_trigger_ssr_smp2p(struct icnss_priv *priv)
ICNSS_SMEM_VALUE_MASK,
value);
if (ret)
- icnss_pr_dbg("Error in SMP2P sent ret: %d\n", ret);
+ icnss_pr_vdbg1("Error in SMP2P sent ret: %d\n", ret);
- icnss_pr_dbg("Initiate Root PD restart. SMP2P sent value: 0x%X\n",
+ icnss_pr_vdbg1("Initiate Root PD restart. SMP2P sent value: 0x%X\n",
value);
set_bit(ICNSS_HOST_TRIGGERED_PDR, &priv->state);
return ret;
@@ -3064,7 +3064,7 @@ int icnss_exit_power_save(struct device *dev)
unsigned int value = 0;
int ret;
- icnss_pr_dbg("Calling Exit Power Save\n");
+ icnss_pr_vdbg1("Calling Exit Power Save\n");
if (test_bit(ICNSS_PD_RESTART, &priv->state) ||
!test_bit(ICNSS_MODE_ON, &priv->state))
@@ -3078,9 +3078,9 @@ int icnss_exit_power_save(struct device *dev)
ICNSS_SMEM_VALUE_MASK,
value);
if (ret)
- icnss_pr_dbg("Error in SMP2P sent ret: %d\n", ret);
+ icnss_pr_vdbg1("Error in SMP2P sent ret: %d\n", ret);
- icnss_pr_dbg("SMP2P sent value: 0x%X\n", value);
+ icnss_pr_vdbg1("SMP2P sent value: 0x%X\n", value);
return ret;
}
EXPORT_SYMBOL(icnss_exit_power_save);
@@ -3530,6 +3530,32 @@ static int icnss_msa_dt_parse(struct icnss_priv *priv)
return ret;
}
+static int icnss_smmu_fault_handler(struct iommu_domain *domain,
+ struct device *dev, unsigned long iova,
+ int flags, void *handler_token)
+{
+ struct icnss_priv *priv = handler_token;
+ struct icnss_uevent_fw_down_data fw_down_data = {0};
+
+ icnss_fatal_err("SMMU fault happened with IOVA 0x%lx\n", iova);
+
+ if (!priv) {
+ icnss_pr_err("priv is NULL\n");
+ return -ENODEV;
+ }
+
+ if (test_bit(ICNSS_FW_READY, &priv->state)) {
+ fw_down_data.crashed = true;
+ icnss_call_driver_uevent(priv, ICNSS_UEVENT_FW_DOWN,
+ &fw_down_data);
+ }
+
+ icnss_trigger_recovery(&priv->pdev->dev);
+
+ /* IOMMU driver requires non-zero return value to print debug info. */
+ return -EINVAL;
+}
+
static int icnss_smmu_dt_parse(struct icnss_priv *priv)
{
int ret = 0;
@@ -3561,6 +3587,10 @@ static int icnss_smmu_dt_parse(struct icnss_priv *priv)
if (!ret && !strcmp("fastmap", iommu_dma_type)) {
icnss_pr_dbg("SMMU S1 stage enabled\n");
priv->smmu_s1_enable = true;
+ if (priv->device_id == WCN6750_DEVICE_ID)
+ iommu_set_fault_handler(priv->iommu_domain,
+ icnss_smmu_fault_handler,
+ priv);
}
res = platform_get_resource_byname(pdev,
@@ -3664,7 +3694,7 @@ static inline void icnss_get_smp2p_info(struct icnss_priv *priv)
"wlan-smp2p-out",
&priv->smp2p_info.smem_bit);
if (IS_ERR(priv->smp2p_info.smem_state)) {
- icnss_pr_dbg("Failed to get smem state %d",
+ icnss_pr_vdbg1("Failed to get smem state %d",
PTR_ERR(priv->smp2p_info.smem_state));
}
@@ -3904,10 +3934,10 @@ static int icnss_pm_suspend(struct device *dev)
ICNSS_SMEM_VALUE_MASK,
value);
if (ret)
- icnss_pr_dbg("Error in SMP2P sent ret: %d\n",
+ icnss_pr_vdbg1("Error in SMP2P sent ret: %d\n",
ret);
- icnss_pr_dbg("SMP2P sent value: 0x%X\n", value);
+ icnss_pr_vdbg1("SMP2P sent value: 0x%X\n", value);
}
priv->stats.pm_suspend++;
set_bit(ICNSS_PM_SUSPEND, &priv->state);
@@ -4042,9 +4072,9 @@ static int icnss_pm_runtime_suspend(struct device *dev)
ICNSS_SMEM_VALUE_MASK,
value);
if (ret)
- icnss_pr_dbg("Error in SMP2P sent ret: %d\n", ret);
+ icnss_pr_vdbg1("Error in SMP2P sent ret: %d\n", ret);
- icnss_pr_dbg("SMP2P sent value: 0x%X\n", value);
+ icnss_pr_vdbg1("SMP2P sent value: 0x%X\n", value);
}
out:
return ret;
diff --git a/drivers/soc/qcom/icnss2/qmi.c b/drivers/soc/qcom/icnss2/qmi.c
index 7b9c1cb..258de02 100644
--- a/drivers/soc/qcom/icnss2/qmi.c
+++ b/drivers/soc/qcom/icnss2/qmi.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
#define pr_fmt(fmt) "icnss2_qmi: " fmt
@@ -2342,8 +2342,6 @@ static void icnss_wlfw_respond_get_info_ind_cb(struct qmi_handle *qmi,
struct icnss_priv *priv = container_of(qmi, struct icnss_priv, qmi);
const struct wlfw_respond_get_info_ind_msg_v01 *ind_msg = data;
- icnss_pr_vdbg("Received QMI WLFW respond get info indication\n");
-
if (!txn) {
icnss_pr_err("Spurious indication\n");
return;
@@ -2942,9 +2940,6 @@ int icnss_wlfw_get_info_send_sync(struct icnss_priv *plat_priv, int type,
struct qmi_txn txn;
int ret = 0;
- icnss_pr_dbg("Sending get info message, type: %d, cmd length: %d, state: 0x%lx\n",
- type, cmd_len, plat_priv->state);
-
if (cmd_len > QMI_WLFW_MAX_DATA_SIZE_V01)
return -EINVAL;
diff --git a/drivers/soc/qcom/subsys-pil-tz.c b/drivers/soc/qcom/subsys-pil-tz.c
index c4e6bfc..61762f4 100644
--- a/drivers/soc/qcom/subsys-pil-tz.c
+++ b/drivers/soc/qcom/subsys-pil-tz.c
@@ -146,6 +146,7 @@ enum pas_id {
static struct icc_path *scm_perf_client;
static int scm_pas_bw_count;
static DEFINE_MUTEX(scm_pas_bw_mutex);
+static int is_inited;
static void subsys_disable_all_irqs(struct pil_tz_data *d);
static void subsys_enable_all_irqs(struct pil_tz_data *d);
@@ -180,7 +181,7 @@ static int scm_pas_enable_bw(void)
{
int ret = 0;
- if (!scm_perf_client)
+ if (IS_ERR(scm_perf_client))
return -EINVAL;
mutex_lock(&scm_pas_bw_mutex);
@@ -1344,7 +1345,7 @@ static int pil_tz_generic_probe(struct platform_device *pdev)
* is not yet registered. Return error if that driver returns with
* any error other than EPROBE_DEFER.
*/
- if (!scm_perf_client)
+ if (!is_inited)
return -EPROBE_DEFER;
if (IS_ERR(scm_perf_client))
return PTR_ERR(scm_perf_client);
@@ -1582,6 +1583,7 @@ static int pil_tz_scm_pas_probe(struct platform_device *pdev)
ret = PTR_ERR(scm_perf_client);
pr_err("scm-pas: Unable to register bus client: %d\n", ret);
}
+ is_inited = 1;
return ret;
}
diff --git a/drivers/soc/qcom/subsystem_notif_virt.c b/drivers/soc/qcom/subsystem_notif_virt.c
new file mode 100644
index 0000000..0f4ed4e
--- /dev/null
+++ b/drivers/soc/qcom/subsystem_notif_virt.c
@@ -0,0 +1,243 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
+ */
+
+#include <linux/err.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/notifier.h>
+#include <linux/list.h>
+#include <linux/slab.h>
+#include <linux/of.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/of_device.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/workqueue.h>
+#include <soc/qcom/subsystem_notif.h>
+
+#define CLIENT_STATE_OFFSET 4
+#define SUBSYS_STATE_OFFSET 8
+
+static void __iomem *base_reg;
+
+enum subsystem_type {
+ VIRTUAL,
+ NATIVE,
+};
+
+struct subsystem_descriptor {
+ const char *name;
+ u32 offset;
+ enum subsystem_type type;
+ struct notifier_block nb;
+ void *handle;
+ int ssr_irq;
+ struct list_head subsystem_list;
+ struct work_struct work;
+};
+
+static LIST_HEAD(subsystem_descriptor_list);
+static struct workqueue_struct *ssr_wq;
+
+static void subsystem_notif_wq_func(struct work_struct *work)
+{
+ struct subsystem_descriptor *subsystem =
+ container_of(work, struct subsystem_descriptor, work);
+ void *subsystem_handle;
+ int state, ret;
+
+ state = readl_relaxed(base_reg + subsystem->offset);
+ subsystem_handle = subsys_notif_add_subsys(subsystem->name);
+ ret = subsys_notif_queue_notification(subsystem_handle, state, NULL);
+ writel_relaxed(ret, base_reg + subsystem->offset + CLIENT_STATE_OFFSET);
+}
+
+static int subsystem_state_callback(struct notifier_block *this,
+ unsigned long value, void *priv)
+{
+ struct subsystem_descriptor *subsystem =
+ container_of(this, struct subsystem_descriptor, nb);
+
+ writel_relaxed(value, base_reg + subsystem->offset +
+ SUBSYS_STATE_OFFSET);
+
+ return NOTIFY_OK;
+}
+
+static irqreturn_t subsystem_restart_irq_handler(int irq, void *dev_id)
+{
+ struct subsystem_descriptor *subsystem = dev_id;
+
+ queue_work(ssr_wq, &subsystem->work);
+
+ return IRQ_HANDLED;
+}
+
+static int get_resources(struct platform_device *pdev)
+{
+ struct device_node *node;
+ struct device_node *child = NULL;
+ const char *ss_type;
+ struct resource *res;
+ struct subsystem_descriptor *subsystem = NULL;
+ int ret = 0;
+
+ res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vdev_base");
+ base_reg = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR_OR_NULL(base_reg)) {
+ dev_err(&pdev->dev, "Memory mapping failed\n");
+ return -ENOMEM;
+ }
+
+ node = pdev->dev.of_node;
+ for_each_child_of_node(node, child) {
+
+ subsystem = devm_kmalloc(&pdev->dev,
+ sizeof(struct subsystem_descriptor),
+ GFP_KERNEL);
+ if (!subsystem)
+ return -ENOMEM;
+
+ subsystem->name =
+ of_get_property(child, "subsys-name", NULL);
+ if (IS_ERR_OR_NULL(subsystem->name)) {
+ dev_err(&pdev->dev, "Could not find subsystem name\n");
+ return -EINVAL;
+ }
+
+ ret = of_property_read_u32(child, "offset",
+ &subsystem->offset);
+ if (ret) {
+ dev_err(&pdev->dev, "offset reading for %s failed\n",
+ subsystem->name);
+ return -EINVAL;
+ }
+
+ ret = of_property_read_string(child, "type",
+ &ss_type);
+ if (ret) {
+ dev_err(&pdev->dev, "type reading for %s failed\n",
+ subsystem->name);
+ return -EINVAL;
+ }
+
+ if (!strcmp(ss_type, "virtual"))
+ subsystem->type = VIRTUAL;
+
+ if (!strcmp(ss_type, "native"))
+ subsystem->type = NATIVE;
+
+ switch (subsystem->type) {
+ case NATIVE:
+ subsystem->nb.notifier_call =
+ subsystem_state_callback;
+
+ subsystem->handle =
+ subsys_notif_register_notifier(
+ subsystem->name, &subsystem->nb);
+ if (IS_ERR_OR_NULL(subsystem->handle)) {
+ dev_err(&pdev->dev,
+ "Could not register SSR notifier cb\n");
+ return -EINVAL;
+ }
+ list_add_tail(&subsystem->subsystem_list,
+ &subsystem_descriptor_list);
+ break;
+ case VIRTUAL:
+ subsystem->ssr_irq =
+ of_irq_get_byname(child, "state-irq");
+ if (subsystem->ssr_irq < 0) {
+ dev_err(&pdev->dev, "Could not find IRQ\n");
+ return -EINVAL;
+ }
+ ret = devm_request_threaded_irq(&pdev->dev,
+ subsystem->ssr_irq, NULL,
+ subsystem_restart_irq_handler,
+ IRQF_ONESHOT | IRQF_TRIGGER_RISING,
+ subsystem->name, subsystem);
+ INIT_WORK(&subsystem->work, subsystem_notif_wq_func);
+ break;
+ default:
+ dev_err(&pdev->dev, "Unsupported type %d\n",
+ subsystem->type);
+ }
+ }
+
+ return 0;
+}
+
+static void release_resources(void)
+{
+ struct subsystem_descriptor *subsystem, *node;
+
+ list_for_each_entry_safe(subsystem, node, &subsystem_descriptor_list,
+ subsystem_list) {
+ subsys_notif_unregister_notifier(subsystem->handle,
+ &subsystem->nb);
+ list_del(&subsystem->subsystem_list);
+ }
+}
+
+static int subsys_notif_virt_probe(struct platform_device *pdev)
+{
+ int ret = 0;
+
+ if (!pdev) {
+ pr_err("%s: pdev is NULL\n", __func__);
+ return -EINVAL;
+ }
+
+ ssr_wq = create_singlethread_workqueue("ssr_wq");
+ if (!ssr_wq) {
+ dev_err(&pdev->dev, "Workqueue creation failed\n");
+ return -ENOMEM;
+ }
+
+ ret = get_resources(pdev);
+ if (ret)
+ destroy_workqueue(ssr_wq);
+
+ return ret;
+}
+
+static int subsys_notif_virt_remove(struct platform_device *pdev)
+{
+ destroy_workqueue(ssr_wq);
+ release_resources();
+
+ return 0;
+}
+
+static const struct of_device_id match_table[] = {
+ { .compatible = "qcom,subsys-notif-virt" },
+ {},
+};
+
+static struct platform_driver subsys_notif_virt_driver = {
+ .probe = subsys_notif_virt_probe,
+ .remove = subsys_notif_virt_remove,
+ .driver = {
+ .name = "subsys_notif_virt",
+ .of_match_table = match_table,
+ },
+};
+
+static int __init subsys_notif_virt_init(void)
+{
+ return platform_driver_register(&subsys_notif_virt_driver);
+}
+module_init(subsys_notif_virt_init);
+
+static void __exit subsys_notif_virt_exit(void)
+{
+ platform_driver_unregister(&subsys_notif_virt_driver);
+}
+module_exit(subsys_notif_virt_exit);
+
+MODULE_DESCRIPTION("Subsystem Notification Virtual Driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/spi/spi-msm-geni.c b/drivers/spi/spi-msm-geni.c
index b5886af..a41194f 100644
--- a/drivers/spi/spi-msm-geni.c
+++ b/drivers/spi/spi-msm-geni.c
@@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
- * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/
@@ -359,10 +359,8 @@ static int setup_fifo_params(struct spi_device *spi_slv,
if (mode & SPI_CPOL)
cpol |= CPOL;
- if (!spi->slave) {
- if (mode & SPI_CPHA)
- cpha |= CPHA;
- }
+ if (mode & SPI_CPHA)
+ cpha |= CPHA;
/* SPI slave supports only mode 1, log unsuppoted mode and exit */
if (spi->slave && !(cpol == 0 && cpha == 1)) {
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 20eebab..ec5551a 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -1040,7 +1040,6 @@ int dwc3_core_init(struct dwc3 *dwc)
*/
if (!dwc3_is_usb31(dwc)) {
reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
- reg |= DWC3_GUCTL1_PARKMODE_DISABLE_HS;
reg |= DWC3_GUCTL1_PARKMODE_DISABLE_FSLS;
}
diff --git a/drivers/usb/dwc3/dwc3-msm.c b/drivers/usb/dwc3/dwc3-msm.c
index dfae9cc..4b6dbc9 100644
--- a/drivers/usb/dwc3/dwc3-msm.c
+++ b/drivers/usb/dwc3/dwc3-msm.c
@@ -4833,7 +4833,9 @@ static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on)
mdwc->host_nb.notifier_call = dwc3_msm_host_notifier;
+#ifdef USB_CONFIG
usb_register_notify(&mdwc->host_nb);
+#endif
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
if (!dwc->dis_enblslpm_quirk)
@@ -4912,7 +4914,9 @@ static int dwc3_otg_start_host(struct dwc3_msm *mdwc, int on)
mdwc->hs_phy->flags &= ~PHY_HOST_MODE;
dwc3_host_exit(dwc);
+#ifdef USB_CONFIG
usb_unregister_notify(&mdwc->host_nb);
+#endif
dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
dwc3_msm_write_reg_field(mdwc->base, DWC3_GUSB3PIPECTL(0),
diff --git a/drivers/usb/gadget/function/f_cdev.c b/drivers/usb/gadget/function/f_cdev.c
index 2b52f86..04aab9d 100644
--- a/drivers/usb/gadget/function/f_cdev.c
+++ b/drivers/usb/gadget/function/f_cdev.c
@@ -583,6 +583,8 @@ static void usb_cser_disable(struct usb_function *f)
"port(%s) deactivated\n", port->name);
usb_cser_disconnect(port);
+ port->func_is_suspended = false;
+ port->func_wakeup_allowed = false;
port->func_wakeup_pending = false;
usb_ep_disable(port->port_usb.notify);
port->port_usb.notify->driver_data = NULL;
@@ -984,6 +986,7 @@ static void usb_cser_read_complete(struct usb_ep *ep, struct usb_request *req)
{
struct f_cdev *port = ep->driver_data;
unsigned long flags;
+ int ret;
pr_debug("ep:(%pK)(%s) port:%p req_status:%d req->actual:%u\n",
ep, ep->name, port, req->status, req->actual);
@@ -993,7 +996,25 @@ static void usb_cser_read_complete(struct usb_ep *ep, struct usb_request *req)
}
spin_lock_irqsave(&port->port_lock, flags);
- if (!port->port_open || req->status || !req->actual) {
+ if (!port->port_open) {
+ list_add_tail(&req->list, &port->read_pool);
+ spin_unlock_irqrestore(&port->port_lock, flags);
+ return;
+ }
+
+ if (req->status || !req->actual) {
+ /*
+ * ECONNRESET can be returned when host issues clear EP halt,
+ * restart OUT requests if so.
+ */
+ if (req->status == -ECONNRESET) {
+ spin_unlock_irqrestore(&port->port_lock, flags);
+ ret = usb_ep_queue(ep, req, GFP_KERNEL);
+ if (!ret)
+ return;
+ spin_lock_irqsave(&port->port_lock, flags);
+ }
+
list_add_tail(&req->list, &port->read_pool);
spin_unlock_irqrestore(&port->port_lock, flags);
return;
diff --git a/drivers/usb/gadget/function/f_gsi.c b/drivers/usb/gadget/function/f_gsi.c
index 27200bc..e368bca 100644
--- a/drivers/usb/gadget/function/f_gsi.c
+++ b/drivers/usb/gadget/function/f_gsi.c
@@ -2596,6 +2596,11 @@ static void gsi_disable(struct usb_function *f)
/* send 0 len pkt to qti/qbi/gps to notify state change */
gsi_ctrl_send_cpkt_tomodem(gsi, NULL, 0);
gsi->c_port.notify_req_queued = false;
+
+ gsi->func_is_suspended = false;
+ gsi->func_wakeup_allowed = false;
+ gsi->func_wakeup_pending = false;
+
/* Disable Data Path - only if it was initialized already (alt=1) */
if (!gsi->data_interface_up) {
log_event_dbg("%s: data intf is closed", __func__);
diff --git a/drivers/usb/host/xhci-mtk-sch.c b/drivers/usb/host/xhci-mtk-sch.c
index 45c54d5..a313e75 100644
--- a/drivers/usb/host/xhci-mtk-sch.c
+++ b/drivers/usb/host/xhci-mtk-sch.c
@@ -200,6 +200,7 @@ static struct mu3h_sch_ep_info *create_sch_ep(struct usb_device *udev,
sch_ep->sch_tt = tt;
sch_ep->ep = ep;
+ INIT_LIST_HEAD(&sch_ep->tt_endpoint);
return sch_ep;
}
@@ -583,6 +584,8 @@ int xhci_mtk_sch_init(struct xhci_hcd_mtk *mtk)
mtk->sch_array = sch_array;
+ INIT_LIST_HEAD(&mtk->bw_ep_list_new);
+
return 0;
}
EXPORT_SYMBOL_GPL(xhci_mtk_sch_init);
@@ -601,19 +604,14 @@ int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
struct xhci_ep_ctx *ep_ctx;
struct xhci_slot_ctx *slot_ctx;
struct xhci_virt_device *virt_dev;
- struct mu3h_sch_bw_info *sch_bw;
struct mu3h_sch_ep_info *sch_ep;
- struct mu3h_sch_bw_info *sch_array;
unsigned int ep_index;
- int bw_index;
- int ret = 0;
xhci = hcd_to_xhci(hcd);
virt_dev = xhci->devs[udev->slot_id];
ep_index = xhci_get_endpoint_index(&ep->desc);
slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
- sch_array = mtk->sch_array;
xhci_dbg(xhci, "%s() type:%d, speed:%d, mpkt:%d, dir:%d, ep:%p\n",
__func__, usb_endpoint_type(&ep->desc), udev->speed,
@@ -632,40 +630,35 @@ int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
return 0;
}
- bw_index = get_bw_index(xhci, udev, ep);
- sch_bw = &sch_array[bw_index];
-
sch_ep = create_sch_ep(udev, ep, ep_ctx);
if (IS_ERR_OR_NULL(sch_ep))
return -ENOMEM;
setup_sch_info(udev, ep_ctx, sch_ep);
- ret = check_sch_bw(udev, sch_bw, sch_ep);
- if (ret) {
- xhci_err(xhci, "Not enough bandwidth!\n");
- if (is_fs_or_ls(udev->speed))
- drop_tt(udev);
-
- kfree(sch_ep);
- return -ENOSPC;
- }
-
- list_add_tail(&sch_ep->endpoint, &sch_bw->bw_ep_list);
-
- ep_ctx->reserved[0] |= cpu_to_le32(EP_BPKTS(sch_ep->pkts)
- | EP_BCSCOUNT(sch_ep->cs_count) | EP_BBM(sch_ep->burst_mode));
- ep_ctx->reserved[1] |= cpu_to_le32(EP_BOFFSET(sch_ep->offset)
- | EP_BREPEAT(sch_ep->repeat));
-
- xhci_dbg(xhci, " PKTS:%x, CSCOUNT:%x, BM:%x, OFFSET:%x, REPEAT:%x\n",
- sch_ep->pkts, sch_ep->cs_count, sch_ep->burst_mode,
- sch_ep->offset, sch_ep->repeat);
+ list_add_tail(&sch_ep->endpoint, &mtk->bw_ep_list_new);
return 0;
}
EXPORT_SYMBOL_GPL(xhci_mtk_add_ep_quirk);
+static void xhci_mtk_drop_ep(struct xhci_hcd_mtk *mtk, struct usb_device *udev,
+ struct mu3h_sch_ep_info *sch_ep)
+{
+ struct xhci_hcd *xhci = hcd_to_xhci(mtk->hcd);
+ int bw_index = get_bw_index(xhci, udev, sch_ep->ep);
+ struct mu3h_sch_bw_info *sch_bw = &mtk->sch_array[bw_index];
+
+ update_bus_bw(sch_bw, sch_ep, 0);
+ list_del(&sch_ep->endpoint);
+
+ if (sch_ep->sch_tt) {
+ list_del(&sch_ep->tt_endpoint);
+ drop_tt(udev);
+ }
+ kfree(sch_ep);
+}
+
void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
struct usb_host_endpoint *ep)
{
@@ -675,7 +668,7 @@ void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
struct xhci_virt_device *virt_dev;
struct mu3h_sch_bw_info *sch_array;
struct mu3h_sch_bw_info *sch_bw;
- struct mu3h_sch_ep_info *sch_ep;
+ struct mu3h_sch_ep_info *sch_ep, *tmp;
int bw_index;
xhci = hcd_to_xhci(hcd);
@@ -694,17 +687,73 @@ void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
bw_index = get_bw_index(xhci, udev, ep);
sch_bw = &sch_array[bw_index];
- list_for_each_entry(sch_ep, &sch_bw->bw_ep_list, endpoint) {
+ list_for_each_entry_safe(sch_ep, tmp, &sch_bw->bw_ep_list, endpoint) {
if (sch_ep->ep == ep) {
- update_bus_bw(sch_bw, sch_ep, 0);
- list_del(&sch_ep->endpoint);
- if (is_fs_or_ls(udev->speed)) {
- list_del(&sch_ep->tt_endpoint);
- drop_tt(udev);
- }
- kfree(sch_ep);
- break;
+ xhci_mtk_drop_ep(mtk, udev, sch_ep);
}
}
}
EXPORT_SYMBOL_GPL(xhci_mtk_drop_ep_quirk);
+
+int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
+{
+ struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+ struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
+ struct mu3h_sch_bw_info *sch_bw;
+ struct mu3h_sch_ep_info *sch_ep, *tmp;
+ int bw_index, ret;
+
+ dev_dbg(&udev->dev, "%s\n", __func__);
+
+ list_for_each_entry(sch_ep, &mtk->bw_ep_list_new, endpoint) {
+ bw_index = get_bw_index(xhci, udev, sch_ep->ep);
+ sch_bw = &mtk->sch_array[bw_index];
+
+ ret = check_sch_bw(udev, sch_bw, sch_ep);
+ if (ret) {
+ xhci_err(xhci, "Not enough bandwidth!\n");
+ return -ENOSPC;
+ }
+ }
+
+ list_for_each_entry_safe(sch_ep, tmp, &mtk->bw_ep_list_new, endpoint) {
+ struct xhci_ep_ctx *ep_ctx;
+ struct usb_host_endpoint *ep = sch_ep->ep;
+ unsigned int ep_index = xhci_get_endpoint_index(&ep->desc);
+
+ bw_index = get_bw_index(xhci, udev, ep);
+ sch_bw = &mtk->sch_array[bw_index];
+
+ list_move_tail(&sch_ep->endpoint, &sch_bw->bw_ep_list);
+
+ ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, ep_index);
+ ep_ctx->reserved[0] |= cpu_to_le32(EP_BPKTS(sch_ep->pkts)
+ | EP_BCSCOUNT(sch_ep->cs_count)
+ | EP_BBM(sch_ep->burst_mode));
+ ep_ctx->reserved[1] |= cpu_to_le32(EP_BOFFSET(sch_ep->offset)
+ | EP_BREPEAT(sch_ep->repeat));
+
+ xhci_dbg(xhci, " PKTS:%x, CSCOUNT:%x, BM:%x, OFFSET:%x, REPEAT:%x\n",
+ sch_ep->pkts, sch_ep->cs_count, sch_ep->burst_mode,
+ sch_ep->offset, sch_ep->repeat);
+ }
+
+ return xhci_check_bandwidth(hcd, udev);
+}
+EXPORT_SYMBOL_GPL(xhci_mtk_check_bandwidth);
+
+void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
+{
+ struct xhci_hcd_mtk *mtk = hcd_to_mtk(hcd);
+ struct mu3h_sch_ep_info *sch_ep, *tmp;
+
+ dev_dbg(&udev->dev, "%s\n", __func__);
+
+ list_for_each_entry_safe(sch_ep, tmp, &mtk->bw_ep_list_new, endpoint) {
+ xhci_mtk_drop_ep(mtk, udev, sch_ep);
+ }
+
+ xhci_reset_bandwidth(hcd, udev);
+}
+EXPORT_SYMBOL_GPL(xhci_mtk_reset_bandwidth);
diff --git a/drivers/usb/host/xhci-mtk.c b/drivers/usb/host/xhci-mtk.c
index 85f1ff0..09b6721 100644
--- a/drivers/usb/host/xhci-mtk.c
+++ b/drivers/usb/host/xhci-mtk.c
@@ -347,6 +347,8 @@ static void usb_wakeup_set(struct xhci_hcd_mtk *mtk, bool enable)
static int xhci_mtk_setup(struct usb_hcd *hcd);
static const struct xhci_driver_overrides xhci_mtk_overrides __initconst = {
.reset = xhci_mtk_setup,
+ .check_bandwidth = xhci_mtk_check_bandwidth,
+ .reset_bandwidth = xhci_mtk_reset_bandwidth,
};
static struct hc_driver __read_mostly xhci_mtk_hc_driver;
diff --git a/drivers/usb/host/xhci-mtk.h b/drivers/usb/host/xhci-mtk.h
index 5ac458b..5ba25b6 100644
--- a/drivers/usb/host/xhci-mtk.h
+++ b/drivers/usb/host/xhci-mtk.h
@@ -130,6 +130,7 @@ struct mu3c_ippc_regs {
struct xhci_hcd_mtk {
struct device *dev;
struct usb_hcd *hcd;
+ struct list_head bw_ep_list_new;
struct mu3h_sch_bw_info *sch_array;
struct mu3c_ippc_regs __iomem *ippc_regs;
bool has_ippc;
@@ -166,6 +167,8 @@ int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
struct usb_host_endpoint *ep);
void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd, struct usb_device *udev,
struct usb_host_endpoint *ep);
+int xhci_mtk_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
+void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
#else
static inline int xhci_mtk_add_ep_quirk(struct usb_hcd *hcd,
@@ -179,6 +182,16 @@ static inline void xhci_mtk_drop_ep_quirk(struct usb_hcd *hcd,
{
}
+static inline int xhci_mtk_check_bandwidth(struct usb_hcd *hcd,
+ struct usb_device *udev)
+{
+ return 0;
+}
+
+static inline void xhci_mtk_reset_bandwidth(struct usb_hcd *hcd,
+ struct usb_device *udev)
+{
+}
#endif
#endif /* _XHCI_MTK_H_ */
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index e44b440..3e16e34 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -2900,7 +2900,7 @@ static void xhci_check_bw_drop_ep_streams(struct xhci_hcd *xhci,
* else should be touching the xhci->devs[slot_id] structure, so we
* don't need to take the xhci->lock for manipulating that.
*/
-static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
+int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
{
int i;
int ret = 0;
@@ -2997,7 +2997,7 @@ static int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
return ret;
}
-static void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
+void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev)
{
struct xhci_hcd *xhci;
struct xhci_virt_device *virt_dev;
@@ -5558,6 +5558,10 @@ void xhci_init_driver(struct hc_driver *drv,
drv->reset = over->reset;
if (over->start)
drv->start = over->start;
+ if (over->check_bandwidth)
+ drv->check_bandwidth = over->check_bandwidth;
+ if (over->reset_bandwidth)
+ drv->reset_bandwidth = over->reset_bandwidth;
}
}
EXPORT_SYMBOL_GPL(xhci_init_driver);
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 37a5d4a..d51d635 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1918,6 +1918,8 @@ struct xhci_driver_overrides {
size_t extra_priv_size;
int (*reset)(struct usb_hcd *hcd);
int (*start)(struct usb_hcd *hcd);
+ int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
+ void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
};
#define XHCI_CFC_DELAY 10
@@ -2072,6 +2074,8 @@ int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
void xhci_shutdown(struct usb_hcd *hcd);
void xhci_init_driver(struct hc_driver *drv,
const struct xhci_driver_overrides *over);
+int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
+void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
int xhci_ext_cap_init(struct xhci_hcd *xhci);
diff --git a/drivers/video/backlight/qcom-spmi-wled.c b/drivers/video/backlight/qcom-spmi-wled.c
index deb2847..156ed0e 100644
--- a/drivers/video/backlight/qcom-spmi-wled.c
+++ b/drivers/video/backlight/qcom-spmi-wled.c
@@ -990,7 +990,7 @@ static bool wled_auto_cal_required(struct wled *wled)
static int wled_auto_calibrate_at_init(struct wled *wled)
{
- int rc;
+ int rc, delay_time_us;
bool fault_set;
if (!wled->cfg.auto_calib_enabled)
@@ -1003,6 +1003,23 @@ static int wled_auto_calibrate_at_init(struct wled *wled)
}
if (fault_set) {
+ wled_get_ovp_delay(wled, &delay_time_us);
+
+ if (delay_time_us < 20000)
+ usleep_range(delay_time_us, delay_time_us + 1000);
+ else
+ msleep(delay_time_us / 1000);
+
+ rc = wled_get_ovp_fault_status(wled, &fault_set);
+ if (rc < 0) {
+ pr_err("Error in getting OVP fault_sts, rc=%d\n", rc);
+ return rc;
+ }
+ if (!fault_set) {
+ pr_debug("WLED OVP fault cleared, not running auto calibration\n");
+ return rc;
+ }
+
mutex_lock(&wled->lock);
rc = wled_auto_calibrate(wled);
mutex_unlock(&wled->lock);
diff --git a/include/dt-bindings/phy/qcom,usb3-11nm-qmp-combo.h b/include/dt-bindings/phy/qcom,usb3-11nm-qmp-combo.h
new file mode 100644
index 0000000..ff7fe6e
--- /dev/null
+++ b/include/dt-bindings/phy/qcom,usb3-11nm-qmp-combo.h
@@ -0,0 +1,643 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019-2021, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_PHY_QCOM_11NM_QMP_COMBO_USB_H
+#define _DT_BINDINGS_PHY_QCOM_11NM_QMP_COMBO_USB_H
+
+#define USB3PHY_QSERDES_COM_ATB_SEL1 0x0000
+#define USB3PHY_QSERDES_COM_ATB_SEL2 0x0004
+#define USB3PHY_QSERDES_COM_FREQ_UPDATE 0x0008
+#define USB3PHY_QSERDES_COM_BG_TIMER 0x000C
+#define USB3PHY_QSERDES_COM_SSC_EN_CENTER 0x0010
+#define USB3PHY_QSERDES_COM_SSC_ADJ_PER1 0x0014
+#define USB3PHY_QSERDES_COM_SSC_ADJ_PER2 0x0018
+#define USB3PHY_QSERDES_COM_SSC_PER1 0x001C
+#define USB3PHY_QSERDES_COM_SSC_PER2 0x0020
+#define USB3PHY_QSERDES_COM_SSC_STEP_SIZE1 0x0024
+#define USB3PHY_QSERDES_COM_SSC_STEP_SIZE2 0x0028
+#define USB3PHY_QSERDES_COM_POST_DIV 0x002C
+#define USB3PHY_QSERDES_COM_POST_DIV_MUX 0x0030
+#define USB3PHY_QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x0034
+#define USB3PHY_QSERDES_COM_CLK_ENABLE1 0x0038
+#define USB3PHY_QSERDES_COM_SYS_CLK_CTRL 0x003C
+#define USB3PHY_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0040
+#define USB3PHY_QSERDES_COM_PLL_EN 0x0044
+#define USB3PHY_QSERDES_COM_PLL_IVCO 0x0048
+#define USB3PHY_QSERDES_COM_LOCK_CMP1_MODE0 0x004C
+#define USB3PHY_QSERDES_COM_LOCK_CMP2_MODE0 0x0050
+#define USB3PHY_QSERDES_COM_LOCK_CMP3_MODE0 0x0054
+#define USB3PHY_QSERDES_COM_LOCK_CMP1_MODE1 0x0058
+#define USB3PHY_QSERDES_COM_LOCK_CMP2_MODE1 0x005C
+#define USB3PHY_QSERDES_COM_LOCK_CMP3_MODE1 0x0060
+#define USB3PHY_QSERDES_COM_CMN_RSVD0 0x0064
+#define USB3PHY_QSERDES_COM_EP_CLOCK_DETECT_CTRL 0x0068
+#define USB3PHY_QSERDES_COM_SYSCLK_DET_COMP_STATUS 0x006C
+#define USB3PHY_QSERDES_COM_BG_TRIM 0x0070
+#define USB3PHY_QSERDES_COM_CLK_EP_DIV 0x0074
+#define USB3PHY_QSERDES_COM_CP_CTRL_MODE0 0x0078
+#define USB3PHY_QSERDES_COM_CP_CTRL_MODE1 0x007C
+#define USB3PHY_QSERDES_COM_CMN_RSVD1 0x0080
+#define USB3PHY_QSERDES_COM_PLL_RCTRL_MODE0 0x0084
+#define USB3PHY_QSERDES_COM_PLL_RCTRL_MODE1 0x0088
+#define USB3PHY_QSERDES_COM_CMN_RSVD2 0x008C
+#define USB3PHY_QSERDES_COM_PLL_CCTRL_MODE0 0x0090
+#define USB3PHY_QSERDES_COM_PLL_CCTRL_MODE1 0x0094
+#define USB3PHY_QSERDES_COM_CMN_RSVD3 0x0098
+#define USB3PHY_QSERDES_COM_PLL_CNTRL 0x009C
+#define USB3PHY_QSERDES_COM_PHASE_SEL_CTRL 0x00A0
+#define USB3PHY_QSERDES_COM_PHASE_SEL_DC 0x00A4
+#define USB3PHY_QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x00A8
+#define USB3PHY_QSERDES_COM_SYSCLK_EN_SEL 0x00AC
+#define USB3PHY_QSERDES_COM_CML_SYSCLK_SEL 0x00B0
+#define USB3PHY_QSERDES_COM_RESETSM_CNTRL 0x00B4
+#define USB3PHY_QSERDES_COM_RESETSM_CNTRL2 0x00B8
+#define USB3PHY_QSERDES_COM_RESTRIM_CTRL 0x00BC
+#define USB3PHY_QSERDES_COM_RESTRIM_CTRL2 0x00C0
+#define USB3PHY_QSERDES_COM_RESCODE_DIV_NUM 0x00C4
+#define USB3PHY_QSERDES_COM_LOCK_CMP_EN 0x00C8
+#define USB3PHY_QSERDES_COM_LOCK_CMP_CFG 0x00CC
+#define USB3PHY_QSERDES_COM_DEC_START_MODE0 0x00D0
+#define USB3PHY_QSERDES_COM_DEC_START_MODE1 0x00D4
+#define USB3PHY_QSERDES_COM_VCOCAL_DEADMAN_CTRL 0x00D8
+#define USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE0 0x00DC
+#define USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE0 0x00E0
+#define USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE0 0x00E4
+#define USB3PHY_QSERDES_COM_DIV_FRAC_START1_MODE1 0x00E8
+#define USB3PHY_QSERDES_COM_DIV_FRAC_START2_MODE1 0x00EC
+#define USB3PHY_QSERDES_COM_DIV_FRAC_START3_MODE1 0x00F0
+#define USB3PHY_QSERDES_COM_VCO_TUNE_MINVAL1 0x00F4
+#define USB3PHY_QSERDES_COM_VCO_TUNE_MINVAL2 0x00F8
+#define USB3PHY_QSERDES_COM_CMN_RSVD4 0x00FC
+#define USB3PHY_QSERDES_COM_INTEGLOOP_INITVAL 0x0100
+#define USB3PHY_QSERDES_COM_INTEGLOOP_EN 0x0104
+#define USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x0108
+#define USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x010C
+#define USB3PHY_QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x0110
+#define USB3PHY_QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x0114
+#define USB3PHY_QSERDES_COM_VCO_TUNE_MAXVAL1 0x0118
+#define USB3PHY_QSERDES_COM_VCO_TUNE_MAXVAL2 0x011C
+#define USB3PHY_QSERDES_COM_RES_TRIM_CONTROL2 0x0120
+#define USB3PHY_QSERDES_COM_VCO_TUNE_CTRL 0x0124
+#define USB3PHY_QSERDES_COM_VCO_TUNE_MAP 0x0128
+#define USB3PHY_QSERDES_COM_VCO_TUNE1_MODE0 0x012C
+#define USB3PHY_QSERDES_COM_VCO_TUNE2_MODE0 0x0130
+#define USB3PHY_QSERDES_COM_VCO_TUNE1_MODE1 0x0134
+#define USB3PHY_QSERDES_COM_VCO_TUNE2_MODE1 0x0138
+#define USB3PHY_QSERDES_COM_VCO_TUNE_INITVAL1 0x013C
+#define USB3PHY_QSERDES_COM_VCO_TUNE_INITVAL2 0x0140
+#define USB3PHY_QSERDES_COM_VCO_TUNE_TIMER1 0x0144
+#define USB3PHY_QSERDES_COM_VCO_TUNE_TIMER2 0x0148
+#define USB3PHY_QSERDES_COM_SAR 0x014C
+#define USB3PHY_QSERDES_COM_SAR_CLK 0x0150
+#define USB3PHY_QSERDES_COM_SAR_CODE_OUT_STATUS 0x0154
+#define USB3PHY_QSERDES_COM_SAR_CODE_READY_STATUS 0x0158
+#define USB3PHY_QSERDES_COM_CMN_STATUS 0x015C
+#define USB3PHY_QSERDES_COM_RESET_SM_STATUS 0x0160
+#define USB3PHY_QSERDES_COM_RESTRIM_CODE_STATUS 0x0164
+#define USB3PHY_QSERDES_COM_PLLCAL_CODE1_STATUS 0x0168
+#define USB3PHY_QSERDES_COM_PLLCAL_CODE2_STATUS 0x016C
+#define USB3PHY_QSERDES_COM_BG_CTRL 0x0170
+#define USB3PHY_QSERDES_COM_CLK_SELECT 0x0174
+#define USB3PHY_QSERDES_COM_HSCLK_SEL 0x0178
+#define USB3PHY_QSERDES_COM_INTEGLOOP_BINCODE_STATUS 0x017C
+#define USB3PHY_QSERDES_COM_PLL_ANALOG 0x0180
+#define USB3PHY_QSERDES_COM_CORECLK_DIV 0x0184
+#define USB3PHY_QSERDES_COM_SW_RESET 0x0188
+#define USB3PHY_QSERDES_COM_CORE_CLK_EN 0x018C
+#define USB3PHY_QSERDES_COM_C_READY_STATUS 0x0190
+#define USB3PHY_QSERDES_COM_CMN_CONFIG 0x0194
+#define USB3PHY_QSERDES_COM_CMN_RATE_OVERRIDE 0x0198
+#define USB3PHY_QSERDES_COM_SVS_MODE_CLK_SEL 0x019C
+#define USB3PHY_QSERDES_COM_DEBUG_BUS0 0x01A0
+#define USB3PHY_QSERDES_COM_DEBUG_BUS1 0x01A4
+#define USB3PHY_QSERDES_COM_DEBUG_BUS2 0x01A8
+#define USB3PHY_QSERDES_COM_DEBUG_BUS3 0x01AC
+#define USB3PHY_QSERDES_COM_DEBUG_BUS_SEL 0x01B0
+#define USB3PHY_QSERDES_COM_CMN_MISC1 0x01B4
+#define USB3PHY_QSERDES_COM_CMN_MISC2 0x01B8
+#define USB3PHY_QSERDES_COM_CORECLK_DIV_MODE1 0x01BC
+#define USB3PHY_QSERDES_COM_CMN_RSVD5 0x01C0
+#define USB3PHY_QSERDES_TXA_BIST_MODE_LANENO 0x0200
+#define USB3PHY_QSERDES_TXA_BIST_INVERT 0x0204
+#define USB3PHY_QSERDES_TXA_CLKBUF_ENABLE 0x0208
+#define USB3PHY_QSERDES_TXA_TX_EMP_POST1_LVL 0x020C
+#define USB3PHY_QSERDES_TXA_TX_POST2_EMPH 0x0210
+#define USB3PHY_QSERDES_TXA_TX_BOOST_LVL_UP_DN 0x0214
+#define USB3PHY_QSERDES_TXA_TX_IDLE_LVL_LARGE_AMP 0x0218
+#define USB3PHY_QSERDES_TXA_TX_DRV_LVL 0x021C
+#define USB3PHY_QSERDES_TXA_TX_DRV_LVL_OFFSET 0x0220
+#define USB3PHY_QSERDES_TXA_RESET_TSYNC_EN 0x0224
+#define USB3PHY_QSERDES_TXA_PRE_STALL_LDO_BOOST_EN 0x0228
+#define USB3PHY_QSERDES_TXA_TX_BAND 0x022C
+#define USB3PHY_QSERDES_TXA_SLEW_CNTL 0x0230
+#define USB3PHY_QSERDES_TXA_INTERFACE_SELECT 0x0234
+#define USB3PHY_QSERDES_TXA_LPB_EN 0x0238
+#define USB3PHY_QSERDES_TXA_RES_CODE_LANE_TX 0x023C
+#define USB3PHY_QSERDES_TXA_RES_CODE_LANE_RX 0x0240
+#define USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x0244
+#define USB3PHY_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0248
+#define USB3PHY_QSERDES_TXA_PERL_LENGTH1 0x024C
+#define USB3PHY_QSERDES_TXA_PERL_LENGTH2 0x0250
+#define USB3PHY_QSERDES_TXA_SERDES_BYP_EN_OUT 0x0254
+#define USB3PHY_QSERDES_TXA_DEBUG_BUS_SEL 0x0258
+#define USB3PHY_QSERDES_TXA_TRANSCEIVER_BIAS_EN 0x025C
+#define USB3PHY_QSERDES_TXA_HIGHZ_DRVR_EN 0x0260
+#define USB3PHY_QSERDES_TXA_TX_POL_INV 0x0264
+#define USB3PHY_QSERDES_TXA_PARRATE_REC_DETECT_IDLE_EN 0x0268
+#define USB3PHY_QSERDES_TXA_BIST_PATTERN1 0x026C
+#define USB3PHY_QSERDES_TXA_BIST_PATTERN2 0x0270
+#define USB3PHY_QSERDES_TXA_BIST_PATTERN3 0x0274
+#define USB3PHY_QSERDES_TXA_BIST_PATTERN4 0x0278
+#define USB3PHY_QSERDES_TXA_BIST_PATTERN5 0x027C
+#define USB3PHY_QSERDES_TXA_BIST_PATTERN6 0x0280
+#define USB3PHY_QSERDES_TXA_BIST_PATTERN7 0x0284
+#define USB3PHY_QSERDES_TXA_BIST_PATTERN8 0x0288
+#define USB3PHY_QSERDES_TXA_LANE_MODE_1 0x028C
+#define USB3PHY_QSERDES_TXA_LANE_MODE_2 0x0290
+#define USB3PHY_QSERDES_TXA_LANE_MODE_3 0x0294
+#define USB3PHY_QSERDES_TXA_ATB_SEL1 0x0298
+#define USB3PHY_QSERDES_TXA_ATB_SEL2 0x029C
+#define USB3PHY_QSERDES_TXA_RCV_DETECT_LVL 0x02A0
+#define USB3PHY_QSERDES_TXA_RCV_DETECT_LVL_2 0x02A4
+#define USB3PHY_QSERDES_TXA_PRBS_SEED1 0x02A8
+#define USB3PHY_QSERDES_TXA_PRBS_SEED2 0x02AC
+#define USB3PHY_QSERDES_TXA_PRBS_SEED3 0x02B0
+#define USB3PHY_QSERDES_TXA_PRBS_SEED4 0x02B4
+#define USB3PHY_QSERDES_TXA_RESET_GEN 0x02B8
+#define USB3PHY_QSERDES_TXA_RESET_GEN_MUXES 0x02BC
+#define USB3PHY_QSERDES_TXA_TRAN_DRVR_EMP_EN 0x02C0
+#define USB3PHY_QSERDES_TXA_TX_INTERFACE_MODE 0x02C4
+#define USB3PHY_QSERDES_TXA_PWM_CTRL 0x02C8
+#define USB3PHY_QSERDES_TXA_PWM_ENCODED_OR_DATA 0x02CC
+#define USB3PHY_QSERDES_TXA_PWM_GEAR_1_DIVIDER_BAND2 0x02D0
+#define USB3PHY_QSERDES_TXA_PWM_GEAR_2_DIVIDER_BAND2 0x02D4
+#define USB3PHY_QSERDES_TXA_PWM_GEAR_3_DIVIDER_BAND2 0x02D8
+#define USB3PHY_QSERDES_TXA_PWM_GEAR_4_DIVIDER_BAND2 0x02DC
+#define USB3PHY_QSERDES_TXA_PWM_GEAR_1_DIVIDER_BAND0_1 0x02E0
+#define USB3PHY_QSERDES_TXA_PWM_GEAR_2_DIVIDER_BAND0_1 0x02E4
+#define USB3PHY_QSERDES_TXA_PWM_GEAR_3_DIVIDER_BAND0_1 0x02E8
+#define USB3PHY_QSERDES_TXA_PWM_GEAR_4_DIVIDER_BAND0_1 0x02EC
+#define USB3PHY_QSERDES_TXA_VMODE_CTRL1 0x02F0
+#define USB3PHY_QSERDES_TXA_ALOG_OBSV_BUS_CTRL_1 0x02F4
+#define USB3PHY_QSERDES_TXA_BIST_STATUS 0x02F8
+#define USB3PHY_QSERDES_TXA_BIST_ERROR_COUNT1 0x02FC
+#define USB3PHY_QSERDES_TXA_BIST_ERROR_COUNT2 0x0300
+#define USB3PHY_QSERDES_TXA_ALOG_OBSV_BUS_STATUS_1 0x0304
+#define USB3PHY_QSERDES_TXA_DIG_BKUP_CTRL 0x0308
+#define USB3PHY_QSERDES_RXA_UCDR_FO_GAIN_HALF 0x0400
+#define USB3PHY_QSERDES_RXA_UCDR_FO_GAIN_QUARTER 0x0404
+#define USB3PHY_QSERDES_RXA_UCDR_FO_GAIN 0x0408
+#define USB3PHY_QSERDES_RXA_UCDR_SO_GAIN_HALF 0x040C
+#define USB3PHY_QSERDES_RXA_UCDR_SO_GAIN_QUARTER 0x0410
+#define USB3PHY_QSERDES_RXA_UCDR_SO_GAIN 0x0414
+#define USB3PHY_QSERDES_RXA_UCDR_SVS_FO_GAIN_HALF 0x0418
+#define USB3PHY_QSERDES_RXA_UCDR_SVS_FO_GAIN_QUARTER 0x041C
+#define USB3PHY_QSERDES_RXA_UCDR_SVS_FO_GAIN 0x0420
+#define USB3PHY_QSERDES_RXA_UCDR_SVS_SO_GAIN_HALF 0x0424
+#define USB3PHY_QSERDES_RXA_UCDR_SVS_SO_GAIN_QUARTER 0x0428
+#define USB3PHY_QSERDES_RXA_UCDR_SVS_SO_GAIN 0x042C
+#define USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x0430
+#define USB3PHY_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x0434
+#define USB3PHY_QSERDES_RXA_UCDR_FO_TO_SO_DELAY 0x0438
+#define USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0x043C
+#define USB3PHY_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0440
+#define USB3PHY_QSERDES_RXA_UCDR_PI_CONTROLS 0x0444
+#define USB3PHY_QSERDES_RXA_UCDR_SB2_THRESH1 0x0448
+#define USB3PHY_QSERDES_RXA_UCDR_SB2_THRESH2 0x044C
+#define USB3PHY_QSERDES_RXA_UCDR_SB2_GAIN1 0x0450
+#define USB3PHY_QSERDES_RXA_UCDR_SB2_GAIN2 0x0454
+#define USB3PHY_QSERDES_RXA_AUX_CONTROL 0x0458
+#define USB3PHY_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0x045C
+#define USB3PHY_QSERDES_RXA_RCLK_AUXDATA_SEL 0x0460
+#define USB3PHY_QSERDES_RXA_AC_JTAG_ENABLE 0x0464
+#define USB3PHY_QSERDES_RXA_AC_JTAG_INITP 0x0468
+#define USB3PHY_QSERDES_RXA_AC_JTAG_INITN 0x046C
+#define USB3PHY_QSERDES_RXA_AC_JTAG_LVL 0x0470
+#define USB3PHY_QSERDES_RXA_AC_JTAG_MODE 0x0474
+#define USB3PHY_QSERDES_RXA_AC_JTAG_RESET 0x0478
+#define USB3PHY_QSERDES_RXA_RX_TERM_BW 0x047C
+#define USB3PHY_QSERDES_RXA_RX_RCVR_IQ_EN 0x0480
+#define USB3PHY_QSERDES_RXA_RX_IDAC_I_DC_OFFSETS 0x0484
+#define USB3PHY_QSERDES_RXA_RX_IDAC_IBAR_DC_OFFSETS 0x0488
+#define USB3PHY_QSERDES_RXA_RX_IDAC_Q_DC_OFFSETS 0x048C
+#define USB3PHY_QSERDES_RXA_RX_IDAC_QBAR_DC_OFFSETS 0x0490
+#define USB3PHY_QSERDES_RXA_RX_IDAC_A_DC_OFFSETS 0x0494
+#define USB3PHY_QSERDES_RXA_RX_IDAC_ABAR_DC_OFFSETS 0x0498
+#define USB3PHY_QSERDES_RXA_RX_IDAC_EN 0x049C
+#define USB3PHY_QSERDES_RXA_RX_IDAC_ENABLES 0x04A0
+#define USB3PHY_QSERDES_RXA_RX_IDAC_SIGN 0x04A4
+#define USB3PHY_QSERDES_RXA_RX_HIGHZ_HIGHRATE 0x04A8
+#define USB3PHY_QSERDES_RXA_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x04AC
+#define USB3PHY_QSERDES_RXA_DFE_1 0x04B0
+#define USB3PHY_QSERDES_RXA_DFE_2 0x04B4
+#define USB3PHY_QSERDES_RXA_DFE_3 0x04B8
+#define USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL1 0x04BC
+#define USB3PHY_QSERDES_RXA_VGA_CAL_CNTRL2 0x04C0
+#define USB3PHY_QSERDES_RXA_GM_CAL 0x04C4
+#define USB3PHY_QSERDES_RXA_RX_EQ_GAIN2_LSB 0x04C8
+#define USB3PHY_QSERDES_RXA_RX_EQ_GAIN2_MSB 0x04CC
+#define USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL1 0x04D0
+#define USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x04D4
+#define USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x04D8
+#define USB3PHY_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x04DC
+#define USB3PHY_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0x04E0
+#define USB3PHY_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x04E4
+#define USB3PHY_QSERDES_RXA_RX_IDAC_MEASURE_TIME 0x04E8
+#define USB3PHY_QSERDES_RXA_RX_IDAC_ACCUMULATOR 0x04EC
+#define USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_LSB 0x04F0
+#define USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_MSB 0x04F4
+#define USB3PHY_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x04F8
+#define USB3PHY_QSERDES_RXA_RX_OFFSET_ADAPTOR_CNTRL2 0x04FC
+#define USB3PHY_QSERDES_RXA_SIGDET_ENABLES 0x0500
+#define USB3PHY_QSERDES_RXA_SIGDET_CNTRL 0x0504
+#define USB3PHY_QSERDES_RXA_SIGDET_LVL 0x0508
+#define USB3PHY_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x050C
+#define USB3PHY_QSERDES_RXA_RX_BAND 0x0510
+#define USB3PHY_QSERDES_RXA_CDR_FREEZE_UP_DN 0x0514
+#define USB3PHY_QSERDES_RXA_CDR_RESET_OVERRIDE 0x0518
+#define USB3PHY_QSERDES_RXA_RX_INTERFACE_MODE 0x051C
+#define USB3PHY_QSERDES_RXA_JITTER_GEN_MODE 0x0520
+#define USB3PHY_QSERDES_RXA_BUJ_AMP 0x0524
+#define USB3PHY_QSERDES_RXA_SJ_AMP1 0x0528
+#define USB3PHY_QSERDES_RXA_SJ_AMP2 0x052C
+#define USB3PHY_QSERDES_RXA_SJ_PER1 0x0530
+#define USB3PHY_QSERDES_RXA_SJ_PER2 0x0534
+#define USB3PHY_QSERDES_RXA_BUJ_STEP_FREQ1 0x0538
+#define USB3PHY_QSERDES_RXA_BUJ_STEP_FREQ2 0x053C
+#define USB3PHY_QSERDES_RXA_PPM_OFFSET1 0x0540
+#define USB3PHY_QSERDES_RXA_PPM_OFFSET2 0x0544
+#define USB3PHY_QSERDES_RXA_SIGN_PPM_PERIOD1 0x0548
+#define USB3PHY_QSERDES_RXA_SIGN_PPM_PERIOD2 0x054C
+#define USB3PHY_QSERDES_RXA_RX_PWM_ENABLE_AND_DATA 0x0550
+#define USB3PHY_QSERDES_RXA_RX_PWM_GEAR1_TIMEOUT_COUNT 0x0554
+#define USB3PHY_QSERDES_RXA_RX_PWM_GEAR2_TIMEOUT_COUNT 0x0558
+#define USB3PHY_QSERDES_RXA_RX_PWM_GEAR3_TIMEOUT_COUNT 0x055C
+#define USB3PHY_QSERDES_RXA_RX_PWM_GEAR4_TIMEOUT_COUNT 0x0560
+#define USB3PHY_QSERDES_RXA_RX_MODE_00 0x0564
+#define USB3PHY_QSERDES_RXA_RX_MODE_01 0x0568
+#define USB3PHY_QSERDES_RXA_RX_MODE_10 0x056C
+#define USB3PHY_QSERDES_RXA_ALOG_OBSV_BUS_CTRL_1 0x0570
+#define USB3PHY_QSERDES_RXA_PI_CTRL1 0x0574
+#define USB3PHY_QSERDES_RXA_PI_CTRL2 0x0578
+#define USB3PHY_QSERDES_RXA_PI_QUAD 0x057C
+#define USB3PHY_QSERDES_RXA_IDATA1 0x0580
+#define USB3PHY_QSERDES_RXA_IDATA2 0x0584
+#define USB3PHY_QSERDES_RXA_AUX_DATA1 0x0588
+#define USB3PHY_QSERDES_RXA_AUX_DATA2 0x058C
+#define USB3PHY_QSERDES_RXA_AC_JTAG_OUTP 0x0590
+#define USB3PHY_QSERDES_RXA_AC_JTAG_OUTN 0x0594
+#define USB3PHY_QSERDES_RXA_RX_SIGDET 0x0598
+#define USB3PHY_QSERDES_RXA_IDAC_STATUS_I 0x059C
+#define USB3PHY_QSERDES_RXA_IDAC_STATUS_IBAR 0x05A0
+#define USB3PHY_QSERDES_RXA_IDAC_STATUS_Q 0x05A4
+#define USB3PHY_QSERDES_RXA_IDAC_STATUS_QBAR 0x05A8
+#define USB3PHY_QSERDES_RXA_IDAC_STATUS_A 0x05AC
+#define USB3PHY_QSERDES_RXA_IDAC_STATUS_ABAR 0x05B0
+#define USB3PHY_QSERDES_RXA_IDAC_STATUS_SM_ON 0x05B4
+#define USB3PHY_QSERDES_RXA_IDAC_STATUS_CAL_DONE 0x05B8
+#define USB3PHY_QSERDES_RXA_IDAC_STATUS_SIGNERROR 0x05BC
+#define USB3PHY_QSERDES_RXA_READ_EQCODE 0x05C0
+#define USB3PHY_QSERDES_RXA_READ_OFFSETCODE 0x05C4
+#define USB3PHY_QSERDES_RXA_IA_ERROR_COUNTER_LOW 0x05C8
+#define USB3PHY_QSERDES_RXA_IA_ERROR_COUNTER_HIGH 0x05CC
+#define USB3PHY_QSERDES_RXA_VGA_READ_CODE 0x05D0
+#define USB3PHY_QSERDES_RXA_DFE_TAP1_READ_CODE 0x05D4
+#define USB3PHY_QSERDES_RXA_DFE_TAP2_READ_CODE 0x05D8
+#define USB3PHY_QSERDES_RXA_ALOG_OBSV_BUS_STATUS_1 0x05DC
+#define USB3PHY_QSERDES_TXB_BIST_MODE_LANENO 0x0600
+#define USB3PHY_QSERDES_TXB_BIST_INVERT 0x0604
+#define USB3PHY_QSERDES_TXB_CLKBUF_ENABLE 0x0608
+#define USB3PHY_QSERDES_TXB_TX_EMP_POST1_LVL 0x060C
+#define USB3PHY_QSERDES_TXB_TX_POST2_EMPH 0x0610
+#define USB3PHY_QSERDES_TXB_TX_BOOST_LVL_UP_DN 0x0614
+#define USB3PHY_QSERDES_TXB_TX_IDLE_LVL_LARGE_AMP 0x0618
+#define USB3PHY_QSERDES_TXB_TX_DRV_LVL 0x061C
+#define USB3PHY_QSERDES_TXB_TX_DRV_LVL_OFFSET 0x0620
+#define USB3PHY_QSERDES_TXB_RESET_TSYNC_EN 0x0624
+#define USB3PHY_QSERDES_TXB_PRE_STALL_LDO_BOOST_EN 0x0628
+#define USB3PHY_QSERDES_TXB_TX_BAND 0x062C
+#define USB3PHY_QSERDES_TXB_SLEW_CNTL 0x0630
+#define USB3PHY_QSERDES_TXB_INTERFACE_SELECT 0x0634
+#define USB3PHY_QSERDES_TXB_LPB_EN 0x0638
+#define USB3PHY_QSERDES_TXB_RES_CODE_LANE_TX 0x063C
+#define USB3PHY_QSERDES_TXB_RES_CODE_LANE_RX 0x0640
+#define USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x0644
+#define USB3PHY_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0648
+#define USB3PHY_QSERDES_TXB_PERL_LENGTH1 0x064C
+#define USB3PHY_QSERDES_TXB_PERL_LENGTH2 0x0650
+#define USB3PHY_QSERDES_TXB_SERDES_BYP_EN_OUT 0x0654
+#define USB3PHY_QSERDES_TXB_DEBUG_BUS_SEL 0x0658
+#define USB3PHY_QSERDES_TXB_TRANSCEIVER_BIAS_EN 0x065C
+#define USB3PHY_QSERDES_TXB_HIGHZ_DRVR_EN 0x0660
+#define USB3PHY_QSERDES_TXB_TX_POL_INV 0x0664
+#define USB3PHY_QSERDES_TXB_PARRATE_REC_DETECT_IDLE_EN 0x0668
+#define USB3PHY_QSERDES_TXB_BIST_PATTERN1 0x066C
+#define USB3PHY_QSERDES_TXB_BIST_PATTERN2 0x0670
+#define USB3PHY_QSERDES_TXB_BIST_PATTERN3 0x0674
+#define USB3PHY_QSERDES_TXB_BIST_PATTERN4 0x0678
+#define USB3PHY_QSERDES_TXB_BIST_PATTERN5 0x067C
+#define USB3PHY_QSERDES_TXB_BIST_PATTERN6 0x0680
+#define USB3PHY_QSERDES_TXB_BIST_PATTERN7 0x0684
+#define USB3PHY_QSERDES_TXB_BIST_PATTERN8 0x0688
+#define USB3PHY_QSERDES_TXB_LANE_MODE_1 0x068C
+#define USB3PHY_QSERDES_TXB_LANE_MODE_2 0x0690
+#define USB3PHY_QSERDES_TXB_LANE_MODE_3 0x0694
+#define USB3PHY_QSERDES_TXB_ATB_SEL1 0x0698
+#define USB3PHY_QSERDES_TXB_ATB_SEL2 0x069C
+#define USB3PHY_QSERDES_TXB_RCV_DETECT_LVL 0x06A0
+#define USB3PHY_QSERDES_TXB_RCV_DETECT_LVL_2 0x06A4
+#define USB3PHY_QSERDES_TXB_PRBS_SEED1 0x06A8
+#define USB3PHY_QSERDES_TXB_PRBS_SEED2 0x06AC
+#define USB3PHY_QSERDES_TXB_PRBS_SEED3 0x06B0
+#define USB3PHY_QSERDES_TXB_PRBS_SEED4 0x06B4
+#define USB3PHY_QSERDES_TXB_RESET_GEN 0x06B8
+#define USB3PHY_QSERDES_TXB_RESET_GEN_MUXES 0x06BC
+#define USB3PHY_QSERDES_TXB_TRAN_DRVR_EMP_EN 0x06C0
+#define USB3PHY_QSERDES_TXB_TX_INTERFACE_MODE 0x06C4
+#define USB3PHY_QSERDES_TXB_PWM_CTRL 0x06C8
+#define USB3PHY_QSERDES_TXB_PWM_ENCODED_OR_DATA 0x06CC
+#define USB3PHY_QSERDES_TXB_PWM_GEAR_1_DIVIDER_BAND2 0x06D0
+#define USB3PHY_QSERDES_TXB_PWM_GEAR_2_DIVIDER_BAND2 0x06D4
+#define USB3PHY_QSERDES_TXB_PWM_GEAR_3_DIVIDER_BAND2 0x06D8
+#define USB3PHY_QSERDES_TXB_PWM_GEAR_4_DIVIDER_BAND2 0x06DC
+#define USB3PHY_QSERDES_TXB_PWM_GEAR_1_DIVIDER_BAND0_1 0x06E0
+#define USB3PHY_QSERDES_TXB_PWM_GEAR_2_DIVIDER_BAND0_1 0x06E4
+#define USB3PHY_QSERDES_TXB_PWM_GEAR_3_DIVIDER_BAND0_1 0x06E8
+#define USB3PHY_QSERDES_TXB_PWM_GEAR_4_DIVIDER_BAND0_1 0x06EC
+#define USB3PHY_QSERDES_TXB_VMODE_CTRL1 0x06F0
+#define USB3PHY_QSERDES_TXB_ALOG_OBSV_BUS_CTRL_1 0x06F4
+#define USB3PHY_QSERDES_TXB_BIST_STATUS 0x06F8
+#define USB3PHY_QSERDES_TXB_BIST_ERROR_COUNT1 0x06FC
+#define USB3PHY_QSERDES_TXB_BIST_ERROR_COUNT2 0x0700
+#define USB3PHY_QSERDES_TXB_ALOG_OBSV_BUS_STATUS_1 0x0704
+#define USB3PHY_QSERDES_TXB_DIG_BKUP_CTRL 0x0708
+#define USB3PHY_QSERDES_RXB_UCDR_FO_GAIN_HALF 0x0800
+#define USB3PHY_QSERDES_RXB_UCDR_FO_GAIN_QUARTER 0x0804
+#define USB3PHY_QSERDES_RXB_UCDR_FO_GAIN 0x0808
+#define USB3PHY_QSERDES_RXB_UCDR_SO_GAIN_HALF 0x080C
+#define USB3PHY_QSERDES_RXB_UCDR_SO_GAIN_QUARTER 0x0810
+#define USB3PHY_QSERDES_RXB_UCDR_SO_GAIN 0x0814
+#define USB3PHY_QSERDES_RXB_UCDR_SVS_FO_GAIN_HALF 0x0818
+#define USB3PHY_QSERDES_RXB_UCDR_SVS_FO_GAIN_QUARTER 0x081C
+#define USB3PHY_QSERDES_RXB_UCDR_SVS_FO_GAIN 0x0820
+#define USB3PHY_QSERDES_RXB_UCDR_SVS_SO_GAIN_HALF 0x0824
+#define USB3PHY_QSERDES_RXB_UCDR_SVS_SO_GAIN_QUARTER 0x0828
+#define USB3PHY_QSERDES_RXB_UCDR_SVS_SO_GAIN 0x082C
+#define USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x0830
+#define USB3PHY_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x0834
+#define USB3PHY_QSERDES_RXB_UCDR_FO_TO_SO_DELAY 0x0838
+#define USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0x083C
+#define USB3PHY_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0840
+#define USB3PHY_QSERDES_RXB_UCDR_PI_CONTROLS 0x0844
+#define USB3PHY_QSERDES_RXB_UCDR_SB2_THRESH1 0x0848
+#define USB3PHY_QSERDES_RXB_UCDR_SB2_THRESH2 0x084C
+#define USB3PHY_QSERDES_RXB_UCDR_SB2_GAIN1 0x0850
+#define USB3PHY_QSERDES_RXB_UCDR_SB2_GAIN2 0x0854
+#define USB3PHY_QSERDES_RXB_AUX_CONTROL 0x0858
+#define USB3PHY_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0x085C
+#define USB3PHY_QSERDES_RXB_RCLK_AUXDATA_SEL 0x0860
+#define USB3PHY_QSERDES_RXB_AC_JTAG_ENABLE 0x0864
+#define USB3PHY_QSERDES_RXB_AC_JTAG_INITP 0x0868
+#define USB3PHY_QSERDES_RXB_AC_JTAG_INITN 0x086C
+#define USB3PHY_QSERDES_RXB_AC_JTAG_LVL 0x0870
+#define USB3PHY_QSERDES_RXB_AC_JTAG_MODE 0x0874
+#define USB3PHY_QSERDES_RXB_AC_JTAG_RESET 0x0878
+#define USB3PHY_QSERDES_RXB_RX_TERM_BW 0x087C
+#define USB3PHY_QSERDES_RXB_RX_RCVR_IQ_EN 0x0880
+#define USB3PHY_QSERDES_RXB_RX_IDAC_I_DC_OFFSETS 0x0884
+#define USB3PHY_QSERDES_RXB_RX_IDAC_IBAR_DC_OFFSETS 0x0888
+#define USB3PHY_QSERDES_RXB_RX_IDAC_Q_DC_OFFSETS 0x088C
+#define USB3PHY_QSERDES_RXB_RX_IDAC_QBAR_DC_OFFSETS 0x0890
+#define USB3PHY_QSERDES_RXB_RX_IDAC_A_DC_OFFSETS 0x0894
+#define USB3PHY_QSERDES_RXB_RX_IDAC_ABAR_DC_OFFSETS 0x0898
+#define USB3PHY_QSERDES_RXB_RX_IDAC_EN 0x089C
+#define USB3PHY_QSERDES_RXB_RX_IDAC_ENABLES 0x08A0
+#define USB3PHY_QSERDES_RXB_RX_IDAC_SIGN 0x08A4
+#define USB3PHY_QSERDES_RXB_RX_HIGHZ_HIGHRATE 0x08A8
+#define USB3PHY_QSERDES_RXB_RX_TERM_AC_BYPASS_DC_COUPLE_OFFSET 0x08AC
+#define USB3PHY_QSERDES_RXB_DFE_1 0x08B0
+#define USB3PHY_QSERDES_RXB_DFE_2 0x08B4
+#define USB3PHY_QSERDES_RXB_DFE_3 0x08B8
+#define USB3PHY_QSERDES_RXB_VGA_CAL_CNTRL1 0x08BC
+#define USB3PHY_QSERDES_RXB_VGA_CAL_CNTRL2 0x08C0
+#define USB3PHY_QSERDES_RXB_GM_CAL 0x08C4
+#define USB3PHY_QSERDES_RXB_RX_EQ_GAIN2_LSB 0x08C8
+#define USB3PHY_QSERDES_RXB_RX_EQ_GAIN2_MSB 0x08CC
+#define USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL1 0x08D0
+#define USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x08D4
+#define USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x08D8
+#define USB3PHY_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x08DC
+#define USB3PHY_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0x08E0
+#define USB3PHY_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x08E4
+#define USB3PHY_QSERDES_RXB_RX_IDAC_MEASURE_TIME 0x08E8
+#define USB3PHY_QSERDES_RXB_RX_IDAC_ACCUMULATOR 0x08EC
+#define USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_LSB 0x08F0
+#define USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_MSB 0x08F4
+#define USB3PHY_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x08F8
+#define USB3PHY_QSERDES_RXB_RX_OFFSET_ADAPTOR_CNTRL2 0x08FC
+#define USB3PHY_QSERDES_RXB_SIGDET_ENABLES 0x0900
+#define USB3PHY_QSERDES_RXB_SIGDET_CNTRL 0x0904
+#define USB3PHY_QSERDES_RXB_SIGDET_LVL 0x0908
+#define USB3PHY_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x090C
+#define USB3PHY_QSERDES_RXB_RX_BAND 0x0910
+#define USB3PHY_QSERDES_RXB_CDR_FREEZE_UP_DN 0x0914
+#define USB3PHY_QSERDES_RXB_CDR_RESET_OVERRIDE 0x0918
+#define USB3PHY_QSERDES_RXB_RX_INTERFACE_MODE 0x091C
+#define USB3PHY_QSERDES_RXB_JITTER_GEN_MODE 0x0920
+#define USB3PHY_QSERDES_RXB_BUJ_AMP 0x0924
+#define USB3PHY_QSERDES_RXB_SJ_AMP1 0x0928
+#define USB3PHY_QSERDES_RXB_SJ_AMP2 0x092C
+#define USB3PHY_QSERDES_RXB_SJ_PER1 0x0930
+#define USB3PHY_QSERDES_RXB_SJ_PER2 0x0934
+#define USB3PHY_QSERDES_RXB_BUJ_STEP_FREQ1 0x0938
+#define USB3PHY_QSERDES_RXB_BUJ_STEP_FREQ2 0x093C
+#define USB3PHY_QSERDES_RXB_PPM_OFFSET1 0x0940
+#define USB3PHY_QSERDES_RXB_PPM_OFFSET2 0x0944
+#define USB3PHY_QSERDES_RXB_SIGN_PPM_PERIOD1 0x0948
+#define USB3PHY_QSERDES_RXB_SIGN_PPM_PERIOD2 0x094C
+#define USB3PHY_QSERDES_RXB_RX_PWM_ENABLE_AND_DATA 0x0950
+#define USB3PHY_QSERDES_RXB_RX_PWM_GEAR1_TIMEOUT_COUNT 0x0954
+#define USB3PHY_QSERDES_RXB_RX_PWM_GEAR2_TIMEOUT_COUNT 0x0958
+#define USB3PHY_QSERDES_RXB_RX_PWM_GEAR3_TIMEOUT_COUNT 0x095C
+#define USB3PHY_QSERDES_RXB_RX_PWM_GEAR4_TIMEOUT_COUNT 0x0960
+#define USB3PHY_QSERDES_RXB_RX_MODE_00 0x0964
+#define USB3PHY_QSERDES_RXB_RX_MODE_01 0x0968
+#define USB3PHY_QSERDES_RXB_RX_MODE_10 0x096C
+#define USB3PHY_QSERDES_RXB_ALOG_OBSV_BUS_CTRL_1 0x0970
+#define USB3PHY_QSERDES_RXB_PI_CTRL1 0x0974
+#define USB3PHY_QSERDES_RXB_PI_CTRL2 0x0978
+#define USB3PHY_QSERDES_RXB_PI_QUAD 0x097C
+#define USB3PHY_QSERDES_RXB_IDATA1 0x0980
+#define USB3PHY_QSERDES_RXB_IDATA2 0x0984
+#define USB3PHY_QSERDES_RXB_AUX_DATA1 0x0988
+#define USB3PHY_QSERDES_RXB_AUX_DATA2 0x098C
+#define USB3PHY_QSERDES_RXB_AC_JTAG_OUTP 0x0990
+#define USB3PHY_QSERDES_RXB_AC_JTAG_OUTN 0x0994
+#define USB3PHY_QSERDES_RXB_RX_SIGDET 0x0998
+#define USB3PHY_QSERDES_RXB_IDAC_STATUS_I 0x099C
+#define USB3PHY_QSERDES_RXB_IDAC_STATUS_IBAR 0x09A0
+#define USB3PHY_QSERDES_RXB_IDAC_STATUS_Q 0x09A4
+#define USB3PHY_QSERDES_RXB_IDAC_STATUS_QBAR 0x09A8
+#define USB3PHY_QSERDES_RXB_IDAC_STATUS_A 0x09AC
+#define USB3PHY_QSERDES_RXB_IDAC_STATUS_ABAR 0x09B0
+#define USB3PHY_QSERDES_RXB_IDAC_STATUS_SM_ON 0x09B4
+#define USB3PHY_QSERDES_RXB_IDAC_STATUS_CAL_DONE 0x09B8
+#define USB3PHY_QSERDES_RXB_IDAC_STATUS_SIGNERROR 0x09BC
+#define USB3PHY_QSERDES_RXB_READ_EQCODE 0x09C0
+#define USB3PHY_QSERDES_RXB_READ_OFFSETCODE 0x09C4
+#define USB3PHY_QSERDES_RXB_IA_ERROR_COUNTER_LOW 0x09C8
+#define USB3PHY_QSERDES_RXB_IA_ERROR_COUNTER_HIGH 0x09CC
+#define USB3PHY_QSERDES_RXB_VGA_READ_CODE 0x09D0
+#define USB3PHY_QSERDES_RXB_DFE_TAP1_READ_CODE 0x09D4
+#define USB3PHY_QSERDES_RXB_DFE_TAP2_READ_CODE 0x09D8
+#define USB3PHY_QSERDES_RXB_ALOG_OBSV_BUS_STATUS_1 0x09DC
+#define USB3PHY_PCS_MISC_TYPEC_CTRL 0x0A00
+#define USB3PHY_PCS_MISC_TYPEC_STATUS 0x0A04
+#define USB3PHY_PCS_MISC_DEBUG_BUS_BYTE0_INDEX 0x0A08
+#define USB3PHY_PCS_MISC_DEBUG_BUS_BYTE1_INDEX 0x0A0C
+#define USB3PHY_PCS_MISC_DEBUG_BUS_BYTE2_INDEX 0x0A10
+#define USB3PHY_PCS_MISC_DEBUG_BUS_BYTE3_INDEX 0x0A14
+#define USB3PHY_PCS_MISC_PLACEHOLDER_STATUS 0x0A18
+#define USB3PHY_PCS_MISC_DEBUG_BUS_0_STATUS 0x0A1C
+#define USB3PHY_PCS_MISC_DEBUG_BUS_1_STATUS 0x0A20
+#define USB3PHY_PCS_MISC_DEBUG_BUS_2_STATUS 0x0A24
+#define USB3PHY_PCS_MISC_DEBUG_BUS_3_STATUS 0x0A28
+#define USB3PHY_PCS_MISC_BIST_CTRL 0x0A2C
+#define USB3PHY_PCS_SW_RESET 0x0C00
+#define USB3PHY_PCS_POWER_DOWN_CONTROL 0x0C04
+#define USB3PHY_PCS_START_CONTROL 0x0C08
+#define USB3PHY_PCS_TXMGN_V0 0x0C0C
+#define USB3PHY_PCS_TXMGN_V1 0x0C10
+#define USB3PHY_PCS_TXMGN_V2 0x0C14
+#define USB3PHY_PCS_TXMGN_V3 0x0C18
+#define USB3PHY_PCS_TXMGN_V4 0x0C1C
+#define USB3PHY_PCS_TXMGN_LS 0x0C20
+#define USB3PHY_PCS_TXDEEMPH_M6DB_V0 0x0C24
+#define USB3PHY_PCS_TXDEEMPH_M3P5DB_V0 0x0C28
+#define USB3PHY_PCS_TXDEEMPH_M6DB_V1 0x0C2C
+#define USB3PHY_PCS_TXDEEMPH_M3P5DB_V1 0x0C30
+#define USB3PHY_PCS_TXDEEMPH_M6DB_V2 0x0C34
+#define USB3PHY_PCS_TXDEEMPH_M3P5DB_V2 0x0C38
+#define USB3PHY_PCS_TXDEEMPH_M6DB_V3 0x0C3C
+#define USB3PHY_PCS_TXDEEMPH_M3P5DB_V3 0x0C40
+#define USB3PHY_PCS_TXDEEMPH_M6DB_V4 0x0C44
+#define USB3PHY_PCS_TXDEEMPH_M3P5DB_V4 0x0C48
+#define USB3PHY_PCS_TXDEEMPH_M6DB_LS 0x0C4C
+#define USB3PHY_PCS_TXDEEMPH_M3P5DB_LS 0x0C50
+#define USB3PHY_PCS_ENDPOINT_REFCLK_DRIVE 0x0C54
+#define USB3PHY_PCS_RX_IDLE_DTCT_CNTRL 0x0C58
+#define USB3PHY_PCS_RATE_SLEW_CNTRL 0x0C5C
+#define USB3PHY_PCS_POWER_STATE_CONFIG1 0x0C60
+#define USB3PHY_PCS_POWER_STATE_CONFIG2 0x0C64
+#define USB3PHY_PCS_POWER_STATE_CONFIG3 0x0C68
+#define USB3PHY_PCS_POWER_STATE_CONFIG4 0x0C6C
+#define USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_L 0x0C70
+#define USB3PHY_PCS_RCVR_DTCT_DLY_P1U2_H 0x0C74
+#define USB3PHY_PCS_RCVR_DTCT_DLY_U3_L 0x0C78
+#define USB3PHY_PCS_RCVR_DTCT_DLY_U3_H 0x0C7C
+#define USB3PHY_PCS_LOCK_DETECT_CONFIG1 0x0C80
+#define USB3PHY_PCS_LOCK_DETECT_CONFIG2 0x0C84
+#define USB3PHY_PCS_LOCK_DETECT_CONFIG3 0x0C88
+#define USB3PHY_PCS_TSYNC_RSYNC_TIME 0x0C8C
+#define USB3PHY_PCS_SIGDET_LOW_2_IDLE_TIME 0x0C90
+#define USB3PHY_PCS_BEACON_2_IDLE_TIME_L 0x0C94
+#define USB3PHY_PCS_BEACON_2_IDLE_TIME_H 0x0C98
+#define USB3PHY_PCS_PWRUP_RESET_DLY_TIME_SYSCLK 0x0C9C
+#define USB3PHY_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0CA0
+#define USB3PHY_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0CA4
+#define USB3PHY_PCS_PLL_LOCK_CHK_DLY_TIME 0x0CA8
+#define USB3PHY_PCS_LFPS_DET_HIGH_COUNT_VAL 0x0CAC
+#define USB3PHY_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0CB0
+#define USB3PHY_PCS_LFPS_TX_END_CNT_P2U3_START 0x0CB4
+#define USB3PHY_PCS_RXEQTRAINING_WAIT_TIME 0x0CB8
+#define USB3PHY_PCS_RXEQTRAINING_RUN_TIME 0x0CBC
+#define USB3PHY_PCS_TXONESZEROS_RUN_LENGTH 0x0CC0
+#define USB3PHY_PCS_FLL_CNTRL1 0x0CC4
+#define USB3PHY_PCS_FLL_CNTRL2 0x0CC8
+#define USB3PHY_PCS_FLL_CNT_VAL_L 0x0CCC
+#define USB3PHY_PCS_FLL_CNT_VAL_H_TOL 0x0CD0
+#define USB3PHY_PCS_FLL_MAN_CODE 0x0CD4
+#define USB3PHY_PCS_AUTONOMOUS_MODE_CTRL 0x0CD8
+#define USB3PHY_PCS_LFPS_RXTERM_IRQ_CLEAR 0x0CDC
+#define USB3PHY_PCS_ARCVR_DTCT_EN_PERIOD 0x0CE0
+#define USB3PHY_PCS_ARCVR_DTCT_CM_DLY 0x0CE4
+#define USB3PHY_PCS_ALFPS_DEGLITCH_VAL 0x0CE8
+#define USB3PHY_PCS_INSIG_SW_CTRL1 0x0CEC
+#define USB3PHY_PCS_INSIG_SW_CTRL2 0x0CF0
+#define USB3PHY_PCS_INSIG_SW_CTRL3 0x0CF4
+#define USB3PHY_PCS_INSIG_MX_CTRL1 0x0CF8
+#define USB3PHY_PCS_INSIG_MX_CTRL2 0x0CFC
+#define USB3PHY_PCS_INSIG_MX_CTRL3 0x0D00
+#define USB3PHY_PCS_OUTSIG_SW_CTRL1 0x0D04
+#define USB3PHY_PCS_OUTSIG_MX_CTRL1 0x0D08
+#define USB3PHY_PCS_CLK_DEBUG_BYPASS_CTRL 0x0D0C
+#define USB3PHY_PCS_TEST_CONTROL 0x0D10
+#define USB3PHY_PCS_TEST_CONTROL2 0x0D14
+#define USB3PHY_PCS_TEST_CONTROL3 0x0D18
+#define USB3PHY_PCS_TEST_CONTROL4 0x0D1C
+#define USB3PHY_PCS_TEST_CONTROL5 0x0D20
+#define USB3PHY_PCS_TEST_CONTROL6 0x0D24
+#define USB3PHY_PCS_TEST_CONTROL7 0x0D28
+#define USB3PHY_PCS_COM_RESET_CONTROL 0x0D2C
+#define USB3PHY_PCS_BIST_CTRL 0x0D30
+#define USB3PHY_PCS_PRBS_POLY0 0x0D34
+#define USB3PHY_PCS_PRBS_POLY1 0x0D38
+#define USB3PHY_PCS_PRBS_SEED0 0x0D3C
+#define USB3PHY_PCS_PRBS_SEED1 0x0D40
+#define USB3PHY_PCS_FIXED_PAT_CTRL 0x0D44
+#define USB3PHY_PCS_FIXED_PAT0 0x0D48
+#define USB3PHY_PCS_FIXED_PAT1 0x0D4C
+#define USB3PHY_PCS_FIXED_PAT2 0x0D50
+#define USB3PHY_PCS_FIXED_PAT3 0x0D54
+#define USB3PHY_PCS_COM_CLK_SWITCH_CTRL 0x0D58
+#define USB3PHY_PCS_ELECIDLE_DLY_SEL 0x0D5C
+#define USB3PHY_PCS_SPARE1 0x0D60
+#define USB3PHY_PCS_BIST_CHK_ERR_CNT_L_STATUS 0x0D64
+#define USB3PHY_PCS_BIST_CHK_ERR_CNT_H_STATUS 0x0D68
+#define USB3PHY_PCS_BIST_CHK_STATUS 0x0D6C
+#define USB3PHY_PCS_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x0D70
+#define USB3PHY_PCS_PCS_STATUS 0x0D74
+#define USB3PHY_PCS_PCS_STATUS2 0x0D78
+#define USB3PHY_PCS_PCS_STATUS3 0x0D7C
+#define USB3PHY_PCS_COM_RESET_STATUS 0x0D80
+#define USB3PHY_PCS_OSC_DTCT_STATUS 0x0D84
+#define USB3PHY_PCS_REVISION_ID0 0x0D88
+#define USB3PHY_PCS_REVISION_ID1 0x0D8C
+#define USB3PHY_PCS_REVISION_ID2 0x0D90
+#define USB3PHY_PCS_REVISION_ID3 0x0D94
+#define USB3PHY_PCS_DEBUG_BUS_0_STATUS 0x0D98
+#define USB3PHY_PCS_DEBUG_BUS_1_STATUS 0x0D9C
+#define USB3PHY_PCS_DEBUG_BUS_2_STATUS 0x0DA0
+#define USB3PHY_PCS_DEBUG_BUS_3_STATUS 0x0DA4
+#define USB3PHY_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x0DA8
+#define USB3PHY_PCS_OSC_DTCT_ACTIONS 0x0DAC
+#define USB3PHY_PCS_SIGDET_CNTRL 0x0DB0
+#define USB3PHY_PCS_IDAC_CAL_CNTRL 0x0DB4
+#define USB3PHY_PCS_CMN_ACK_OUT_SEL 0x0DB8
+#define USB3PHY_PCS_PLL_LOCK_CHK_DLY_TIME_SYSCLK 0x0DBC
+#define USB3PHY_PCS_AUTONOMOUS_MODE_STATUS 0x0DC0
+#define USB3PHY_PCS_ENDPOINT_REFCLK_CNTRL 0x0DC4
+#define USB3PHY_PCS_EPCLK_PRE_PLL_LOCK_DLY_SYSCLK 0x0DC8
+#define USB3PHY_PCS_EPCLK_PRE_PLL_LOCK_DLY_AUXCLK 0x0DCC
+#define USB3PHY_PCS_EPCLK_DLY_COUNT_VAL_L 0x0DD0
+#define USB3PHY_PCS_EPCLK_DLY_COUNT_VAL_H 0x0DD4
+#define USB3PHY_PCS_RX_SIGDET_LVL 0x0DD8
+#define USB3PHY_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x0DDC
+#define USB3PHY_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x0DE0
+#define USB3PHY_PCS_AUTONOMOUS_MODE_CTRL2 0x0DE4
+#define USB3PHY_PCS_RXTERMINATION_DLY_SEL 0x0DE8
+#define USB3PHY_PCS_LFPS_PER_TIMER_VAL 0x0DEC
+#define USB3PHY_PCS_SIGDET_STARTUP_TIMER_VAL 0x0DF0
+#define USB3PHY_PCS_LOCK_DETECT_CONFIG4 0x0DF4
+#define USB3PHY_PCS_RX_SIGDET_DTCT_CNTRL 0x0DF8
+#define USB3PHY_PCS_PCS_STATUS4 0x0DFC
+#define USB3PHY_PCS_PCS_STATUS4_CLEAR 0x0E00
+#define USB3PHY_PCS_DEC_ERROR_COUNT_STATUS 0x0E04
+#define USB3PHY_PCS_COMMA_POS_STATUS 0x0E08
+#define USB3PHY_PCS_REFGEN_REQ_CONFIG1 0x0E0C
+#define USB3PHY_PCS_REFGEN_REQ_CONFIG2 0x0E10
+#define USB3PHY_PCS_REFGEN_REQ_CONFIG3 0x0E14
+
+#endif /* _DT_BINDINGS_PHY_QCOM_11NM_QMP_COMBO_USB_H */
diff --git a/include/linux/android_vendor.h b/include/linux/android_vendor.h
index c0d3abb..59fc573 100644
--- a/include/linux/android_vendor.h
+++ b/include/linux/android_vendor.h
@@ -29,4 +29,7 @@
#define ANDROID_VENDOR_DATA(n) u64 android_vendor_data##n
#define ANDROID_VENDOR_DATA_ARRAY(n, s) u64 android_vendor_data##n[s]
+#define ANDROID_OEM_DATA(n) u64 android_oem_data##n
+#define ANDROID_OEM_DATA_ARRAY(n, s) u64 android_oem_data##n[s]
+
#endif /* _ANDROID_VENDOR_H */
diff --git a/include/linux/ipa.h b/include/linux/ipa.h
index ff0d3d8..0dd2de9 100644
--- a/include/linux/ipa.h
+++ b/include/linux/ipa.h
@@ -1412,6 +1412,7 @@ int ipa_put_rt_tbl(u32 rt_tbl_hdl);
int ipa_register_intf(const char *name,
const struct ipa_tx_intf *tx,
const struct ipa_rx_intf *rx);
+int ipa_deregister_intf(const char *name);
/*
* Aggregation
@@ -1586,7 +1587,11 @@ int ipa_enable_wdi_pipe(u32 clnt_hdl);
int ipa_disable_wdi_pipe(u32 clnt_hdl);
int ipa_resume_wdi_pipe(u32 clnt_hdl);
int ipa_suspend_wdi_pipe(u32 clnt_hdl);
-
+int ipa_reg_uc_rdyCB(struct ipa_wdi_uc_ready_params *param);
+int ipa_dereg_uc_rdyCB(void);
+int ipa_add_hdr(struct ipa_ioc_add_hdr *hdrs);
+int ipa_del_hdr(struct ipa_ioc_del_hdr *hdls);
+int ipa_get_hdr(struct ipa_ioc_get_hdr *lookup);
/**
* ipa_get_wdi_stats() - Query WDI statistics from uc
* @stats: [inout] stats blob from client populated by driver
@@ -2338,26 +2343,6 @@ static inline int ipa_disable_apps_wan_cons_deaggr(
return -EPERM;
}
-static inline int ipa_add_hdr(struct ipa_ioc_add_hdr *hdrs)
-{
- return -EPERM;
-}
-
-static inline int ipa_del_hdr(struct ipa_ioc_del_hdr *hdls)
-{
- return -EPERM;
-}
-
-static inline int ipa_get_hdr(struct ipa_ioc_get_hdr *lookup)
-{
- return -EPERM;
-}
-
-static inline int ipa_deregister_intf(const char *name)
-{
- return -EPERM;
-}
-
static inline int ipa_uc_dereg_rdyCB(void)
{
return -EPERM;
diff --git a/include/linux/ipa_fmwk.h b/include/linux/ipa_fmwk.h
index bc987d1..0fd1b36 100644
--- a/include/linux/ipa_fmwk.h
+++ b/include/linux/ipa_fmwk.h
@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
- * Copyright (c) 2018 - 2020, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2018 - 2021, The Linux Foundation. All rights reserved.
*/
#ifndef _IPA_FMWK_H_
@@ -108,6 +108,20 @@ struct ipa_core_data {
int (*ipa_unregister_rmnet_ctl_cb)(void);
int (*ipa_get_default_aggr_time_limit)(enum ipa_client_type client,
u32 *default_aggr_time_limit);
+ int (*ipa_add_hdr)(struct ipa_ioc_add_hdr *hdrs);
+ int (*ipa_del_hdr)(struct ipa_ioc_del_hdr *hdls);
+ int (*ipa_get_hdr)(struct ipa_ioc_get_hdr *lookup);
+ int (*ipa_deregister_intf)(const char *name);
+
+ int (*ipa_enable_wdi_pipe)(u32 clnt_hdl);
+ int (*ipa_disable_wdi_pipe)(u32 clnt_hdl);
+ int (*ipa_resume_wdi_pipe)(u32 clnt_hdl);
+ int (*ipa_suspend_wdi_pipe)(u32 clnt_hdl);
+ int (*ipa_connect_wdi_pipe)(struct ipa_wdi_in_params *in,
+ struct ipa_wdi_out_params *out);
+ int (*ipa_disconnect_wdi_pipe)(u32 clnt_hdl);
+ int (*ipa_uc_reg_rdyCB)(struct ipa_wdi_uc_ready_params *param);
+ int (*ipa_uc_dereg_rdyCB)(void);
};
struct ipa_usb_data {
diff --git a/include/linux/usb/xhci-sec.h b/include/linux/usb/xhci-sec.h
index 5f4c3b1..0014aee 100644
--- a/include/linux/usb/xhci-sec.h
+++ b/include/linux/usb/xhci-sec.h
@@ -2,7 +2,7 @@
/*
* xHCI secondary ring APIs
*
- * Copyright (c) 2019, The Linux Foundation. All rights reserved.
+ * Copyright (c) 2019,2021 The Linux Foundation. All rights reserved.
*/
#ifndef __LINUX_XHCI_SEC_H
@@ -20,7 +20,7 @@ phys_addr_t xhci_get_xfer_ring_phys_addr(struct usb_device *udev,
int xhci_stop_endpoint(struct usb_device *udev, struct usb_host_endpoint *ep);
#else
static inline int xhci_sec_event_ring_setup(struct usb_device *udev,
- unsigned int intr_num);
+ unsigned int intr_num)
{
return -ENODEV;
}
@@ -35,13 +35,13 @@ static inline phys_addr_t xhci_get_sec_event_ring_phys_addr(
struct usb_device *udev, unsigned int intr_num,
dma_addr_t *dma)
{
- return NULL;
+ return 0;
}
static inline phys_addr_t xhci_get_xfer_ring_phys_addr(struct usb_device *udev,
struct usb_host_endpoint *ep, dma_addr_t *dma)
{
- return NULL;
+ return 0;
}
static inline int xhci_stop_endpoint(struct usb_device *udev,
diff --git a/include/net/cnss2.h b/include/net/cnss2.h
index 8758feb..cf05c0b 100644
--- a/include/net/cnss2.h
+++ b/include/net/cnss2.h
@@ -239,4 +239,7 @@ extern int cnss_athdiag_write(struct device *dev, uint32_t offset,
uint8_t *input);
extern int cnss_set_fw_log_mode(struct device *dev, uint8_t fw_log_mode);
extern int cnss_set_pcie_gen_speed(struct device *dev, u8 pcie_gen_speed);
+extern int cnss_pci_get_reg_dump(struct device *dev, uint8_t *buffer,
+ uint32_t len);
+
#endif /* _NET_CNSS2_H */
diff --git a/include/trace/hooks/restricted_preemptirq.h b/include/trace/hooks/restricted_preemptirq.h
index 238c3e6..7af3a67 100644
--- a/include/trace/hooks/restricted_preemptirq.h
+++ b/include/trace/hooks/restricted_preemptirq.h
@@ -2,20 +2,18 @@
/*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
-#if !defined(_TRACE_RESTRICTED_PREEMPTIRQ_H) || defined(TRACE_HEADER_MULTI_READ)
-#define _TRACE_RESTRICTED_PREEMPTIRQ_H
-
-#ifdef CONFIG_PREEMPTIRQ_TRACEPOINTS
-
#undef TRACE_SYSTEM
#define TRACE_SYSTEM restricted_preemptirq
-
#undef TRACE_INCLUDE_PATH
#define TRACE_INCLUDE_PATH trace/hooks
-
+#if !defined(_TRACE_RESTRICTED_PREEMPTIRQ_H) || defined(TRACE_HEADER_MULTI_READ)
+#define _TRACE_RESTRICTED_PREEMPTIRQ_H
#include <linux/tracepoint.h>
#include <trace/hooks/vendor_hooks.h>
+#if defined(CONFIG_PREEMPTIRQ_TRACEPOINTS) && \
+ defined(CONFIG_ANDROID_VENDOR_HOOKS)
+
#ifdef CONFIG_TRACE_IRQFLAGS
DECLARE_RESTRICTED_HOOK(restricted_irq_disable,
TP_PROTO(unsigned long ip, unsigned long parent_ip),
@@ -28,6 +26,8 @@ DECLARE_RESTRICTED_HOOK(restricted_irq_enable,
#else
#define trace_restricted_irq_enable(ip, parent_ip)
#define trace_restricted_irq_disable(ip, parent_ip)
+#define register_trace_restricted_irq_enable(...)
+#define register_trace_restricted_irq_disable(...)
#endif /* CONFIG_TRACE_IRQFLAGS */
#ifdef CONFIG_TRACE_PREEMPT_TOGGLE
@@ -42,15 +42,20 @@ DECLARE_RESTRICTED_HOOK(restricted_preempt_enable,
#else
#define trace_restricted_preempt_enable(ip, parent_ip)
#define trace_restricted_preempt_disable(ip, parent_ip)
+#define register_trace_restricted_preempt_enable(...)
+#define register_trace_restricted_preempt_disable(...)
#endif /* CONFIG_TRACE_PREEMPT_TOGGLE */
-#include <trace/define_trace.h>
-
-#else /* ! CONFIG_PREEMPTIRQ_TRACEPOINTS */
+#else /* CONFIG_PREEMPTIRQ_TRACEPOINTS && CONFIG_ANDROID_VENDOR_HOOKS */
#define trace_restricted_irq_enable(...)
#define trace_restricted_irq_disable(...)
+#define register_trace_restricted_irq_enable(...)
+#define register_trace_restricted_irq_disable(...)
#define trace_restricted_preempt_enable(...)
#define trace_restricted_preempt_disable(...)
-#endif /* ! CONFIG_PREEMPTIRQ_TRACEPOINTS */
+#define register_trace_restricted_preempt_enable(...)
+#define register_trace_restricted_preempt_disable(...)
+#endif /* CONFIG_PREEMPTIRQ_TRACEPOINTS && CONFIG_ANDROID_VENDOR_HOOKS */
#endif /* TRACE_RESTRICTED_PREEMPTIRQ_H || TRACE_HEADER_MULTI_READ */
+#include <trace/define_trace.h>
diff --git a/include/trace/hooks/sched.h b/include/trace/hooks/sched.h
index 4e2be4d..ed5b113 100644
--- a/include/trace/hooks/sched.h
+++ b/include/trace/hooks/sched.h
@@ -10,7 +10,6 @@
* Following tracepoints are not exported in tracefs and provide a
* mechanism for vendor modules to hook and extend functionality
*/
-#if defined(CONFIG_TRACEPOINTS) && defined(CONFIG_ANDROID_VENDOR_HOOKS)
struct task_struct;
DECLARE_RESTRICTED_HOOK(android_rvh_select_task_rq_fair,
TP_PROTO(struct task_struct *p, int prev_cpu, int sd_flag, int wake_flags, int *new_cpu),
@@ -70,22 +69,21 @@ struct sched_group;
DECLARE_RESTRICTED_HOOK(android_rvh_find_busiest_group,
TP_PROTO(struct sched_group *busiest, struct rq *dst_rq, int *out_balance),
TP_ARGS(busiest, dst_rq, out_balance), 1);
-#else
-#define trace_android_rvh_select_task_rq_fair(p, prev_cpu, sd_flag, wake_flags, new_cpu)
-#define trace_android_rvh_select_task_rq_rt(p, prev_cpu, sd_flag, wake_flags, new_cpu)
-#define trace_android_rvh_select_fallback_rq(cpu, p, dest_cpu)
-#define trace_android_vh_scheduler_tick(rq)
-#define trace_android_rvh_enqueue_task(rq, p)
-#define trace_android_rvh_dequeue_task(rq, p)
-#define trace_android_rvh_can_migrate_task(p, dst_cpu, can_migrate)
-#define trace_android_rvh_find_lowest_rq(p, local_cpu_mask, lowest_cpu)
-#define trace_android_rvh_prepare_prio_fork(p)
-#define trace_android_rvh_finish_prio_fork(p)
-#define trace_android_rvh_rtmutex_prepare_setprio(p, pi_task)
-#define trace_android_rvh_set_user_nice(p, nice)
-#define trace_android_rvh_setscheduler(p)
-#define trace_android_rvh_find_busiest_group(busiest, dst_rq, out_balance)
-#endif
+
+DECLARE_HOOK(android_vh_map_util_freq,
+ TP_PROTO(unsigned long util, unsigned long freq,
+ unsigned long cap, unsigned long *next_freq),
+ TP_ARGS(util, freq, cap, next_freq));
+
+struct em_perf_domain;
+DECLARE_HOOK(android_vh_em_pd_energy,
+ TP_PROTO(struct em_perf_domain *pd,
+ unsigned long max_util, unsigned long sum_util,
+ unsigned long *energy),
+ TP_ARGS(pd, max_util, sum_util, energy));
+
+/* macro versions of hooks are no longer required */
+
#endif /* _TRACE_HOOK_SCHED_H */
/* This part must be outside protection */
#include <trace/define_trace.h>
diff --git a/include/trace/hooks/vendor_hooks.h b/include/trace/hooks/vendor_hooks.h
index 8a3fdb9..eea8819 100644
--- a/include/trace/hooks/vendor_hooks.h
+++ b/include/trace/hooks/vendor_hooks.h
@@ -9,6 +9,8 @@
#include <linux/tracepoint.h>
+#if defined(CONFIG_TRACEPOINTS) && defined(CONFIG_ANDROID_VENDOR_HOOKS)
+
#define DECLARE_HOOK DECLARE_TRACE
#ifdef TRACE_HEADER_MULTI_READ
@@ -74,3 +76,10 @@
PARAMS(__data, args))
#endif /* TRACE_HEADER_MULTI_READ */
+
+#else /* !CONFIG_TRACEPOINTS || !CONFIG_ANDROID_VENDOR_HOOKS */
+/* suppress trace hooks */
+#define DECLARE_HOOK DECLARE_EVENT_NOP
+#define DECLARE_RESTRICTED_HOOK(name, proto, args, cond) \
+ DECLARE_EVENT_NOP(name, PARAMS(proto), PARAMS(args))
+#endif
diff --git a/kernel/futex.c b/kernel/futex.c
index d3867d6..0f0afad 100644
--- a/kernel/futex.c
+++ b/kernel/futex.c
@@ -881,8 +881,9 @@ static void put_pi_state(struct futex_pi_state *pi_state)
*/
if (pi_state->owner) {
struct task_struct *owner;
+ unsigned long flags;
- raw_spin_lock_irq(&pi_state->pi_mutex.wait_lock);
+ raw_spin_lock_irqsave(&pi_state->pi_mutex.wait_lock, flags);
owner = pi_state->owner;
if (owner) {
raw_spin_lock(&owner->pi_lock);
@@ -890,7 +891,7 @@ static void put_pi_state(struct futex_pi_state *pi_state)
raw_spin_unlock(&owner->pi_lock);
}
rt_mutex_proxy_unlock(&pi_state->pi_mutex, owner);
- raw_spin_unlock_irq(&pi_state->pi_mutex.wait_lock);
+ raw_spin_unlock_irqrestore(&pi_state->pi_mutex.wait_lock, flags);
}
if (current->pi_state_cache) {
@@ -1595,8 +1596,10 @@ static int wake_futex_pi(u32 __user *uaddr, u32 uval, struct futex_pi_state *pi_
*/
newval = FUTEX_WAITERS | task_pid_vnr(new_owner);
- if (unlikely(should_fail_futex(true)))
+ if (unlikely(should_fail_futex(true))) {
ret = -EFAULT;
+ goto out_unlock;
+ }
ret = cmpxchg_futex_value_locked(&curval, uaddr, uval, newval);
if (!ret && (curval != uval)) {
@@ -2513,10 +2516,22 @@ static int fixup_pi_state_owner(u32 __user *uaddr, struct futex_q *q,
}
/*
- * Since we just failed the trylock; there must be an owner.
+ * The trylock just failed, so either there is an owner or
+ * there is a higher priority waiter than this one.
*/
newowner = rt_mutex_owner(&pi_state->pi_mutex);
- BUG_ON(!newowner);
+ /*
+ * If the higher priority waiter has not yet taken over the
+ * rtmutex then newowner is NULL. We can't return here with
+ * that state because it's inconsistent vs. the user space
+ * state. So drop the locks and try again. It's a valid
+ * situation and not any different from the other retry
+ * conditions.
+ */
+ if (unlikely(!newowner)) {
+ err = -EAGAIN;
+ goto handle_err;
+ }
} else {
WARN_ON_ONCE(argowner != current);
if (oldowner == current) {
diff --git a/kernel/sched/cpufreq_schedutil.c b/kernel/sched/cpufreq_schedutil.c
index 10c4905..9c0a2c7 100644
--- a/kernel/sched/cpufreq_schedutil.c
+++ b/kernel/sched/cpufreq_schedutil.c
@@ -13,6 +13,7 @@
#include <linux/sched/cpufreq.h>
#include <trace/events/power.h>
#include <linux/sched/sysctl.h>
+#include <trace/hooks/sched.h>
#define IOWAIT_BOOST_MIN (SCHED_CAPACITY_SCALE / 8)
@@ -295,10 +296,15 @@ static unsigned int get_next_freq(struct sugov_policy *sg_policy,
struct cpufreq_policy *policy = sg_policy->policy;
unsigned int freq = arch_scale_freq_invariant() ?
policy->cpuinfo.max_freq : policy->cur;
+ unsigned long next_freq = 0;
- freq = map_util_freq(util, freq, max);
+ trace_android_vh_map_util_freq(util, freq, max, &next_freq);
+ if (next_freq)
+ freq = next_freq;
+ else
+ freq = map_util_freq(util, freq, max);
+
trace_sugov_next_freq(policy->cpu, util, max, freq);
-
if (freq == sg_policy->cached_raw_freq && !sg_policy->need_freq_update)
return sg_policy->next_freq;
diff --git a/kernel/sched/fair.c b/kernel/sched/fair.c
index fe27a7f..949475d 100644
--- a/kernel/sched/fair.c
+++ b/kernel/sched/fair.c
@@ -6903,6 +6903,7 @@ compute_energy(struct task_struct *p, int dst_cpu, struct perf_domain *pd)
unsigned long cpu_cap = arch_scale_cpu_capacity(cpumask_first(pd_mask));
#endif
unsigned long max_util = 0, sum_util = 0;
+ unsigned long energy = 0;
int cpu;
unsigned long cpu_util;
@@ -6945,7 +6946,11 @@ compute_energy(struct task_struct *p, int dst_cpu, struct perf_domain *pd)
max_util = max(max_util, cpu_util);
}
- return em_pd_energy(pd->em_pd, max_util, sum_util);
+ trace_android_vh_em_pd_energy(pd->em_pd, max_util, sum_util, &energy);
+ if (!energy)
+ energy = em_pd_energy(pd->em_pd, max_util, sum_util);
+
+ return energy;
}
#ifdef CONFIG_SCHED_WALT
diff --git a/kernel/trace/preemptirq_long.c b/kernel/trace/preemptirq_long.c
index e7c02b4..54e55f6 100644
--- a/kernel/trace/preemptirq_long.c
+++ b/kernel/trace/preemptirq_long.c
@@ -29,7 +29,8 @@ static unsigned int one_million = 1000000;
static DEFINE_PER_CPU(u64, irq_disabled_ts);
static DEFINE_PER_CPU(u64, preempt_disabled_ts);
-static void note_irq_disable(void *u1, unsigned long u2, unsigned long u3)
+static void __attribute__((__unused__))
+ note_irq_disable(void *u1, unsigned long u2, unsigned long u3)
{
if (is_idle_task(current))
return;
@@ -41,7 +42,8 @@ static void note_irq_disable(void *u1, unsigned long u2, unsigned long u3)
this_cpu_write(irq_disabled_ts, sched_clock());
}
-static void test_irq_disable_long(void *u1, unsigned long u2, unsigned long u3)
+static void __attribute__((__unused__))
+ test_irq_disable_long(void *u1, unsigned long u2, unsigned long u3)
{
u64 ts = this_cpu_read(irq_disabled_ts);
@@ -69,12 +71,14 @@ static void test_irq_disable_long(void *u1, unsigned long u2, unsigned long u3)
}
}
-static void note_preempt_disable(void *u1, unsigned long u2, unsigned long u3)
+static void __attribute__((__unused__))
+ note_preempt_disable(void *u1, unsigned long u2, unsigned long u3)
{
this_cpu_write(preempt_disabled_ts, sched_clock());
}
-static void test_preempt_disable_long(void *u1, unsigned long u2,
+static void __attribute__((__unused__))
+ test_preempt_disable_long(void *u1, unsigned long u2,
unsigned long u3)
{
u64 ts = this_cpu_read(preempt_disabled_ts);