Merge tag 'omap-devel-am33xx-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc
From Tony Lindgren:
From Paul Walmsley <paul@pwsan.com>:
AM33xx hwmod data and miscellaneous clock and hwmod fixes. AM33xx
should now boot on mainline after this is applied, according to
Vaibhav.
(The shortlog makes no sense here since it contains mostly the dependent
cleanups that are part of the preceding branches).
Signed-off-by: Olof Johansson <olof@lixom.net>
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt
index 1c044eb..343781b 100644
--- a/Documentation/devicetree/bindings/arm/pmu.txt
+++ b/Documentation/devicetree/bindings/arm/pmu.txt
@@ -7,8 +7,12 @@
Required properties:
- compatible : should be one of
+ "arm,cortex-a15-pmu"
"arm,cortex-a9-pmu"
"arm,cortex-a8-pmu"
+ "arm,cortex-a7-pmu"
+ "arm,cortex-a5-pmu"
+ "arm,arm11mpcore-pmu"
"arm,arm1176-pmu"
"arm,arm1136-pmu"
- interrupts : 1 combined interrupt or 1 per core.
diff --git a/MAINTAINERS b/MAINTAINERS
index fdc0119..437a7dd 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -595,7 +595,6 @@
S: Maintained
F: arch/arm/kernel/perf_event*
F: arch/arm/oprofile/common.c
-F: arch/arm/kernel/pmu.c
F: arch/arm/include/asm/pmu.h
F: arch/arm/kernel/hw_breakpoint.c
F: arch/arm/include/asm/hw_breakpoint.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 2f88d8d..e5a4438 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -686,6 +686,7 @@
select NEED_MACH_IO_H if PCI
select ARCH_HAS_CPUFREQ
select USE_OF
+ select COMMON_CLK
help
This enables support for NVIDIA Tegra based systems (Tegra APX,
Tegra 6xx and Tegra 2 series).
@@ -1179,12 +1180,6 @@
depends on CPU_XSCALE
default y
-config CPU_HAS_PMU
- depends on (CPU_V6 || CPU_V6K || CPU_V7 || XSCALE_PMU) && \
- (!ARCH_OMAP3 || OMAP3_EMU)
- default y
- bool
-
config MULTI_IRQ_HANDLER
bool
help
@@ -1757,7 +1752,7 @@
config HW_PERF_EVENTS
bool "Enable hardware performance counter support for perf events"
- depends on PERF_EVENTS && CPU_HAS_PMU
+ depends on PERF_EVENTS
default y
help
Enable hardware performance counter support for perf events. If
diff --git a/arch/arm/configs/kzm9d_defconfig b/arch/arm/configs/kzm9d_defconfig
index 26146ff..8c49df6 100644
--- a/arch/arm/configs/kzm9d_defconfig
+++ b/arch/arm/configs/kzm9d_defconfig
@@ -8,6 +8,7 @@
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
# CONFIG_BLK_DEV_BSG is not set
# CONFIG_IOSCHED_DEADLINE is not set
diff --git a/arch/arm/configs/kzm9g_defconfig b/arch/arm/configs/kzm9g_defconfig
index 2388c86..5d0c6670 100644
--- a/arch/arm/configs/kzm9g_defconfig
+++ b/arch/arm/configs/kzm9g_defconfig
@@ -14,6 +14,7 @@
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
CONFIG_SYSCTL_SYSCALL=y
CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
CONFIG_SLAB=y
CONFIG_MODULES=y
CONFIG_MODULE_FORCE_LOAD=y
diff --git a/arch/arm/include/asm/perf_event.h b/arch/arm/include/asm/perf_event.h
index e074948..625cd62 100644
--- a/arch/arm/include/asm/perf_event.h
+++ b/arch/arm/include/asm/perf_event.h
@@ -12,6 +12,13 @@
#ifndef __ARM_PERF_EVENT_H__
#define __ARM_PERF_EVENT_H__
-/* Nothing to see here... */
+/*
+ * The ARMv7 CPU PMU supports up to 32 event counters.
+ */
+#define ARMPMU_MAX_HWEVENTS 32
+
+#define HW_OP_UNSUPPORTED 0xFFFF
+#define C(_x) PERF_COUNT_HW_CACHE_##_x
+#define CACHE_OP_UNSUPPORTED 0xFFFF
#endif /* __ARM_PERF_EVENT_H__ */
diff --git a/arch/arm/include/asm/pmu.h b/arch/arm/include/asm/pmu.h
index 4432305..a26170d 100644
--- a/arch/arm/include/asm/pmu.h
+++ b/arch/arm/include/asm/pmu.h
@@ -16,69 +16,30 @@
#include <linux/perf_event.h>
/*
- * Types of PMUs that can be accessed directly and require mutual
- * exclusion between profiling tools.
- */
-enum arm_pmu_type {
- ARM_PMU_DEVICE_CPU = 0,
- ARM_NUM_PMU_DEVICES,
-};
-
-/*
* struct arm_pmu_platdata - ARM PMU platform data
*
* @handle_irq: an optional handler which will be called from the
* interrupt and passed the address of the low level handler,
* and can be used to implement any platform specific handling
* before or after calling it.
- * @enable_irq: an optional handler which will be called after
- * request_irq and be used to handle some platform specific
- * irq enablement
- * @disable_irq: an optional handler which will be called before
- * free_irq and be used to handle some platform specific
- * irq disablement
+ * @runtime_resume: an optional handler which will be called by the
+ * runtime PM framework following a call to pm_runtime_get().
+ * Note that if pm_runtime_get() is called more than once in
+ * succession this handler will only be called once.
+ * @runtime_suspend: an optional handler which will be called by the
+ * runtime PM framework following a call to pm_runtime_put().
+ * Note that if pm_runtime_get() is called more than once in
+ * succession this handler will only be called following the
+ * final call to pm_runtime_put() that actually disables the
+ * hardware.
*/
struct arm_pmu_platdata {
irqreturn_t (*handle_irq)(int irq, void *dev,
irq_handler_t pmu_handler);
- void (*enable_irq)(int irq);
- void (*disable_irq)(int irq);
+ int (*runtime_resume)(struct device *dev);
+ int (*runtime_suspend)(struct device *dev);
};
-#ifdef CONFIG_CPU_HAS_PMU
-
-/**
- * reserve_pmu() - reserve the hardware performance counters
- *
- * Reserve the hardware performance counters in the system for exclusive use.
- * Returns 0 on success or -EBUSY if the lock is already held.
- */
-extern int
-reserve_pmu(enum arm_pmu_type type);
-
-/**
- * release_pmu() - Relinquish control of the performance counters
- *
- * Release the performance counters and allow someone else to use them.
- */
-extern void
-release_pmu(enum arm_pmu_type type);
-
-#else /* CONFIG_CPU_HAS_PMU */
-
-#include <linux/err.h>
-
-static inline int
-reserve_pmu(enum arm_pmu_type type)
-{
- return -ENODEV;
-}
-
-static inline void
-release_pmu(enum arm_pmu_type type) { }
-
-#endif /* CONFIG_CPU_HAS_PMU */
-
#ifdef CONFIG_HW_PERF_EVENTS
/* The events for a given PMU register set. */
@@ -103,7 +64,6 @@
struct arm_pmu {
struct pmu pmu;
- enum arm_pmu_type type;
cpumask_t active_irqs;
char *name;
irqreturn_t (*handle_irq)(int irq_num, void *dev);
@@ -118,6 +78,8 @@
void (*start)(void);
void (*stop)(void);
void (*reset)(void *);
+ int (*request_irq)(irq_handler_t handler);
+ void (*free_irq)(void);
int (*map_event)(struct perf_event *event);
int num_events;
atomic_t active_events;
@@ -129,7 +91,9 @@
#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type);
+extern const struct dev_pm_ops armpmu_dev_pm_ops;
+
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type);
u64 armpmu_event_update(struct perf_event *event,
struct hw_perf_event *hwc,
@@ -139,6 +103,13 @@
struct hw_perf_event *hwc,
int idx);
+int armpmu_map_event(struct perf_event *event,
+ const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+ const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX],
+ u32 raw_event_mask);
+
#endif /* CONFIG_HW_PERF_EVENTS */
#endif /* __ARM_PMU_H__ */
diff --git a/arch/arm/kernel/Makefile b/arch/arm/kernel/Makefile
index 7ad2d5c..1c43214 100644
--- a/arch/arm/kernel/Makefile
+++ b/arch/arm/kernel/Makefile
@@ -69,8 +69,7 @@
obj-$(CONFIG_CPU_MOHAWK) += xscale-cp0.o
obj-$(CONFIG_CPU_PJ4) += pj4-cp0.o
obj-$(CONFIG_IWMMXT) += iwmmxt.o
-obj-$(CONFIG_CPU_HAS_PMU) += pmu.o
-obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o
+obj-$(CONFIG_HW_PERF_EVENTS) += perf_event.o perf_event_cpu.o
AFLAGS_iwmmxt.o := -Wa,-mcpu=iwmmxt
obj-$(CONFIG_ARM_CPU_TOPOLOGY) += topology.o
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index ab243b8..93971b1 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -12,68 +12,15 @@
*/
#define pr_fmt(fmt) "hw perfevents: " fmt
-#include <linux/bitmap.h>
-#include <linux/interrupt.h>
#include <linux/kernel.h>
-#include <linux/export.h>
-#include <linux/perf_event.h>
#include <linux/platform_device.h>
-#include <linux/spinlock.h>
+#include <linux/pm_runtime.h>
#include <linux/uaccess.h>
-#include <asm/cputype.h>
-#include <asm/irq.h>
#include <asm/irq_regs.h>
#include <asm/pmu.h>
#include <asm/stacktrace.h>
-/*
- * ARMv6 supports a maximum of 3 events, starting from index 0. If we add
- * another platform that supports more, we need to increase this to be the
- * largest of all platforms.
- *
- * ARMv7 supports up to 32 events:
- * cycle counter CCNT + 31 events counters CNT0..30.
- * Cortex-A8 has 1+4 counters, Cortex-A9 has 1+6 counters.
- */
-#define ARMPMU_MAX_HWEVENTS 32
-
-static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
-static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
-static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
-
-#define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
-
-/* Set at runtime when we know what CPU type we are. */
-static struct arm_pmu *cpu_pmu;
-
-const char *perf_pmu_name(void)
-{
- if (!cpu_pmu)
- return NULL;
-
- return cpu_pmu->pmu.name;
-}
-EXPORT_SYMBOL_GPL(perf_pmu_name);
-
-int perf_num_counters(void)
-{
- int max_events = 0;
-
- if (cpu_pmu != NULL)
- max_events = cpu_pmu->num_events;
-
- return max_events;
-}
-EXPORT_SYMBOL_GPL(perf_num_counters);
-
-#define HW_OP_UNSUPPORTED 0xFFFF
-
-#define C(_x) \
- PERF_COUNT_HW_CACHE_##_x
-
-#define CACHE_OP_UNSUPPORTED 0xFFFF
-
static int
armpmu_map_cache_event(const unsigned (*cache_map)
[PERF_COUNT_HW_CACHE_MAX]
@@ -104,7 +51,7 @@
}
static int
-armpmu_map_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
+armpmu_map_hw_event(const unsigned (*event_map)[PERF_COUNT_HW_MAX], u64 config)
{
int mapping = (*event_map)[config];
return mapping == HW_OP_UNSUPPORTED ? -ENOENT : mapping;
@@ -116,19 +63,20 @@
return (int)(config & raw_event_mask);
}
-static int map_cpu_event(struct perf_event *event,
- const unsigned (*event_map)[PERF_COUNT_HW_MAX],
- const unsigned (*cache_map)
- [PERF_COUNT_HW_CACHE_MAX]
- [PERF_COUNT_HW_CACHE_OP_MAX]
- [PERF_COUNT_HW_CACHE_RESULT_MAX],
- u32 raw_event_mask)
+int
+armpmu_map_event(struct perf_event *event,
+ const unsigned (*event_map)[PERF_COUNT_HW_MAX],
+ const unsigned (*cache_map)
+ [PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX],
+ u32 raw_event_mask)
{
u64 config = event->attr.config;
switch (event->attr.type) {
case PERF_TYPE_HARDWARE:
- return armpmu_map_event(event_map, config);
+ return armpmu_map_hw_event(event_map, config);
case PERF_TYPE_HW_CACHE:
return armpmu_map_cache_event(cache_map, config);
case PERF_TYPE_RAW:
@@ -222,7 +170,6 @@
*/
if (!(hwc->state & PERF_HES_STOPPED)) {
armpmu->disable(hwc, hwc->idx);
- barrier(); /* why? */
armpmu_event_update(event, hwc, hwc->idx);
hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
}
@@ -350,99 +297,41 @@
return 0;
}
-static irqreturn_t armpmu_platform_irq(int irq, void *dev)
+static irqreturn_t armpmu_dispatch_irq(int irq, void *dev)
{
struct arm_pmu *armpmu = (struct arm_pmu *) dev;
struct platform_device *plat_device = armpmu->plat_device;
struct arm_pmu_platdata *plat = dev_get_platdata(&plat_device->dev);
- return plat->handle_irq(irq, dev, armpmu->handle_irq);
+ if (plat && plat->handle_irq)
+ return plat->handle_irq(irq, dev, armpmu->handle_irq);
+ else
+ return armpmu->handle_irq(irq, dev);
}
static void
armpmu_release_hardware(struct arm_pmu *armpmu)
{
- int i, irq, irqs;
- struct platform_device *pmu_device = armpmu->plat_device;
- struct arm_pmu_platdata *plat =
- dev_get_platdata(&pmu_device->dev);
-
- irqs = min(pmu_device->num_resources, num_possible_cpus());
-
- for (i = 0; i < irqs; ++i) {
- if (!cpumask_test_and_clear_cpu(i, &armpmu->active_irqs))
- continue;
- irq = platform_get_irq(pmu_device, i);
- if (irq >= 0) {
- if (plat && plat->disable_irq)
- plat->disable_irq(irq);
- free_irq(irq, armpmu);
- }
- }
-
- release_pmu(armpmu->type);
+ armpmu->free_irq();
+ pm_runtime_put_sync(&armpmu->plat_device->dev);
}
static int
armpmu_reserve_hardware(struct arm_pmu *armpmu)
{
- struct arm_pmu_platdata *plat;
- irq_handler_t handle_irq;
- int i, err, irq, irqs;
+ int err;
struct platform_device *pmu_device = armpmu->plat_device;
if (!pmu_device)
return -ENODEV;
- err = reserve_pmu(armpmu->type);
+ pm_runtime_get_sync(&pmu_device->dev);
+ err = armpmu->request_irq(armpmu_dispatch_irq);
if (err) {
- pr_warning("unable to reserve pmu\n");
+ armpmu_release_hardware(armpmu);
return err;
}
- plat = dev_get_platdata(&pmu_device->dev);
- if (plat && plat->handle_irq)
- handle_irq = armpmu_platform_irq;
- else
- handle_irq = armpmu->handle_irq;
-
- irqs = min(pmu_device->num_resources, num_possible_cpus());
- if (irqs < 1) {
- pr_err("no irqs for PMUs defined\n");
- return -ENODEV;
- }
-
- for (i = 0; i < irqs; ++i) {
- err = 0;
- irq = platform_get_irq(pmu_device, i);
- if (irq < 0)
- continue;
-
- /*
- * If we have a single PMU interrupt that we can't shift,
- * assume that we're running on a uniprocessor machine and
- * continue. Otherwise, continue without this interrupt.
- */
- if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
- pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
- irq, i);
- continue;
- }
-
- err = request_irq(irq, handle_irq,
- IRQF_DISABLED | IRQF_NOBALANCING,
- "arm-pmu", armpmu);
- if (err) {
- pr_err("unable to request IRQ%d for ARM PMU counters\n",
- irq);
- armpmu_release_hardware(armpmu);
- return err;
- } else if (plat && plat->enable_irq)
- plat->enable_irq(irq);
-
- cpumask_set_cpu(i, &armpmu->active_irqs);
- }
-
return 0;
}
@@ -581,6 +470,32 @@
armpmu->stop();
}
+#ifdef CONFIG_PM_RUNTIME
+static int armpmu_runtime_resume(struct device *dev)
+{
+ struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+
+ if (plat && plat->runtime_resume)
+ return plat->runtime_resume(dev);
+
+ return 0;
+}
+
+static int armpmu_runtime_suspend(struct device *dev)
+{
+ struct arm_pmu_platdata *plat = dev_get_platdata(dev);
+
+ if (plat && plat->runtime_suspend)
+ return plat->runtime_suspend(dev);
+
+ return 0;
+}
+#endif
+
+const struct dev_pm_ops armpmu_dev_pm_ops = {
+ SET_RUNTIME_PM_OPS(armpmu_runtime_suspend, armpmu_runtime_resume, NULL)
+};
+
static void __init armpmu_init(struct arm_pmu *armpmu)
{
atomic_set(&armpmu->active_events, 0);
@@ -598,174 +513,14 @@
};
}
-int __init armpmu_register(struct arm_pmu *armpmu, char *name, int type)
+int armpmu_register(struct arm_pmu *armpmu, char *name, int type)
{
armpmu_init(armpmu);
+ pr_info("enabled with %s PMU driver, %d counters available\n",
+ armpmu->name, armpmu->num_events);
return perf_pmu_register(&armpmu->pmu, name, type);
}
-/* Include the PMU-specific implementations. */
-#include "perf_event_xscale.c"
-#include "perf_event_v6.c"
-#include "perf_event_v7.c"
-
-/*
- * Ensure the PMU has sane values out of reset.
- * This requires SMP to be available, so exists as a separate initcall.
- */
-static int __init
-cpu_pmu_reset(void)
-{
- if (cpu_pmu && cpu_pmu->reset)
- return on_each_cpu(cpu_pmu->reset, NULL, 1);
- return 0;
-}
-arch_initcall(cpu_pmu_reset);
-
-/*
- * PMU platform driver and devicetree bindings.
- */
-static struct of_device_id armpmu_of_device_ids[] = {
- {.compatible = "arm,cortex-a9-pmu"},
- {.compatible = "arm,cortex-a8-pmu"},
- {.compatible = "arm,arm1136-pmu"},
- {.compatible = "arm,arm1176-pmu"},
- {},
-};
-
-static struct platform_device_id armpmu_plat_device_ids[] = {
- {.name = "arm-pmu"},
- {},
-};
-
-static int __devinit armpmu_device_probe(struct platform_device *pdev)
-{
- if (!cpu_pmu)
- return -ENODEV;
-
- cpu_pmu->plat_device = pdev;
- return 0;
-}
-
-static struct platform_driver armpmu_driver = {
- .driver = {
- .name = "arm-pmu",
- .of_match_table = armpmu_of_device_ids,
- },
- .probe = armpmu_device_probe,
- .id_table = armpmu_plat_device_ids,
-};
-
-static int __init register_pmu_driver(void)
-{
- return platform_driver_register(&armpmu_driver);
-}
-device_initcall(register_pmu_driver);
-
-static struct pmu_hw_events *armpmu_get_cpu_events(void)
-{
- return &__get_cpu_var(cpu_hw_events);
-}
-
-static void __init cpu_pmu_init(struct arm_pmu *armpmu)
-{
- int cpu;
- for_each_possible_cpu(cpu) {
- struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
- events->events = per_cpu(hw_events, cpu);
- events->used_mask = per_cpu(used_mask, cpu);
- raw_spin_lock_init(&events->pmu_lock);
- }
- armpmu->get_hw_events = armpmu_get_cpu_events;
- armpmu->type = ARM_PMU_DEVICE_CPU;
-}
-
-/*
- * PMU hardware loses all context when a CPU goes offline.
- * When a CPU is hotplugged back in, since some hardware registers are
- * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
- * junk values out of them.
- */
-static int __cpuinit pmu_cpu_notify(struct notifier_block *b,
- unsigned long action, void *hcpu)
-{
- if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
- return NOTIFY_DONE;
-
- if (cpu_pmu && cpu_pmu->reset)
- cpu_pmu->reset(NULL);
-
- return NOTIFY_OK;
-}
-
-static struct notifier_block __cpuinitdata pmu_cpu_notifier = {
- .notifier_call = pmu_cpu_notify,
-};
-
-/*
- * CPU PMU identification and registration.
- */
-static int __init
-init_hw_perf_events(void)
-{
- unsigned long cpuid = read_cpuid_id();
- unsigned long implementor = (cpuid & 0xFF000000) >> 24;
- unsigned long part_number = (cpuid & 0xFFF0);
-
- /* ARM Ltd CPUs. */
- if (0x41 == implementor) {
- switch (part_number) {
- case 0xB360: /* ARM1136 */
- case 0xB560: /* ARM1156 */
- case 0xB760: /* ARM1176 */
- cpu_pmu = armv6pmu_init();
- break;
- case 0xB020: /* ARM11mpcore */
- cpu_pmu = armv6mpcore_pmu_init();
- break;
- case 0xC080: /* Cortex-A8 */
- cpu_pmu = armv7_a8_pmu_init();
- break;
- case 0xC090: /* Cortex-A9 */
- cpu_pmu = armv7_a9_pmu_init();
- break;
- case 0xC050: /* Cortex-A5 */
- cpu_pmu = armv7_a5_pmu_init();
- break;
- case 0xC0F0: /* Cortex-A15 */
- cpu_pmu = armv7_a15_pmu_init();
- break;
- case 0xC070: /* Cortex-A7 */
- cpu_pmu = armv7_a7_pmu_init();
- break;
- }
- /* Intel CPUs [xscale]. */
- } else if (0x69 == implementor) {
- part_number = (cpuid >> 13) & 0x7;
- switch (part_number) {
- case 1:
- cpu_pmu = xscale1pmu_init();
- break;
- case 2:
- cpu_pmu = xscale2pmu_init();
- break;
- }
- }
-
- if (cpu_pmu) {
- pr_info("enabled with %s PMU driver, %d counters available\n",
- cpu_pmu->name, cpu_pmu->num_events);
- cpu_pmu_init(cpu_pmu);
- register_cpu_notifier(&pmu_cpu_notifier);
- armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
- } else {
- pr_info("no hardware support available\n");
- }
-
- return 0;
-}
-early_initcall(init_hw_perf_events);
-
/*
* Callchain handling code.
*/
diff --git a/arch/arm/kernel/perf_event_cpu.c b/arch/arm/kernel/perf_event_cpu.c
new file mode 100644
index 0000000..8d7d8d4
--- /dev/null
+++ b/arch/arm/kernel/perf_event_cpu.c
@@ -0,0 +1,295 @@
+/*
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ * Copyright (C) 2012 ARM Limited
+ *
+ * Author: Will Deacon <will.deacon@arm.com>
+ */
+#define pr_fmt(fmt) "CPU PMU: " fmt
+
+#include <linux/bitmap.h>
+#include <linux/export.h>
+#include <linux/kernel.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/spinlock.h>
+
+#include <asm/cputype.h>
+#include <asm/irq_regs.h>
+#include <asm/pmu.h>
+
+/* Set at runtime when we know what CPU type we are. */
+static struct arm_pmu *cpu_pmu;
+
+static DEFINE_PER_CPU(struct perf_event * [ARMPMU_MAX_HWEVENTS], hw_events);
+static DEFINE_PER_CPU(unsigned long [BITS_TO_LONGS(ARMPMU_MAX_HWEVENTS)], used_mask);
+static DEFINE_PER_CPU(struct pmu_hw_events, cpu_hw_events);
+
+/*
+ * Despite the names, these two functions are CPU-specific and are used
+ * by the OProfile/perf code.
+ */
+const char *perf_pmu_name(void)
+{
+ if (!cpu_pmu)
+ return NULL;
+
+ return cpu_pmu->pmu.name;
+}
+EXPORT_SYMBOL_GPL(perf_pmu_name);
+
+int perf_num_counters(void)
+{
+ int max_events = 0;
+
+ if (cpu_pmu != NULL)
+ max_events = cpu_pmu->num_events;
+
+ return max_events;
+}
+EXPORT_SYMBOL_GPL(perf_num_counters);
+
+/* Include the PMU-specific implementations. */
+#include "perf_event_xscale.c"
+#include "perf_event_v6.c"
+#include "perf_event_v7.c"
+
+static struct pmu_hw_events *cpu_pmu_get_cpu_events(void)
+{
+ return &__get_cpu_var(cpu_hw_events);
+}
+
+static void cpu_pmu_free_irq(void)
+{
+ int i, irq, irqs;
+ struct platform_device *pmu_device = cpu_pmu->plat_device;
+
+ irqs = min(pmu_device->num_resources, num_possible_cpus());
+
+ for (i = 0; i < irqs; ++i) {
+ if (!cpumask_test_and_clear_cpu(i, &cpu_pmu->active_irqs))
+ continue;
+ irq = platform_get_irq(pmu_device, i);
+ if (irq >= 0)
+ free_irq(irq, cpu_pmu);
+ }
+}
+
+static int cpu_pmu_request_irq(irq_handler_t handler)
+{
+ int i, err, irq, irqs;
+ struct platform_device *pmu_device = cpu_pmu->plat_device;
+
+ if (!pmu_device)
+ return -ENODEV;
+
+ irqs = min(pmu_device->num_resources, num_possible_cpus());
+ if (irqs < 1) {
+ pr_err("no irqs for PMUs defined\n");
+ return -ENODEV;
+ }
+
+ for (i = 0; i < irqs; ++i) {
+ err = 0;
+ irq = platform_get_irq(pmu_device, i);
+ if (irq < 0)
+ continue;
+
+ /*
+ * If we have a single PMU interrupt that we can't shift,
+ * assume that we're running on a uniprocessor machine and
+ * continue. Otherwise, continue without this interrupt.
+ */
+ if (irq_set_affinity(irq, cpumask_of(i)) && irqs > 1) {
+ pr_warning("unable to set irq affinity (irq=%d, cpu=%u)\n",
+ irq, i);
+ continue;
+ }
+
+ err = request_irq(irq, handler, IRQF_NOBALANCING, "arm-pmu",
+ cpu_pmu);
+ if (err) {
+ pr_err("unable to request IRQ%d for ARM PMU counters\n",
+ irq);
+ return err;
+ }
+
+ cpumask_set_cpu(i, &cpu_pmu->active_irqs);
+ }
+
+ return 0;
+}
+
+static void __devinit cpu_pmu_init(struct arm_pmu *cpu_pmu)
+{
+ int cpu;
+ for_each_possible_cpu(cpu) {
+ struct pmu_hw_events *events = &per_cpu(cpu_hw_events, cpu);
+ events->events = per_cpu(hw_events, cpu);
+ events->used_mask = per_cpu(used_mask, cpu);
+ raw_spin_lock_init(&events->pmu_lock);
+ }
+
+ cpu_pmu->get_hw_events = cpu_pmu_get_cpu_events;
+ cpu_pmu->request_irq = cpu_pmu_request_irq;
+ cpu_pmu->free_irq = cpu_pmu_free_irq;
+
+ /* Ensure the PMU has sane values out of reset. */
+ if (cpu_pmu && cpu_pmu->reset)
+ on_each_cpu(cpu_pmu->reset, NULL, 1);
+}
+
+/*
+ * PMU hardware loses all context when a CPU goes offline.
+ * When a CPU is hotplugged back in, since some hardware registers are
+ * UNKNOWN at reset, the PMU must be explicitly reset to avoid reading
+ * junk values out of them.
+ */
+static int __cpuinit cpu_pmu_notify(struct notifier_block *b,
+ unsigned long action, void *hcpu)
+{
+ if ((action & ~CPU_TASKS_FROZEN) != CPU_STARTING)
+ return NOTIFY_DONE;
+
+ if (cpu_pmu && cpu_pmu->reset)
+ cpu_pmu->reset(NULL);
+
+ return NOTIFY_OK;
+}
+
+static struct notifier_block __cpuinitdata cpu_pmu_hotplug_notifier = {
+ .notifier_call = cpu_pmu_notify,
+};
+
+/*
+ * PMU platform driver and devicetree bindings.
+ */
+static struct of_device_id __devinitdata cpu_pmu_of_device_ids[] = {
+ {.compatible = "arm,cortex-a15-pmu", .data = armv7_a15_pmu_init},
+ {.compatible = "arm,cortex-a9-pmu", .data = armv7_a9_pmu_init},
+ {.compatible = "arm,cortex-a8-pmu", .data = armv7_a8_pmu_init},
+ {.compatible = "arm,cortex-a7-pmu", .data = armv7_a7_pmu_init},
+ {.compatible = "arm,cortex-a5-pmu", .data = armv7_a5_pmu_init},
+ {.compatible = "arm,arm11mpcore-pmu", .data = armv6mpcore_pmu_init},
+ {.compatible = "arm,arm1176-pmu", .data = armv6pmu_init},
+ {.compatible = "arm,arm1136-pmu", .data = armv6pmu_init},
+ {},
+};
+
+static struct platform_device_id __devinitdata cpu_pmu_plat_device_ids[] = {
+ {.name = "arm-pmu"},
+ {},
+};
+
+/*
+ * CPU PMU identification and probing.
+ */
+static struct arm_pmu *__devinit probe_current_pmu(void)
+{
+ struct arm_pmu *pmu = NULL;
+ int cpu = get_cpu();
+ unsigned long cpuid = read_cpuid_id();
+ unsigned long implementor = (cpuid & 0xFF000000) >> 24;
+ unsigned long part_number = (cpuid & 0xFFF0);
+
+ pr_info("probing PMU on CPU %d\n", cpu);
+
+ /* ARM Ltd CPUs. */
+ if (0x41 == implementor) {
+ switch (part_number) {
+ case 0xB360: /* ARM1136 */
+ case 0xB560: /* ARM1156 */
+ case 0xB760: /* ARM1176 */
+ pmu = armv6pmu_init();
+ break;
+ case 0xB020: /* ARM11mpcore */
+ pmu = armv6mpcore_pmu_init();
+ break;
+ case 0xC080: /* Cortex-A8 */
+ pmu = armv7_a8_pmu_init();
+ break;
+ case 0xC090: /* Cortex-A9 */
+ pmu = armv7_a9_pmu_init();
+ break;
+ case 0xC050: /* Cortex-A5 */
+ pmu = armv7_a5_pmu_init();
+ break;
+ case 0xC0F0: /* Cortex-A15 */
+ pmu = armv7_a15_pmu_init();
+ break;
+ case 0xC070: /* Cortex-A7 */
+ pmu = armv7_a7_pmu_init();
+ break;
+ }
+ /* Intel CPUs [xscale]. */
+ } else if (0x69 == implementor) {
+ part_number = (cpuid >> 13) & 0x7;
+ switch (part_number) {
+ case 1:
+ pmu = xscale1pmu_init();
+ break;
+ case 2:
+ pmu = xscale2pmu_init();
+ break;
+ }
+ }
+
+ put_cpu();
+ return pmu;
+}
+
+static int __devinit cpu_pmu_device_probe(struct platform_device *pdev)
+{
+ const struct of_device_id *of_id;
+ struct arm_pmu *(*init_fn)(void);
+ struct device_node *node = pdev->dev.of_node;
+
+ if (cpu_pmu) {
+ pr_info("attempt to register multiple PMU devices!");
+ return -ENOSPC;
+ }
+
+ if (node && (of_id = of_match_node(cpu_pmu_of_device_ids, pdev->dev.of_node))) {
+ init_fn = of_id->data;
+ cpu_pmu = init_fn();
+ } else {
+ cpu_pmu = probe_current_pmu();
+ }
+
+ if (!cpu_pmu)
+ return -ENODEV;
+
+ cpu_pmu->plat_device = pdev;
+ cpu_pmu_init(cpu_pmu);
+ register_cpu_notifier(&cpu_pmu_hotplug_notifier);
+ armpmu_register(cpu_pmu, cpu_pmu->name, PERF_TYPE_RAW);
+
+ return 0;
+}
+
+static struct platform_driver cpu_pmu_driver = {
+ .driver = {
+ .name = "arm-pmu",
+ .pm = &armpmu_dev_pm_ops,
+ .of_match_table = cpu_pmu_of_device_ids,
+ },
+ .probe = cpu_pmu_device_probe,
+ .id_table = cpu_pmu_plat_device_ids,
+};
+
+static int __init register_pmu_driver(void)
+{
+ return platform_driver_register(&cpu_pmu_driver);
+}
+device_initcall(register_pmu_driver);
diff --git a/arch/arm/kernel/perf_event_v6.c b/arch/arm/kernel/perf_event_v6.c
index c90fcb2..6ccc079 100644
--- a/arch/arm/kernel/perf_event_v6.c
+++ b/arch/arm/kernel/perf_event_v6.c
@@ -645,7 +645,7 @@
static int armv6_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv6_perf_map,
+ return armpmu_map_event(event, &armv6_perf_map,
&armv6_perf_cache_map, 0xFF);
}
@@ -664,7 +664,7 @@
.max_period = (1LLU << 32) - 1,
};
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
{
return &armv6pmu;
}
@@ -679,7 +679,7 @@
static int armv6mpcore_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv6mpcore_perf_map,
+ return armpmu_map_event(event, &armv6mpcore_perf_map,
&armv6mpcore_perf_cache_map, 0xFF);
}
@@ -698,17 +698,17 @@
.max_period = (1LLU << 32) - 1,
};
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
{
return &armv6mpcore_pmu;
}
#else
-static struct arm_pmu *__init armv6pmu_init(void)
+static struct arm_pmu *__devinit armv6pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init armv6mpcore_pmu_init(void)
+static struct arm_pmu *__devinit armv6mpcore_pmu_init(void)
{
return NULL;
}
diff --git a/arch/arm/kernel/perf_event_v7.c b/arch/arm/kernel/perf_event_v7.c
index f04070b..bd4b090 100644
--- a/arch/arm/kernel/perf_event_v7.c
+++ b/arch/arm/kernel/perf_event_v7.c
@@ -1204,31 +1204,31 @@
static int armv7_a8_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv7_a8_perf_map,
+ return armpmu_map_event(event, &armv7_a8_perf_map,
&armv7_a8_perf_cache_map, 0xFF);
}
static int armv7_a9_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv7_a9_perf_map,
+ return armpmu_map_event(event, &armv7_a9_perf_map,
&armv7_a9_perf_cache_map, 0xFF);
}
static int armv7_a5_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv7_a5_perf_map,
+ return armpmu_map_event(event, &armv7_a5_perf_map,
&armv7_a5_perf_cache_map, 0xFF);
}
static int armv7_a15_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv7_a15_perf_map,
+ return armpmu_map_event(event, &armv7_a15_perf_map,
&armv7_a15_perf_cache_map, 0xFF);
}
static int armv7_a7_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &armv7_a7_perf_map,
+ return armpmu_map_event(event, &armv7_a7_perf_map,
&armv7_a7_perf_cache_map, 0xFF);
}
@@ -1245,7 +1245,7 @@
.max_period = (1LLU << 32) - 1,
};
-static u32 __init armv7_read_num_pmnc_events(void)
+static u32 __devinit armv7_read_num_pmnc_events(void)
{
u32 nb_cnt;
@@ -1256,7 +1256,7 @@
return nb_cnt + 1;
}
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
{
armv7pmu.name = "ARMv7 Cortex-A8";
armv7pmu.map_event = armv7_a8_map_event;
@@ -1264,7 +1264,7 @@
return &armv7pmu;
}
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
{
armv7pmu.name = "ARMv7 Cortex-A9";
armv7pmu.map_event = armv7_a9_map_event;
@@ -1272,7 +1272,7 @@
return &armv7pmu;
}
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
{
armv7pmu.name = "ARMv7 Cortex-A5";
armv7pmu.map_event = armv7_a5_map_event;
@@ -1280,7 +1280,7 @@
return &armv7pmu;
}
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
{
armv7pmu.name = "ARMv7 Cortex-A15";
armv7pmu.map_event = armv7_a15_map_event;
@@ -1289,7 +1289,7 @@
return &armv7pmu;
}
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
{
armv7pmu.name = "ARMv7 Cortex-A7";
armv7pmu.map_event = armv7_a7_map_event;
@@ -1298,27 +1298,27 @@
return &armv7pmu;
}
#else
-static struct arm_pmu *__init armv7_a8_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a8_pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init armv7_a9_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a9_pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init armv7_a5_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a5_pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init armv7_a15_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a15_pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init armv7_a7_pmu_init(void)
+static struct arm_pmu *__devinit armv7_a7_pmu_init(void)
{
return NULL;
}
diff --git a/arch/arm/kernel/perf_event_xscale.c b/arch/arm/kernel/perf_event_xscale.c
index f759fe0..426e19f 100644
--- a/arch/arm/kernel/perf_event_xscale.c
+++ b/arch/arm/kernel/perf_event_xscale.c
@@ -430,7 +430,7 @@
static int xscale_map_event(struct perf_event *event)
{
- return map_cpu_event(event, &xscale_perf_map,
+ return armpmu_map_event(event, &xscale_perf_map,
&xscale_perf_cache_map, 0xFF);
}
@@ -449,7 +449,7 @@
.max_period = (1LLU << 32) - 1,
};
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
{
return &xscale1pmu;
}
@@ -816,17 +816,17 @@
.max_period = (1LLU << 32) - 1,
};
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
{
return &xscale2pmu;
}
#else
-static struct arm_pmu *__init xscale1pmu_init(void)
+static struct arm_pmu *__devinit xscale1pmu_init(void)
{
return NULL;
}
-static struct arm_pmu *__init xscale2pmu_init(void)
+static struct arm_pmu *__devinit xscale2pmu_init(void)
{
return NULL;
}
diff --git a/arch/arm/kernel/pmu.c b/arch/arm/kernel/pmu.c
deleted file mode 100644
index 2334bf8..0000000
--- a/arch/arm/kernel/pmu.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * linux/arch/arm/kernel/pmu.c
- *
- * Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
- * Copyright (C) 2010 ARM Ltd, Will Deacon
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/err.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <asm/pmu.h>
-
-/*
- * PMU locking to ensure mutual exclusion between different subsystems.
- */
-static unsigned long pmu_lock[BITS_TO_LONGS(ARM_NUM_PMU_DEVICES)];
-
-int
-reserve_pmu(enum arm_pmu_type type)
-{
- return test_and_set_bit_lock(type, pmu_lock) ? -EBUSY : 0;
-}
-EXPORT_SYMBOL_GPL(reserve_pmu);
-
-void
-release_pmu(enum arm_pmu_type type)
-{
- clear_bit_unlock(type, pmu_lock);
-}
-EXPORT_SYMBOL_GPL(release_pmu);
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 45c97b1..76e7953 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -29,7 +29,6 @@
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/mach/time.h>
-#include <asm/pmu.h>
#include <asm/mach/arch.h>
#include <mach/dma.h>
@@ -116,7 +115,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.resource = &pmu_resource,
.num_resources = 1,
};
diff --git a/arch/arm/mach-imx/clk-imx35.c b/arch/arm/mach-imx/clk-imx35.c
index c6422fb..cebc71d 100644
--- a/arch/arm/mach-imx/clk-imx35.c
+++ b/arch/arm/mach-imx/clk-imx35.c
@@ -62,8 +62,8 @@
kpp_gate, mlb_gate, mshc_gate, owire_gate, pwm_gate, rngc_gate,
rtc_gate, rtic_gate, scc_gate, sdma_gate, spba_gate, spdif_gate,
ssi1_gate, ssi2_gate, uart1_gate, uart2_gate, uart3_gate, usbotg_gate,
- wdog_gate, max_gate, admux_gate, csi_gate, iim_gate, gpu2d_gate,
- clk_max
+ wdog_gate, max_gate, admux_gate, csi_gate, csi_div, csi_sel, iim_gate,
+ gpu2d_gate, clk_max
};
static struct clk *clk[clk_max];
@@ -142,6 +142,9 @@
clk[nfc_div] = imx_clk_divider("nfc_div", "ahb", base + MX35_CCM_PDR4, 28, 4);
+ clk[csi_sel] = imx_clk_mux("csi_sel", base + MX35_CCM_PDR2, 7, 1, std_sel, ARRAY_SIZE(std_sel));
+ clk[csi_div] = imx_clk_divider("csi_div", "csi_sel", base + MX35_CCM_PDR2, 16, 6);
+
clk[asrc_gate] = imx_clk_gate2("asrc_gate", "ipg", base + MX35_CCM_CGR0, 0);
clk[pata_gate] = imx_clk_gate2("pata_gate", "ipg", base + MX35_CCM_CGR0, 2);
clk[audmux_gate] = imx_clk_gate2("audmux_gate", "ipg", base + MX35_CCM_CGR0, 4);
@@ -192,7 +195,7 @@
clk[max_gate] = imx_clk_gate2("max_gate", "dummy", base + MX35_CCM_CGR2, 26);
clk[admux_gate] = imx_clk_gate2("admux_gate", "ipg", base + MX35_CCM_CGR2, 30);
- clk[csi_gate] = imx_clk_gate2("csi_gate", "ipg", base + MX35_CCM_CGR3, 0);
+ clk[csi_gate] = imx_clk_gate2("csi_gate", "csi_div", base + MX35_CCM_CGR3, 0);
clk[iim_gate] = imx_clk_gate2("iim_gate", "ipg", base + MX35_CCM_CGR3, 2);
clk[gpu2d_gate] = imx_clk_gate2("gpu2d_gate", "ahb", base + MX35_CCM_CGR3, 4);
@@ -228,6 +231,7 @@
clk_register_clkdev(clk[i2c3_gate], NULL, "imx-i2c.2");
clk_register_clkdev(clk[ipu_gate], NULL, "ipu-core");
clk_register_clkdev(clk[ipu_gate], NULL, "mx3_sdc_fb");
+ clk_register_clkdev(clk[kpp_gate], NULL, "imx-keypad");
clk_register_clkdev(clk[owire_gate], NULL, "mxc_w1");
clk_register_clkdev(clk[sdma_gate], NULL, "imx35-sdma");
clk_register_clkdev(clk[ipg], "ipg", "imx-ssi.0");
@@ -255,6 +259,7 @@
clk_register_clkdev(clk[usbotg_gate], "ahb", "fsl-usb2-udc");
clk_register_clkdev(clk[wdog_gate], NULL, "imx2-wdt.0");
clk_register_clkdev(clk[nfc_div], NULL, "mxc_nand.0");
+ clk_register_clkdev(clk[csi_gate], NULL, "mx3-camera.0");
clk_prepare_enable(clk[spba_gate]);
clk_prepare_enable(clk[gpio1_gate]);
diff --git a/arch/arm/mach-imx/clk-imx51-imx53.c b/arch/arm/mach-imx/clk-imx51-imx53.c
index 4bdcaa9..db70d23 100644
--- a/arch/arm/mach-imx/clk-imx51-imx53.c
+++ b/arch/arm/mach-imx/clk-imx51-imx53.c
@@ -49,6 +49,7 @@
static const char *tve_sel[] = { "tve_pred", "tve_ext_sel", };
static const char *ipu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
static const char *vpu_sel[] = { "axi_a", "axi_b", "emi_slow_gate", "ahb", };
+static const char *mx53_can_sel[] = { "ipg", "ckih1", "ckih2", "lp_apm", };
enum imx5_clks {
dummy, ckil, osc, ckih1, ckih2, ahb, ipg, axi_a, axi_b, uart_pred,
@@ -82,6 +83,7 @@
ssi_ext1_podf, ssi_ext2_pred, ssi_ext2_podf, ssi1_root_gate,
ssi2_root_gate, ssi3_root_gate, ssi_ext1_gate, ssi_ext2_gate,
epit1_ipg_gate, epit1_hf_gate, epit2_ipg_gate, epit2_hf_gate,
+ can_sel, can1_serial_gate, can1_ipg_gate,
clk_max
};
@@ -421,8 +423,12 @@
clk[esdhc4_per_gate] = imx_clk_gate2("esdhc4_per_gate", "esdhc_d_sel", MXC_CCM_CCGR3, 14);
clk[usb_phy1_gate] = imx_clk_gate2("usb_phy1_gate", "usb_phy_sel", MXC_CCM_CCGR4, 10);
clk[usb_phy2_gate] = imx_clk_gate2("usb_phy2_gate", "usb_phy_sel", MXC_CCM_CCGR4, 12);
- clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "ipg", MXC_CCM_CCGR4, 6);
- clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 8);
+ clk[can_sel] = imx_clk_mux("can_sel", MXC_CCM_CSCMR2, 6, 2,
+ mx53_can_sel, ARRAY_SIZE(mx53_can_sel));
+ clk[can1_serial_gate] = imx_clk_gate2("can1_serial_gate", "can_sel", MXC_CCM_CCGR6, 22);
+ clk[can1_ipg_gate] = imx_clk_gate2("can1_ipg_gate", "ipg", MXC_CCM_CCGR6, 20);
+ clk[can2_serial_gate] = imx_clk_gate2("can2_serial_gate", "can_sel", MXC_CCM_CCGR4, 8);
+ clk[can2_ipg_gate] = imx_clk_gate2("can2_ipg_gate", "ipg", MXC_CCM_CCGR4, 6);
clk[i2c3_gate] = imx_clk_gate2("i2c3_gate", "per_root", MXC_CCM_CCGR1, 22);
for (i = 0; i < ARRAY_SIZE(clk); i++)
@@ -455,6 +461,10 @@
clk_register_clkdev(clk[ssi1_ipg_gate], NULL, "63fcc000.ssi");
clk_register_clkdev(clk[ssi2_ipg_gate], NULL, "50014000.ssi");
clk_register_clkdev(clk[ssi3_ipg_gate], NULL, "63fd0000.ssi");
+ clk_register_clkdev(clk[can1_ipg_gate], "ipg", "53fc8000.can");
+ clk_register_clkdev(clk[can1_serial_gate], "per", "53fc8000.can");
+ clk_register_clkdev(clk[can2_ipg_gate], "ipg", "53fcc000.can");
+ clk_register_clkdev(clk[can2_serial_gate], "per", "53fcc000.can");
/* set SDHC root clock to 200MHZ*/
clk_set_rate(clk[esdhc_a_podf], 200000000);
diff --git a/arch/arm/mach-lpc32xx/irq.c b/arch/arm/mach-lpc32xx/irq.c
index 5b1cc35..3c63327 100644
--- a/arch/arm/mach-lpc32xx/irq.c
+++ b/arch/arm/mach-lpc32xx/irq.c
@@ -283,21 +283,25 @@
case IRQ_TYPE_EDGE_RISING:
/* Rising edge sensitive */
__lpc32xx_set_irq_type(d->hwirq, 1, 1);
+ __irq_set_handler_locked(d->hwirq, handle_edge_irq);
break;
case IRQ_TYPE_EDGE_FALLING:
/* Falling edge sensitive */
__lpc32xx_set_irq_type(d->hwirq, 0, 1);
+ __irq_set_handler_locked(d->hwirq, handle_edge_irq);
break;
case IRQ_TYPE_LEVEL_LOW:
/* Low level sensitive */
__lpc32xx_set_irq_type(d->hwirq, 0, 0);
+ __irq_set_handler_locked(d->hwirq, handle_level_irq);
break;
case IRQ_TYPE_LEVEL_HIGH:
/* High level sensitive */
__lpc32xx_set_irq_type(d->hwirq, 1, 0);
+ __irq_set_handler_locked(d->hwirq, handle_level_irq);
break;
/* Other modes are not supported */
@@ -305,9 +309,6 @@
return -EINVAL;
}
- /* Ok to use the level handler for all types */
- irq_set_handler(d->hwirq, handle_level_irq);
-
return 0;
}
diff --git a/arch/arm/mach-lpc32xx/phy3250.c b/arch/arm/mach-lpc32xx/phy3250.c
index b07dcc9..8f2a2f8 100644
--- a/arch/arm/mach-lpc32xx/phy3250.c
+++ b/arch/arm/mach-lpc32xx/phy3250.c
@@ -37,6 +37,8 @@
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <linux/clk.h>
+#include <linux/mtd/lpc32xx_slc.h>
+#include <linux/mtd/lpc32xx_mlc.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
@@ -223,6 +225,14 @@
* gather, and the MMCI driver doesn't do it this way */
};
+static struct lpc32xx_slc_platform_data lpc32xx_slc_data = {
+ .dma_filter = pl08x_filter_id,
+};
+
+static struct lpc32xx_mlc_platform_data lpc32xx_mlc_data = {
+ .dma_filter = pl08x_filter_id,
+};
+
static const struct of_dev_auxdata lpc32xx_auxdata_lookup[] __initconst = {
OF_DEV_AUXDATA("arm,pl022", 0x20084000, "dev:ssp0", &lpc32xx_ssp0_data),
OF_DEV_AUXDATA("arm,pl022", 0x2008C000, "dev:ssp1", &lpc32xx_ssp1_data),
@@ -230,6 +240,10 @@
OF_DEV_AUXDATA("arm,pl080", 0x31000000, "pl08xdmac", &pl08x_pd),
OF_DEV_AUXDATA("arm,pl18x", 0x20098000, "20098000.sd",
&lpc32xx_mmci_data),
+ OF_DEV_AUXDATA("nxp,lpc3220-slc", 0x20020000, "20020000.flash",
+ &lpc32xx_slc_data),
+ OF_DEV_AUXDATA("nxp,lpc3220-mlc", 0x200a8000, "200a8000.flash",
+ &lpc32xx_mlc_data),
{ }
};
@@ -253,12 +267,6 @@
of_platform_populate(NULL, of_default_bus_match_table,
lpc32xx_auxdata_lookup, NULL);
-
- /* Register GPIOs used on this board */
- if (gpio_request(MMC_PWR_ENABLE_GPIO, "mmc_power_en"))
- pr_err("Error requesting gpio %u", MMC_PWR_ENABLE_GPIO);
- else if (gpio_direction_output(MMC_PWR_ENABLE_GPIO, 1))
- pr_err("Error setting gpio %u to output", MMC_PWR_ENABLE_GPIO);
}
static char const *lpc32xx_dt_compat[] __initdata = {
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 1efa984..6f6893e 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -21,7 +21,6 @@
#include <asm/mach-types.h>
#include <asm/mach/map.h>
-#include <asm/pmu.h>
#include "iomap.h"
#include <plat/dma.h>
@@ -445,7 +444,7 @@
static struct platform_device omap_pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = 1,
};
diff --git a/arch/arm/mach-pxa/devices.c b/arch/arm/mach-pxa/devices.c
index 166eee5..c1f3b12 100644
--- a/arch/arm/mach-pxa/devices.c
+++ b/arch/arm/mach-pxa/devices.c
@@ -6,7 +6,6 @@
#include <linux/spi/pxa2xx_spi.h>
#include <linux/i2c/pxa-i2c.h>
-#include <asm/pmu.h>
#include <mach/udc.h>
#include <mach/pxa3xx-u2d.h>
#include <mach/pxafb.h>
@@ -42,7 +41,7 @@
struct platform_device pxa_device_pmu = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.resource = &pxa_resource_pmu,
.num_resources = 1,
};
diff --git a/arch/arm/mach-realview/realview_eb.c b/arch/arm/mach-realview/realview_eb.c
index baf382c..d7a6e9c 100644
--- a/arch/arm/mach-realview/realview_eb.c
+++ b/arch/arm/mach-realview/realview_eb.c
@@ -32,7 +32,6 @@
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
-#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@@ -297,7 +296,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
diff --git a/arch/arm/mach-realview/realview_pb1176.c b/arch/arm/mach-realview/realview_pb1176.c
index b1d7caf..361f898 100644
--- a/arch/arm/mach-realview/realview_pb1176.c
+++ b/arch/arm/mach-realview/realview_pb1176.c
@@ -34,7 +34,6 @@
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
-#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@@ -280,7 +279,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = 1,
.resource = &pmu_resource,
};
diff --git a/arch/arm/mach-realview/realview_pb11mp.c b/arch/arm/mach-realview/realview_pb11mp.c
index a98c536..c56bc8d 100644
--- a/arch/arm/mach-realview/realview_pb11mp.c
+++ b/arch/arm/mach-realview/realview_pb11mp.c
@@ -32,7 +32,6 @@
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
-#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
@@ -263,7 +262,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
diff --git a/arch/arm/mach-realview/realview_pba8.c b/arch/arm/mach-realview/realview_pba8.c
index 5965017..0409375 100644
--- a/arch/arm/mach-realview/realview_pba8.c
+++ b/arch/arm/mach-realview/realview_pba8.c
@@ -31,7 +31,6 @@
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
-#include <asm/pmu.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
@@ -241,7 +240,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = 1,
.resource = &pmu_resource,
};
diff --git a/arch/arm/mach-realview/realview_pbx.c b/arch/arm/mach-realview/realview_pbx.c
index 3f2f605..97885dc 100644
--- a/arch/arm/mach-realview/realview_pbx.c
+++ b/arch/arm/mach-realview/realview_pbx.c
@@ -30,7 +30,6 @@
#include <asm/irq.h>
#include <asm/leds.h>
#include <asm/mach-types.h>
-#include <asm/pmu.h>
#include <asm/smp_twd.h>
#include <asm/pgtable.h>
#include <asm/hardware/gic.h>
@@ -280,7 +279,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
diff --git a/arch/arm/mach-shmobile/board-kzm9g.c b/arch/arm/mach-shmobile/board-kzm9g.c
index 53b7ea9..fd21fb6 100644
--- a/arch/arm/mach-shmobile/board-kzm9g.c
+++ b/arch/arm/mach-shmobile/board-kzm9g.c
@@ -763,6 +763,13 @@
platform_add_devices(kzm_devices, ARRAY_SIZE(kzm_devices));
}
+static void kzm9g_restart(char mode, const char *cmd)
+{
+#define RESCNT2 0xe6188020
+ /* Do soft power on reset */
+ writel((1 << 31), RESCNT2);
+}
+
static const char *kzm9g_boards_compat_dt[] __initdata = {
"renesas,kzm9g",
NULL,
@@ -777,5 +784,6 @@
.init_machine = kzm_init,
.init_late = shmobile_init_late,
.timer = &shmobile_timer,
+ .restart = kzm9g_restart,
.dt_compat = kzm9g_boards_compat_dt,
MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-r8a7779.c b/arch/arm/mach-shmobile/clock-r8a7779.c
index 339c62c..3cafb6a 100644
--- a/arch/arm/mach-shmobile/clock-r8a7779.c
+++ b/arch/arm/mach-shmobile/clock-r8a7779.c
@@ -86,11 +86,16 @@
0x0300, CLK_ENABLE_ON_INIT),
};
-enum { MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
+enum { MSTP323, MSTP322, MSTP321, MSTP320,
+ MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
MSTP016, MSTP015, MSTP014,
MSTP_NR };
static struct clk mstp_clks[MSTP_NR] = {
+ [MSTP323] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 23, 0), /* SDHI0 */
+ [MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
+ [MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
+ [MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
[MSTP026] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 26, 0), /* SCIF0 */
[MSTP025] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 25, 0), /* SCIF1 */
[MSTP024] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 24, 0), /* SCIF2 */
@@ -149,6 +154,10 @@
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP023]), /* SCIF3 */
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP022]), /* SCIF4 */
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP021]), /* SCIF6 */
+ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP323]), /* SDHI0 */
+ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
+ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
+ CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
};
void __init r8a7779_clock_init(void)
diff --git a/arch/arm/mach-shmobile/setup-emev2.c b/arch/arm/mach-shmobile/setup-emev2.c
index dae9aa6..61446f3 100644
--- a/arch/arm/mach-shmobile/setup-emev2.c
+++ b/arch/arm/mach-shmobile/setup-emev2.c
@@ -356,6 +356,26 @@
},
};
+static struct resource pmu_resources[] = {
+ [0] = {
+ .start = 152,
+ .end = 152,
+ .flags = IORESOURCE_IRQ,
+ },
+ [1] = {
+ .start = 153,
+ .end = 153,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device pmu_device = {
+ .name = "arm-pmu",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(pmu_resources),
+ .resource = pmu_resources,
+};
+
static struct platform_device *emev2_early_devices[] __initdata = {
&uart0_device,
&uart1_device,
@@ -370,6 +390,7 @@
&gio2_device,
&gio3_device,
&gio4_device,
+ &pmu_device,
};
void __init emev2_add_standard_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index d230af6..38ed2dd 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -734,6 +734,26 @@
},
};
+static struct resource pmu_resources[] = {
+ [0] = {
+ .start = gic_spi(55),
+ .end = gic_spi(55),
+ .flags = IORESOURCE_IRQ,
+ },
+ [1] = {
+ .start = gic_spi(56),
+ .end = gic_spi(56),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device pmu_device = {
+ .name = "arm-pmu",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(pmu_resources),
+ .resource = pmu_resources,
+};
+
static struct platform_device *sh73a0_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
@@ -757,6 +777,7 @@
&i2c4_device,
&dma0_device,
&mpdma0_device,
+ &pmu_device,
};
#define SRCR2 0xe61580b0
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index c3d7303..84d21f5 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -12,9 +12,13 @@
obj-y += apbio.o
obj-$(CONFIG_CPU_IDLE) += cpuidle.o
obj-$(CONFIG_CPU_IDLE) += sleep.o
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra20_clocks_data.o
obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += tegra2_emc.o
+obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += sleep-t20.o
obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += tegra30_clocks_data.o
+obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += sleep-t30.o
obj-$(CONFIG_SMP) += platsmp.o headsmp.o
obj-$(CONFIG_SMP) += reset.o
obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/board-dt-tegra20.c
index c099963..b4e7cc1 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/board-dt-tegra20.c
@@ -71,6 +71,7 @@
static __initdata struct tegra_clk_init_table tegra_dt_clk_init_table[] = {
/* name parent rate enabled */
+ { "uarta", "pll_p", 216000000, true },
{ "uartd", "pll_p", 216000000, true },
{ "usbd", "clk_m", 12000000, false },
{ "usb2", "clk_m", 12000000, false },
diff --git a/arch/arm/mach-tegra/clock.c b/arch/arm/mach-tegra/clock.c
index 58f981c..fd82085 100644
--- a/arch/arm/mach-tegra/clock.c
+++ b/arch/arm/mach-tegra/clock.c
@@ -1,6 +1,7 @@
/*
*
* Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Colin Cross <ccross@google.com>
@@ -19,8 +20,6 @@
#include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/clkdev.h>
-#include <linux/debugfs.h>
-#include <linux/delay.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/module.h>
@@ -32,44 +31,38 @@
#include "board.h"
#include "clock.h"
+#include "tegra_cpu_car.h"
+
+/* Global data of Tegra CPU CAR ops */
+struct tegra_cpu_car_ops *tegra_cpu_car_ops;
/*
* Locking:
*
- * Each struct clk has a spinlock.
- *
- * To avoid AB-BA locking problems, locks must always be traversed from child
- * clock to parent clock. For example, when enabling a clock, the clock's lock
- * is taken, and then clk_enable is called on the parent, which take's the
- * parent clock's lock. There is one exceptions to this ordering: When dumping
- * the clock tree through debugfs. In this case, clk_lock_all is called,
- * which attemps to iterate through the entire list of clocks and take every
- * clock lock. If any call to spin_trylock fails, all locked clocks are
- * unlocked, and the process is retried. When all the locks are held,
- * the only clock operation that can be called is clk_get_rate_all_locked.
- *
- * Within a single clock, no clock operation can call another clock operation
- * on itself, except for clk_get_rate_locked and clk_set_rate_locked. Any
- * clock operation can call any other clock operation on any of it's possible
- * parents.
- *
* An additional mutex, clock_list_lock, is used to protect the list of all
* clocks.
*
- * The clock operations must lock internally to protect against
- * read-modify-write on registers that are shared by multiple clocks
*/
static DEFINE_MUTEX(clock_list_lock);
static LIST_HEAD(clocks);
+void tegra_clk_add(struct clk *clk)
+{
+ struct clk_tegra *c = to_clk_tegra(__clk_get_hw(clk));
+
+ mutex_lock(&clock_list_lock);
+ list_add(&c->node, &clocks);
+ mutex_unlock(&clock_list_lock);
+}
+
struct clk *tegra_get_clock_by_name(const char *name)
{
- struct clk *c;
+ struct clk_tegra *c;
struct clk *ret = NULL;
mutex_lock(&clock_list_lock);
list_for_each_entry(c, &clocks, node) {
- if (strcmp(c->name, name) == 0) {
- ret = c;
+ if (strcmp(__clk_get_name(c->hw.clk), name) == 0) {
+ ret = c->hw.clk;
break;
}
}
@@ -77,280 +70,36 @@
return ret;
}
-/* Must be called with c->spinlock held */
-static unsigned long clk_predict_rate_from_parent(struct clk *c, struct clk *p)
-{
- u64 rate;
-
- rate = clk_get_rate(p);
-
- if (c->mul != 0 && c->div != 0) {
- rate *= c->mul;
- rate += c->div - 1; /* round up */
- do_div(rate, c->div);
- }
-
- return rate;
-}
-
-/* Must be called with c->spinlock held */
-unsigned long clk_get_rate_locked(struct clk *c)
-{
- unsigned long rate;
-
- if (c->parent)
- rate = clk_predict_rate_from_parent(c, c->parent);
- else
- rate = c->rate;
-
- return rate;
-}
-
-unsigned long clk_get_rate(struct clk *c)
-{
- unsigned long flags;
- unsigned long rate;
-
- spin_lock_irqsave(&c->spinlock, flags);
-
- rate = clk_get_rate_locked(c);
-
- spin_unlock_irqrestore(&c->spinlock, flags);
-
- return rate;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_reparent(struct clk *c, struct clk *parent)
-{
- c->parent = parent;
- return 0;
-}
-
-void clk_init(struct clk *c)
-{
- spin_lock_init(&c->spinlock);
-
- if (c->ops && c->ops->init)
- c->ops->init(c);
-
- if (!c->ops || !c->ops->enable) {
- c->refcnt++;
- c->set = true;
- if (c->parent)
- c->state = c->parent->state;
- else
- c->state = ON;
- }
-
- mutex_lock(&clock_list_lock);
- list_add(&c->node, &clocks);
- mutex_unlock(&clock_list_lock);
-}
-
-int clk_enable(struct clk *c)
-{
- int ret = 0;
- unsigned long flags;
-
- spin_lock_irqsave(&c->spinlock, flags);
-
- if (c->refcnt == 0) {
- if (c->parent) {
- ret = clk_enable(c->parent);
- if (ret)
- goto out;
- }
-
- if (c->ops && c->ops->enable) {
- ret = c->ops->enable(c);
- if (ret) {
- if (c->parent)
- clk_disable(c->parent);
- goto out;
- }
- c->state = ON;
- c->set = true;
- }
- }
- c->refcnt++;
-out:
- spin_unlock_irqrestore(&c->spinlock, flags);
- return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-void clk_disable(struct clk *c)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&c->spinlock, flags);
-
- if (c->refcnt == 0) {
- WARN(1, "Attempting to disable clock %s with refcnt 0", c->name);
- spin_unlock_irqrestore(&c->spinlock, flags);
- return;
- }
- if (c->refcnt == 1) {
- if (c->ops && c->ops->disable)
- c->ops->disable(c);
-
- if (c->parent)
- clk_disable(c->parent);
-
- c->state = OFF;
- }
- c->refcnt--;
-
- spin_unlock_irqrestore(&c->spinlock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-int clk_set_parent(struct clk *c, struct clk *parent)
-{
- int ret;
- unsigned long flags;
- unsigned long new_rate;
- unsigned long old_rate;
-
- spin_lock_irqsave(&c->spinlock, flags);
-
- if (!c->ops || !c->ops->set_parent) {
- ret = -ENOSYS;
- goto out;
- }
-
- new_rate = clk_predict_rate_from_parent(c, parent);
- old_rate = clk_get_rate_locked(c);
-
- ret = c->ops->set_parent(c, parent);
- if (ret)
- goto out;
-
-out:
- spin_unlock_irqrestore(&c->spinlock, flags);
- return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *c)
-{
- return c->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-int clk_set_rate_locked(struct clk *c, unsigned long rate)
-{
- long new_rate;
-
- if (!c->ops || !c->ops->set_rate)
- return -ENOSYS;
-
- if (rate > c->max_rate)
- rate = c->max_rate;
-
- if (c->ops && c->ops->round_rate) {
- new_rate = c->ops->round_rate(c, rate);
-
- if (new_rate < 0)
- return new_rate;
-
- rate = new_rate;
- }
-
- return c->ops->set_rate(c, rate);
-}
-
-int clk_set_rate(struct clk *c, unsigned long rate)
-{
- int ret;
- unsigned long flags;
-
- spin_lock_irqsave(&c->spinlock, flags);
-
- ret = clk_set_rate_locked(c, rate);
-
- spin_unlock_irqrestore(&c->spinlock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-
-/* Must be called with clocks lock and all indvidual clock locks held */
-unsigned long clk_get_rate_all_locked(struct clk *c)
-{
- u64 rate;
- int mul = 1;
- int div = 1;
- struct clk *p = c;
-
- while (p) {
- c = p;
- if (c->mul != 0 && c->div != 0) {
- mul *= c->mul;
- div *= c->div;
- }
- p = c->parent;
- }
-
- rate = c->rate;
- rate *= mul;
- do_div(rate, div);
-
- return rate;
-}
-
-long clk_round_rate(struct clk *c, unsigned long rate)
-{
- unsigned long flags;
- long ret;
-
- spin_lock_irqsave(&c->spinlock, flags);
-
- if (!c->ops || !c->ops->round_rate) {
- ret = -ENOSYS;
- goto out;
- }
-
- if (rate > c->max_rate)
- rate = c->max_rate;
-
- ret = c->ops->round_rate(c, rate);
-
-out:
- spin_unlock_irqrestore(&c->spinlock, flags);
- return ret;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
static int tegra_clk_init_one_from_table(struct tegra_clk_init_table *table)
{
struct clk *c;
struct clk *p;
+ struct clk *parent;
int ret = 0;
c = tegra_get_clock_by_name(table->name);
if (!c) {
- pr_warning("Unable to initialize clock %s\n",
+ pr_warn("Unable to initialize clock %s\n",
table->name);
return -ENODEV;
}
+ parent = clk_get_parent(c);
+
if (table->parent) {
p = tegra_get_clock_by_name(table->parent);
if (!p) {
- pr_warning("Unable to find parent %s of clock %s\n",
+ pr_warn("Unable to find parent %s of clock %s\n",
table->parent, table->name);
return -ENODEV;
}
- if (c->parent != p) {
+ if (parent != p) {
ret = clk_set_parent(c, p);
if (ret) {
- pr_warning("Unable to set parent %s of clock %s: %d\n",
+ pr_warn("Unable to set parent %s of clock %s: %d\n",
table->parent, table->name, ret);
return -EINVAL;
}
@@ -360,16 +109,16 @@
if (table->rate && table->rate != clk_get_rate(c)) {
ret = clk_set_rate(c, table->rate);
if (ret) {
- pr_warning("Unable to set clock %s to rate %lu: %d\n",
+ pr_warn("Unable to set clock %s to rate %lu: %d\n",
table->name, table->rate, ret);
return -EINVAL;
}
}
if (table->enabled) {
- ret = clk_enable(c);
+ ret = clk_prepare_enable(c);
if (ret) {
- pr_warning("Unable to enable clock %s: %d\n",
+ pr_warn("Unable to enable clock %s: %d\n",
table->name, ret);
return -EINVAL;
}
@@ -383,19 +132,20 @@
for (; table->name; table++)
tegra_clk_init_one_from_table(table);
}
-EXPORT_SYMBOL(tegra_clk_init_from_table);
void tegra_periph_reset_deassert(struct clk *c)
{
- BUG_ON(!c->ops->reset);
- c->ops->reset(c, false);
+ struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
+ BUG_ON(!clk->reset);
+ clk->reset(__clk_get_hw(c), false);
}
EXPORT_SYMBOL(tegra_periph_reset_deassert);
void tegra_periph_reset_assert(struct clk *c)
{
- BUG_ON(!c->ops->reset);
- c->ops->reset(c, true);
+ struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
+ BUG_ON(!clk->reset);
+ clk->reset(__clk_get_hw(c), true);
}
EXPORT_SYMBOL(tegra_periph_reset_assert);
@@ -405,268 +155,14 @@
int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
{
int ret = 0;
- unsigned long flags;
+ struct clk_tegra *clk = to_clk_tegra(__clk_get_hw(c));
- spin_lock_irqsave(&c->spinlock, flags);
-
- if (!c->ops || !c->ops->clk_cfg_ex) {
+ if (!clk->clk_cfg_ex) {
ret = -ENOSYS;
goto out;
}
- ret = c->ops->clk_cfg_ex(c, p, setting);
+ ret = clk->clk_cfg_ex(__clk_get_hw(c), p, setting);
out:
- spin_unlock_irqrestore(&c->spinlock, flags);
-
return ret;
}
-
-#ifdef CONFIG_DEBUG_FS
-
-static int __clk_lock_all_spinlocks(void)
-{
- struct clk *c;
-
- list_for_each_entry(c, &clocks, node)
- if (!spin_trylock(&c->spinlock))
- goto unlock_spinlocks;
-
- return 0;
-
-unlock_spinlocks:
- list_for_each_entry_continue_reverse(c, &clocks, node)
- spin_unlock(&c->spinlock);
-
- return -EAGAIN;
-}
-
-static void __clk_unlock_all_spinlocks(void)
-{
- struct clk *c;
-
- list_for_each_entry_reverse(c, &clocks, node)
- spin_unlock(&c->spinlock);
-}
-
-/*
- * This function retries until it can take all locks, and may take
- * an arbitrarily long time to complete.
- * Must be called with irqs enabled, returns with irqs disabled
- * Must be called with clock_list_lock held
- */
-static void clk_lock_all(void)
-{
- int ret;
-retry:
- local_irq_disable();
-
- ret = __clk_lock_all_spinlocks();
- if (ret)
- goto failed_spinlocks;
-
- /* All locks taken successfully, return */
- return;
-
-failed_spinlocks:
- local_irq_enable();
- yield();
- goto retry;
-}
-
-/*
- * Unlocks all clocks after a clk_lock_all
- * Must be called with irqs disabled, returns with irqs enabled
- * Must be called with clock_list_lock held
- */
-static void clk_unlock_all(void)
-{
- __clk_unlock_all_spinlocks();
-
- local_irq_enable();
-}
-
-static struct dentry *clk_debugfs_root;
-
-
-static void clock_tree_show_one(struct seq_file *s, struct clk *c, int level)
-{
- struct clk *child;
- const char *state = "uninit";
- char div[8] = {0};
-
- if (c->state == ON)
- state = "on";
- else if (c->state == OFF)
- state = "off";
-
- if (c->mul != 0 && c->div != 0) {
- if (c->mul > c->div) {
- int mul = c->mul / c->div;
- int mul2 = (c->mul * 10 / c->div) % 10;
- int mul3 = (c->mul * 10) % c->div;
- if (mul2 == 0 && mul3 == 0)
- snprintf(div, sizeof(div), "x%d", mul);
- else if (mul3 == 0)
- snprintf(div, sizeof(div), "x%d.%d", mul, mul2);
- else
- snprintf(div, sizeof(div), "x%d.%d..", mul, mul2);
- } else {
- snprintf(div, sizeof(div), "%d%s", c->div / c->mul,
- (c->div % c->mul) ? ".5" : "");
- }
- }
-
- seq_printf(s, "%*s%c%c%-*s %-6s %-3d %-8s %-10lu\n",
- level * 3 + 1, "",
- c->rate > c->max_rate ? '!' : ' ',
- !c->set ? '*' : ' ',
- 30 - level * 3, c->name,
- state, c->refcnt, div, clk_get_rate_all_locked(c));
-
- list_for_each_entry(child, &clocks, node) {
- if (child->parent != c)
- continue;
-
- clock_tree_show_one(s, child, level + 1);
- }
-}
-
-static int clock_tree_show(struct seq_file *s, void *data)
-{
- struct clk *c;
- seq_printf(s, " clock state ref div rate\n");
- seq_printf(s, "--------------------------------------------------------------\n");
-
- mutex_lock(&clock_list_lock);
-
- clk_lock_all();
-
- list_for_each_entry(c, &clocks, node)
- if (c->parent == NULL)
- clock_tree_show_one(s, c, 0);
-
- clk_unlock_all();
-
- mutex_unlock(&clock_list_lock);
- return 0;
-}
-
-static int clock_tree_open(struct inode *inode, struct file *file)
-{
- return single_open(file, clock_tree_show, inode->i_private);
-}
-
-static const struct file_operations clock_tree_fops = {
- .open = clock_tree_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int possible_parents_show(struct seq_file *s, void *data)
-{
- struct clk *c = s->private;
- int i;
-
- for (i = 0; c->inputs[i].input; i++) {
- char *first = (i == 0) ? "" : " ";
- seq_printf(s, "%s%s", first, c->inputs[i].input->name);
- }
- seq_printf(s, "\n");
- return 0;
-}
-
-static int possible_parents_open(struct inode *inode, struct file *file)
-{
- return single_open(file, possible_parents_show, inode->i_private);
-}
-
-static const struct file_operations possible_parents_fops = {
- .open = possible_parents_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int clk_debugfs_register_one(struct clk *c)
-{
- struct dentry *d;
-
- d = debugfs_create_dir(c->name, clk_debugfs_root);
- if (!d)
- return -ENOMEM;
- c->dent = d;
-
- d = debugfs_create_u8("refcnt", S_IRUGO, c->dent, (u8 *)&c->refcnt);
- if (!d)
- goto err_out;
-
- d = debugfs_create_u32("rate", S_IRUGO, c->dent, (u32 *)&c->rate);
- if (!d)
- goto err_out;
-
- d = debugfs_create_x32("flags", S_IRUGO, c->dent, (u32 *)&c->flags);
- if (!d)
- goto err_out;
-
- if (c->inputs) {
- d = debugfs_create_file("possible_parents", S_IRUGO, c->dent,
- c, &possible_parents_fops);
- if (!d)
- goto err_out;
- }
-
- return 0;
-
-err_out:
- debugfs_remove_recursive(c->dent);
- return -ENOMEM;
-}
-
-static int clk_debugfs_register(struct clk *c)
-{
- int err;
- struct clk *pa = c->parent;
-
- if (pa && !pa->dent) {
- err = clk_debugfs_register(pa);
- if (err)
- return err;
- }
-
- if (!c->dent) {
- err = clk_debugfs_register_one(c);
- if (err)
- return err;
- }
- return 0;
-}
-
-int __init tegra_clk_debugfs_init(void)
-{
- struct clk *c;
- struct dentry *d;
- int err = -ENOMEM;
-
- d = debugfs_create_dir("clock", NULL);
- if (!d)
- return -ENOMEM;
- clk_debugfs_root = d;
-
- d = debugfs_create_file("clock_tree", S_IRUGO, clk_debugfs_root, NULL,
- &clock_tree_fops);
- if (!d)
- goto err_out;
-
- list_for_each_entry(c, &clocks, node) {
- err = clk_debugfs_register(c);
- if (err)
- goto err_out;
- }
- return 0;
-err_out:
- debugfs_remove_recursive(clk_debugfs_root);
- return err;
-}
-
-#endif
diff --git a/arch/arm/mach-tegra/clock.h b/arch/arm/mach-tegra/clock.h
index bc30065..2aa37f5 100644
--- a/arch/arm/mach-tegra/clock.h
+++ b/arch/arm/mach-tegra/clock.h
@@ -2,6 +2,7 @@
* arch/arm/mach-tegra/include/mach/clock.h
*
* Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
*
* Author:
* Colin Cross <ccross@google.com>
@@ -20,9 +21,9 @@
#ifndef __MACH_TEGRA_CLOCK_H
#define __MACH_TEGRA_CLOCK_H
+#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <linux/list.h>
-#include <linux/spinlock.h>
#include <mach/clk.h>
@@ -52,7 +53,8 @@
#define ENABLE_ON_INIT (1 << 28)
#define PERIPH_ON_APB (1 << 29)
-struct clk;
+struct clk_tegra;
+#define to_clk_tegra(_hw) container_of(_hw, struct clk_tegra, hw)
struct clk_mux_sel {
struct clk *input;
@@ -68,47 +70,29 @@
u8 cpcon;
};
-struct clk_ops {
- void (*init)(struct clk *);
- int (*enable)(struct clk *);
- void (*disable)(struct clk *);
- int (*set_parent)(struct clk *, struct clk *);
- int (*set_rate)(struct clk *, unsigned long);
- long (*round_rate)(struct clk *, unsigned long);
- void (*reset)(struct clk *, bool);
- int (*clk_cfg_ex)(struct clk *,
- enum tegra_clk_ex_param, u32);
-};
-
enum clk_state {
UNINITIALIZED = 0,
ON,
OFF,
};
-struct clk {
+struct clk_tegra {
/* node for master clocks list */
- struct list_head node; /* node for list of all clocks */
+ struct list_head node; /* node for list of all clocks */
struct clk_lookup lookup;
+ struct clk_hw hw;
-#ifdef CONFIG_DEBUG_FS
- struct dentry *dent;
-#endif
bool set;
- struct clk_ops *ops;
- unsigned long rate;
+ unsigned long fixed_rate;
unsigned long max_rate;
unsigned long min_rate;
u32 flags;
const char *name;
- u32 refcnt;
enum clk_state state;
- struct clk *parent;
u32 div;
u32 mul;
- const struct clk_mux_sel *inputs;
u32 reg;
u32 reg_shift;
@@ -144,7 +128,8 @@
} shared_bus_user;
} u;
- spinlock_t spinlock;
+ void (*reset)(struct clk_hw *, bool);
+ int (*clk_cfg_ex)(struct clk_hw *, enum tegra_clk_ex_param, u32);
};
struct clk_duplicate {
@@ -159,13 +144,10 @@
bool enabled;
};
+void tegra_clk_add(struct clk *c);
void tegra2_init_clocks(void);
void tegra30_init_clocks(void);
-void clk_init(struct clk *clk);
struct clk *tegra_get_clock_by_name(const char *name);
-int clk_reparent(struct clk *c, struct clk *parent);
void tegra_clk_init_from_table(struct tegra_clk_init_table *table);
-unsigned long clk_get_rate_locked(struct clk *c);
-int clk_set_rate_locked(struct clk *c, unsigned long rate);
#endif
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 96fef6b..0560538 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -34,6 +34,7 @@
#include "fuse.h"
#include "pmc.h"
#include "apbio.h"
+#include "sleep.h"
/*
* Storage for debug-macro.S's state.
@@ -135,6 +136,7 @@
tegra_init_cache(0x331, 0x441);
tegra_pmc_init();
tegra_powergate_init();
+ tegra20_hotplug_init();
}
#endif
#ifdef CONFIG_ARCH_TEGRA_3x_SOC
@@ -147,11 +149,11 @@
tegra_init_cache(0x441, 0x551);
tegra_pmc_init();
tegra_powergate_init();
+ tegra30_hotplug_init();
}
#endif
void __init tegra_init_late(void)
{
- tegra_clk_debugfs_init();
tegra_powergate_debugfs_init();
}
diff --git a/arch/arm/mach-tegra/cpu-tegra.c b/arch/arm/mach-tegra/cpu-tegra.c
index ceb52db..627bf0f 100644
--- a/arch/arm/mach-tegra/cpu-tegra.c
+++ b/arch/arm/mach-tegra/cpu-tegra.c
@@ -49,6 +49,8 @@
#define NUM_CPUS 2
static struct clk *cpu_clk;
+static struct clk *pll_x_clk;
+static struct clk *pll_p_clk;
static struct clk *emc_clk;
static unsigned long target_cpu_speed[NUM_CPUS];
@@ -71,6 +73,42 @@
return rate;
}
+static int tegra_cpu_clk_set_rate(unsigned long rate)
+{
+ int ret;
+
+ /*
+ * Take an extra reference to the main pll so it doesn't turn
+ * off when we move the cpu off of it
+ */
+ clk_prepare_enable(pll_x_clk);
+
+ ret = clk_set_parent(cpu_clk, pll_p_clk);
+ if (ret) {
+ pr_err("Failed to switch cpu to clock pll_p\n");
+ goto out;
+ }
+
+ if (rate == clk_get_rate(pll_p_clk))
+ goto out;
+
+ ret = clk_set_rate(pll_x_clk, rate);
+ if (ret) {
+ pr_err("Failed to change pll_x to %lu\n", rate);
+ goto out;
+ }
+
+ ret = clk_set_parent(cpu_clk, pll_x_clk);
+ if (ret) {
+ pr_err("Failed to switch cpu to clock pll_x\n");
+ goto out;
+ }
+
+out:
+ clk_disable_unprepare(pll_x_clk);
+ return ret;
+}
+
static int tegra_update_cpu_speed(unsigned long rate)
{
int ret = 0;
@@ -101,7 +139,7 @@
freqs.old, freqs.new);
#endif
- ret = clk_set_rate(cpu_clk, freqs.new * 1000);
+ ret = tegra_cpu_clk_set_rate(freqs.new * 1000);
if (ret) {
pr_err("cpu-tegra: Failed to set cpu frequency to %d kHz\n",
freqs.new);
@@ -183,6 +221,14 @@
if (IS_ERR(cpu_clk))
return PTR_ERR(cpu_clk);
+ pll_x_clk = clk_get_sys(NULL, "pll_x");
+ if (IS_ERR(pll_x_clk))
+ return PTR_ERR(pll_x_clk);
+
+ pll_p_clk = clk_get_sys(NULL, "pll_p");
+ if (IS_ERR(pll_p_clk))
+ return PTR_ERR(pll_p_clk);
+
emc_clk = clk_get_sys("cpu", "emc");
if (IS_ERR(emc_clk)) {
clk_put(cpu_clk);
diff --git a/arch/arm/mach-tegra/devices.c b/arch/arm/mach-tegra/devices.c
index c70e65f..61e9603 100644
--- a/arch/arm/mach-tegra/devices.c
+++ b/arch/arm/mach-tegra/devices.c
@@ -23,7 +23,6 @@
#include <linux/fsl_devices.h>
#include <linux/serial_8250.h>
#include <linux/i2c-tegra.h>
-#include <asm/pmu.h>
#include <mach/irqs.h>
#include <mach/iomap.h>
#include <mach/dma.h>
@@ -516,7 +515,7 @@
struct platform_device tegra_pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(tegra_pmu_resources),
.resource = tegra_pmu_resources,
};
diff --git a/arch/arm/mach-tegra/headsmp.S b/arch/arm/mach-tegra/headsmp.S
index fef9c2c..6addc78 100644
--- a/arch/arm/mach-tegra/headsmp.S
+++ b/arch/arm/mach-tegra/headsmp.S
@@ -7,17 +7,13 @@
#include "flowctrl.h"
#include "reset.h"
+#include "sleep.h"
#define APB_MISC_GP_HIDREV 0x804
#define PMC_SCRATCH41 0x140
#define RESET_DATA(x) ((TEGRA_RESET_##x)*4)
- .macro mov32, reg, val
- movw \reg, #:lower16:\val
- movt \reg, #:upper16:\val
- .endm
-
.section ".text.head", "ax"
__CPUINIT
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index d8dc9dd..d02a354 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,91 +1,23 @@
/*
- * linux/arch/arm/mach-realview/hotplug.c
*
* Copyright (C) 2002 ARM Ltd.
* All Rights Reserved
+ * Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
-#include <linux/errno.h>
#include <linux/smp.h>
#include <asm/cacheflush.h>
-#include <asm/cp15.h>
+#include <asm/smp_plat.h>
-static inline void cpu_enter_lowpower(void)
-{
- unsigned int v;
+#include "sleep.h"
+#include "tegra_cpu_car.h"
- flush_cache_all();
- asm volatile(
- " mcr p15, 0, %1, c7, c5, 0\n"
- " mcr p15, 0, %1, c7, c10, 4\n"
- /*
- * Turn off coherency
- */
- " mrc p15, 0, %0, c1, c0, 1\n"
- " bic %0, %0, #0x20\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- " mrc p15, 0, %0, c1, c0, 0\n"
- " bic %0, %0, %2\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- : "=&r" (v)
- : "r" (0), "Ir" (CR_C)
- : "cc");
-}
-
-static inline void cpu_leave_lowpower(void)
-{
- unsigned int v;
-
- asm volatile(
- "mrc p15, 0, %0, c1, c0, 0\n"
- " orr %0, %0, %1\n"
- " mcr p15, 0, %0, c1, c0, 0\n"
- " mrc p15, 0, %0, c1, c0, 1\n"
- " orr %0, %0, #0x20\n"
- " mcr p15, 0, %0, c1, c0, 1\n"
- : "=&r" (v)
- : "Ir" (CR_C)
- : "cc");
-}
-
-static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
-{
- /*
- * there is no power-control hardware on this platform, so all
- * we can do is put the core into WFI; this is safe as the calling
- * code will have already disabled interrupts
- */
- for (;;) {
- /*
- * here's the WFI
- */
- asm(".word 0xe320f003\n"
- :
- :
- : "memory", "cc");
-
- /*if (pen_release == cpu) {*/
- /*
- * OK, proper wakeup, we're done
- */
- break;
- /*}*/
-
- /*
- * Getting here, means that we have come out of WFI without
- * having been woken up - this shouldn't happen
- *
- * Just note it happening - when we're woken, we can report
- * its occurrence.
- */
- (*spurious)++;
- }
-}
+static void (*tegra_hotplug_shutdown)(void);
int platform_cpu_kill(unsigned int cpu)
{
@@ -99,22 +31,20 @@
*/
void platform_cpu_die(unsigned int cpu)
{
- int spurious = 0;
+ cpu = cpu_logical_map(cpu);
- /*
- * we're ready for shutdown now, so do it
- */
- cpu_enter_lowpower();
- platform_do_lowpower(cpu, &spurious);
+ /* Flush the L1 data cache. */
+ flush_cache_all();
- /*
- * bring this CPU back into the world of cache
- * coherency, and then restore interrupts
- */
- cpu_leave_lowpower();
+ /* Shut down the current CPU. */
+ tegra_hotplug_shutdown();
- if (spurious)
- pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
+ /* Clock gate the CPU */
+ tegra_wait_cpu_in_reset(cpu);
+ tegra_disable_cpu_clock(cpu);
+
+ /* Should never return here. */
+ BUG();
}
int platform_cpu_disable(unsigned int cpu)
@@ -125,3 +55,19 @@
*/
return cpu == 0 ? -EPERM : 0;
}
+
+#ifdef CONFIG_ARCH_TEGRA_2x_SOC
+extern void tegra20_hotplug_shutdown(void);
+void __init tegra20_hotplug_init(void)
+{
+ tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+}
+#endif
+
+#ifdef CONFIG_ARCH_TEGRA_3x_SOC
+extern void tegra30_hotplug_shutdown(void);
+void __init tegra30_hotplug_init(void)
+{
+ tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+}
+#endif
diff --git a/arch/arm/mach-tegra/include/mach/clk.h b/arch/arm/mach-tegra/include/mach/clk.h
index d97e403..95f3a54 100644
--- a/arch/arm/mach-tegra/include/mach/clk.h
+++ b/arch/arm/mach-tegra/include/mach/clk.h
@@ -34,7 +34,10 @@
void tegra_periph_reset_deassert(struct clk *c);
void tegra_periph_reset_assert(struct clk *c);
+#ifndef CONFIG_COMMON_CLK
unsigned long clk_get_rate_all_locked(struct clk *c);
+#endif
+
void tegra2_sdmmc_tap_delay(struct clk *c, int delay);
int tegra_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting);
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index 1a208db..96ed171 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -31,6 +31,7 @@
#include "fuse.h"
#include "flowctrl.h"
#include "reset.h"
+#include "tegra_cpu_car.h"
extern void tegra_secondary_startup(void);
@@ -38,17 +39,6 @@
#define EVP_CPU_RESET_VECTOR \
(IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX \
- (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x4c)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET \
- (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x340)
-#define CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR \
- (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x344)
-#define CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR \
- (IO_ADDRESS(TEGRA_CLK_RESET_BASE) + 0x34c)
-
-#define CPU_CLOCK(cpu) (0x1<<(8+cpu))
-#define CPU_RESET(cpu) (0x1111ul<<(cpu))
void __cpuinit platform_secondary_init(unsigned int cpu)
{
@@ -63,13 +53,8 @@
static int tegra20_power_up_cpu(unsigned int cpu)
{
- u32 reg;
-
/* Enable the CPU clock. */
- reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
- writel(reg & ~CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
- barrier();
- reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+ tegra_enable_cpu_clock(cpu);
/* Clear flow controller CSR. */
flowctrl_write_cpu_csr(cpu, 0);
@@ -79,7 +64,6 @@
static int tegra30_power_up_cpu(unsigned int cpu)
{
- u32 reg;
int ret, pwrgateid;
unsigned long timeout;
@@ -103,8 +87,7 @@
}
/* CPU partition is powered. Enable the CPU clock. */
- writel(CPU_CLOCK(cpu), CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
- reg = readl(CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+ tegra_enable_cpu_clock(cpu);
udelay(10);
/* Remove I/O clamps. */
@@ -128,8 +111,7 @@
* via the flow controller). This will have no effect on first boot
* of the CPU since it should already be in reset.
*/
- writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
- dmb();
+ tegra_put_cpu_in_reset(cpu);
/*
* Unhalt the CPU. If the flow controller was used to power-gate the
@@ -155,8 +137,7 @@
goto done;
/* Take the CPU out of reset. */
- writel(CPU_RESET(cpu), CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
- wmb();
+ tegra_cpu_out_of_reset(cpu);
done:
return status;
}
diff --git a/arch/arm/mach-tegra/sleep-t20.S b/arch/arm/mach-tegra/sleep-t20.S
new file mode 100644
index 0000000..a36ae41
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t20.S
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2011, Google, Inc.
+ *
+ * Author: Colin Cross <ccross@android.com>
+ * Gary King <gking@nvidia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra20_hotplug_shutdown(void)
+ *
+ * puts the current cpu in reset
+ * should never return
+ */
+ENTRY(tegra20_hotplug_shutdown)
+ /* Turn off SMP coherency */
+ exit_smp r4, r5
+
+ /* Put this CPU down */
+ cpu_id r0
+ bl tegra20_cpu_shutdown
+ mov pc, lr @ should never get here
+ENDPROC(tegra20_hotplug_shutdown)
+
+/*
+ * tegra20_cpu_shutdown(int cpu)
+ *
+ * r0 is cpu to reset
+ *
+ * puts the specified CPU in wait-for-event mode on the flow controller
+ * and puts the CPU in reset
+ * can be called on the current cpu or another cpu
+ * if called on the current cpu, does not return
+ * MUST NOT BE CALLED FOR CPU 0.
+ *
+ * corrupts r0-r3, r12
+ */
+ENTRY(tegra20_cpu_shutdown)
+ cmp r0, #0
+ moveq pc, lr @ must not be called for CPU 0
+
+ cpu_to_halt_reg r1, r0
+ ldr r3, =TEGRA_FLOW_CTRL_VIRT
+ mov r2, #FLOW_CTRL_WAITEVENT | FLOW_CTRL_JTAG_RESUME
+ str r2, [r3, r1] @ put flow controller in wait event mode
+ ldr r2, [r3, r1]
+ isb
+ dsb
+ movw r1, 0x1011
+ mov r1, r1, lsl r0
+ ldr r3, =TEGRA_CLK_RESET_VIRT
+ str r1, [r3, #0x340] @ put slave CPU in reset
+ isb
+ dsb
+ cpu_id r3
+ cmp r3, r0
+ beq .
+ mov pc, lr
+ENDPROC(tegra20_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep-t30.S b/arch/arm/mach-tegra/sleep-t30.S
new file mode 100644
index 0000000..777d9ce
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep-t30.S
@@ -0,0 +1,107 @@
+/*
+ * Copyright (c) 2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/linkage.h>
+
+#include <asm/assembler.h>
+
+#include <mach/iomap.h>
+
+#include "sleep.h"
+#include "flowctrl.h"
+
+#define TEGRA30_POWER_HOTPLUG_SHUTDOWN (1 << 27) /* Hotplug shutdown */
+
+#if defined(CONFIG_HOTPLUG_CPU) || defined(CONFIG_PM_SLEEP)
+/*
+ * tegra30_hotplug_shutdown(void)
+ *
+ * Powergates the current CPU.
+ * Should never return.
+ */
+ENTRY(tegra30_hotplug_shutdown)
+ /* Turn off SMP coherency */
+ exit_smp r4, r5
+
+ /* Powergate this CPU */
+ mov r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+ bl tegra30_cpu_shutdown
+ mov pc, lr @ should never get here
+ENDPROC(tegra30_hotplug_shutdown)
+
+/*
+ * tegra30_cpu_shutdown(unsigned long flags)
+ *
+ * Puts the current CPU in wait-for-event mode on the flow controller
+ * and powergates it -- flags (in R0) indicate the request type.
+ * Must never be called for CPU 0.
+ *
+ * corrupts r0-r4, r12
+ */
+ENTRY(tegra30_cpu_shutdown)
+ cpu_id r3
+ cmp r3, #0
+ moveq pc, lr @ Must never be called for CPU 0
+
+ ldr r12, =TEGRA_FLOW_CTRL_VIRT
+ cpu_to_csr_reg r1, r3
+ add r1, r1, r12 @ virtual CSR address for this CPU
+ cpu_to_halt_reg r2, r3
+ add r2, r2, r12 @ virtual HALT_EVENTS address for this CPU
+
+ /*
+ * Clear this CPU's "event" and "interrupt" flags and power gate
+ * it when halting but not before it is in the "WFE" state.
+ */
+ movw r12, \
+ FLOW_CTRL_CSR_INTR_FLAG | FLOW_CTRL_CSR_EVENT_FLAG | \
+ FLOW_CTRL_CSR_ENABLE
+ mov r4, #(1 << 4)
+ orr r12, r12, r4, lsl r3
+ str r12, [r1]
+
+ /* Halt this CPU. */
+ mov r3, #0x400
+delay_1:
+ subs r3, r3, #1 @ delay as a part of wfe war.
+ bge delay_1;
+ cpsid a @ disable imprecise aborts.
+ ldr r3, [r1] @ read CSR
+ str r3, [r1] @ clear CSR
+ tst r0, #TEGRA30_POWER_HOTPLUG_SHUTDOWN
+ movne r3, #FLOW_CTRL_WAITEVENT @ For hotplug
+ str r3, [r2]
+ ldr r0, [r2]
+ b wfe_war
+
+__cpu_reset_again:
+ dsb
+ .align 5
+ wfe @ CPU should be power gated here
+wfe_war:
+ b __cpu_reset_again
+
+ /*
+ * 38 nop's, which fills reset of wfe cache line and
+ * 4 more cachelines with nop
+ */
+ .rept 38
+ nop
+ .endr
+ b . @ should never get here
+
+ENDPROC(tegra30_cpu_shutdown)
+#endif
diff --git a/arch/arm/mach-tegra/sleep.S b/arch/arm/mach-tegra/sleep.S
index d29b156..ea81554 100644
--- a/arch/arm/mach-tegra/sleep.S
+++ b/arch/arm/mach-tegra/sleep.S
@@ -29,36 +29,5 @@
#include <mach/iomap.h>
#include "flowctrl.h"
+#include "sleep.h"
-#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
- + IO_PPSB_VIRT)
-
-/* returns the offset of the flow controller halt register for a cpu */
-.macro cpu_to_halt_reg rd, rcpu
- cmp \rcpu, #0
- subne \rd, \rcpu, #1
- movne \rd, \rd, lsl #3
- addne \rd, \rd, #0x14
- moveq \rd, #0
-.endm
-
-/* returns the offset of the flow controller csr register for a cpu */
-.macro cpu_to_csr_reg rd, rcpu
- cmp \rcpu, #0
- subne \rd, \rcpu, #1
- movne \rd, \rd, lsl #3
- addne \rd, \rd, #0x18
- moveq \rd, #8
-.endm
-
-/* returns the ID of the current processor */
-.macro cpu_id, rd
- mrc p15, 0, \rd, c0, c0, 5
- and \rd, \rd, #0xF
-.endm
-
-/* loads a 32-bit value into a register without a data access */
-.macro mov32, reg, val
- movw \reg, #:lower16:\val
- movt \reg, #:upper16:\val
-.endm
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
new file mode 100644
index 0000000..e25a7cd
--- /dev/null
+++ b/arch/arm/mach-tegra/sleep.h
@@ -0,0 +1,85 @@
+/*
+ * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_SLEEP_H
+#define __MACH_TEGRA_SLEEP_H
+
+#include <mach/iomap.h>
+
+#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
+ + IO_CPU_VIRT)
+#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
+ + IO_PPSB_VIRT)
+#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
+ + IO_PPSB_VIRT)
+
+#ifdef __ASSEMBLY__
+/* returns the offset of the flow controller halt register for a cpu */
+.macro cpu_to_halt_reg rd, rcpu
+ cmp \rcpu, #0
+ subne \rd, \rcpu, #1
+ movne \rd, \rd, lsl #3
+ addne \rd, \rd, #0x14
+ moveq \rd, #0
+.endm
+
+/* returns the offset of the flow controller csr register for a cpu */
+.macro cpu_to_csr_reg rd, rcpu
+ cmp \rcpu, #0
+ subne \rd, \rcpu, #1
+ movne \rd, \rd, lsl #3
+ addne \rd, \rd, #0x18
+ moveq \rd, #8
+.endm
+
+/* returns the ID of the current processor */
+.macro cpu_id, rd
+ mrc p15, 0, \rd, c0, c0, 5
+ and \rd, \rd, #0xF
+.endm
+
+/* loads a 32-bit value into a register without a data access */
+.macro mov32, reg, val
+ movw \reg, #:lower16:\val
+ movt \reg, #:upper16:\val
+.endm
+
+/* Macro to exit SMP coherency. */
+.macro exit_smp, tmp1, tmp2
+ mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
+ bic \tmp1, \tmp1, #(1<<6) | (1<<0) @ clear ACTLR.SMP | ACTLR.FW
+ mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
+ isb
+ cpu_id \tmp1
+ mov \tmp1, \tmp1, lsl #2
+ mov \tmp2, #0xf
+ mov \tmp2, \tmp2, lsl \tmp1
+ mov32 \tmp1, TEGRA_ARM_PERIF_VIRT + 0xC
+ str \tmp2, [\tmp1] @ invalidate SCU tags for CPU
+ dsb
+.endm
+#else
+
+#ifdef CONFIG_HOTPLUG_CPU
+void tegra20_hotplug_init(void);
+void tegra30_hotplug_init(void);
+#else
+static inline void tegra20_hotplug_init(void) {}
+static inline void tegra30_hotplug_init(void) {}
+#endif
+
+#endif
+#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks.c b/arch/arm/mach-tegra/tegra20_clocks.c
new file mode 100644
index 0000000..9273b0df
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.c
@@ -0,0 +1,1625 @@
+/*
+ * arch/arm/mach-tegra/tegra20_clocks.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+#include <linux/clk.h>
+
+#include <mach/iomap.h>
+#include <mach/suspend.h>
+
+#include "clock.h"
+#include "fuse.h"
+#include "tegra2_emc.h"
+#include "tegra_cpu_car.h"
+
+#define RST_DEVICES 0x004
+#define RST_DEVICES_SET 0x300
+#define RST_DEVICES_CLR 0x304
+#define RST_DEVICES_NUM 3
+
+#define CLK_OUT_ENB 0x010
+#define CLK_OUT_ENB_SET 0x320
+#define CLK_OUT_ENB_CLR 0x324
+#define CLK_OUT_ENB_NUM 3
+
+#define CLK_MASK_ARM 0x44
+#define MISC_CLK_ENB 0x48
+
+#define OSC_CTRL 0x50
+#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
+#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
+#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
+#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
+#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
+#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
+
+#define OSC_FREQ_DET 0x58
+#define OSC_FREQ_DET_TRIG (1<<31)
+
+#define OSC_FREQ_DET_STATUS 0x5C
+#define OSC_FREQ_DET_BUSY (1<<31)
+#define OSC_FREQ_DET_CNT_MASK 0xFFFF
+
+#define PERIPH_CLK_SOURCE_I2S1 0x100
+#define PERIPH_CLK_SOURCE_EMC 0x19c
+#define PERIPH_CLK_SOURCE_OSC 0x1fc
+#define PERIPH_CLK_SOURCE_NUM \
+ ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
+
+#define PERIPH_CLK_SOURCE_MASK (3<<30)
+#define PERIPH_CLK_SOURCE_SHIFT 30
+#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
+#define PERIPH_CLK_SOURCE_PWM_SHIFT 28
+#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
+#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
+#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
+#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
+
+#define SDMMC_CLK_INT_FB_SEL (1 << 23)
+#define SDMMC_CLK_INT_FB_DLY_SHIFT 16
+#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
+
+#define PLL_BASE 0x0
+#define PLL_BASE_BYPASS (1<<31)
+#define PLL_BASE_ENABLE (1<<30)
+#define PLL_BASE_REF_ENABLE (1<<29)
+#define PLL_BASE_OVERRIDE (1<<28)
+#define PLL_BASE_DIVP_MASK (0x7<<20)
+#define PLL_BASE_DIVP_SHIFT 20
+#define PLL_BASE_DIVN_MASK (0x3FF<<8)
+#define PLL_BASE_DIVN_SHIFT 8
+#define PLL_BASE_DIVM_MASK (0x1F)
+#define PLL_BASE_DIVM_SHIFT 0
+
+#define PLL_OUT_RATIO_MASK (0xFF<<8)
+#define PLL_OUT_RATIO_SHIFT 8
+#define PLL_OUT_OVERRIDE (1<<2)
+#define PLL_OUT_CLKEN (1<<1)
+#define PLL_OUT_RESET_DISABLE (1<<0)
+
+#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
+
+#define PLL_MISC_DCCON_SHIFT 20
+#define PLL_MISC_CPCON_SHIFT 8
+#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
+#define PLL_MISC_LFCON_SHIFT 4
+#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
+#define PLL_MISC_VCOCON_SHIFT 0
+#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
+
+#define PLLU_BASE_POST_DIV (1<<20)
+
+#define PLLD_MISC_CLKENABLE (1<<30)
+#define PLLD_MISC_DIV_RST (1<<23)
+#define PLLD_MISC_DCCON_SHIFT 12
+
+#define PLLE_MISC_READY (1 << 15)
+
+#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
+#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
+#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
+
+#define SUPER_CLK_MUX 0x00
+#define SUPER_STATE_SHIFT 28
+#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
+#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
+#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
+#define SUPER_SOURCE_MASK 0xF
+#define SUPER_FIQ_SOURCE_SHIFT 12
+#define SUPER_IRQ_SOURCE_SHIFT 8
+#define SUPER_RUN_SOURCE_SHIFT 4
+#define SUPER_IDLE_SOURCE_SHIFT 0
+
+#define SUPER_CLK_DIVIDER 0x04
+
+#define BUS_CLK_DISABLE (1<<3)
+#define BUS_CLK_DIV_MASK 0x3
+
+#define PMC_CTRL 0x0
+ #define PMC_CTRL_BLINK_ENB (1 << 7)
+
+#define PMC_DPD_PADS_ORIDE 0x1c
+ #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
+
+#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
+#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
+#define PMC_BLINK_TIMER_ENB (1 << 15)
+#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
+#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
+
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
+
+#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
+#define CPU_RESET(cpu) (0x1111ul << (cpu))
+
+static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
+static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
+
+/*
+ * Some clocks share a register with other clocks. Any clock op that
+ * non-atomically modifies a register used by another clock must lock
+ * clock_register_lock first.
+ */
+static DEFINE_SPINLOCK(clock_register_lock);
+
+/*
+ * Some peripheral clocks share an enable bit, so refcount the enable bits
+ * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
+ */
+static int tegra_periph_clk_enable_refcount[3 * 32];
+
+#define clk_writel(value, reg) \
+ __raw_writel(value, reg_clk_base + (reg))
+#define clk_readl(reg) \
+ __raw_readl(reg_clk_base + (reg))
+#define pmc_writel(value, reg) \
+ __raw_writel(value, reg_pmc_base + (reg))
+#define pmc_readl(reg) \
+ __raw_readl(reg_pmc_base + (reg))
+
+static unsigned long clk_measure_input_freq(void)
+{
+ u32 clock_autodetect;
+ clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
+ do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
+ clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
+ if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
+ return 12000000;
+ } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
+ return 13000000;
+ } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
+ return 19200000;
+ } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
+ return 26000000;
+ } else {
+ pr_err("%s: Unexpected clock autodetect value %d",
+ __func__, clock_autodetect);
+ BUG();
+ return 0;
+ }
+}
+
+static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
+{
+ s64 divider_u71 = parent_rate * 2;
+ divider_u71 += rate - 1;
+ do_div(divider_u71, rate);
+
+ if (divider_u71 - 2 < 0)
+ return 0;
+
+ if (divider_u71 - 2 > 255)
+ return -EINVAL;
+
+ return divider_u71 - 2;
+}
+
+static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
+{
+ s64 divider_u16;
+
+ divider_u16 = parent_rate;
+ divider_u16 += rate - 1;
+ do_div(divider_u16, rate);
+
+ if (divider_u16 - 1 < 0)
+ return 0;
+
+ if (divider_u16 - 1 > 0xFFFF)
+ return -EINVAL;
+
+ return divider_u16 - 1;
+}
+
+static unsigned long tegra_clk_fixed_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra_clk_32k_ops = {
+ .recalc_rate = tegra_clk_fixed_recalc_rate,
+};
+
+/* clk_m functions */
+static unsigned long tegra20_clk_m_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ if (!to_clk_tegra(hw)->fixed_rate)
+ to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
+ return to_clk_tegra(hw)->fixed_rate;
+}
+
+static void tegra20_clk_m_init(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 osc_ctrl = clk_readl(OSC_CTRL);
+ u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
+
+ switch (c->fixed_rate) {
+ case 12000000:
+ auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
+ break;
+ case 13000000:
+ auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
+ break;
+ case 19200000:
+ auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
+ break;
+ case 26000000:
+ auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
+ break;
+ default:
+ BUG();
+ }
+ clk_writel(auto_clock_control, OSC_CTRL);
+}
+
+struct clk_ops tegra_clk_m_ops = {
+ .init = tegra20_clk_m_init,
+ .recalc_rate = tegra20_clk_m_recalc_rate,
+};
+
+/* super clock functions */
+/* "super clocks" on tegra have two-stage muxes and a clock skipping
+ * super divider. We will ignore the clock skipping divider, since we
+ * can't lower the voltage when using the clock skip, but we can if we
+ * lower the PLL frequency.
+ */
+static int tegra20_super_clk_is_enabled(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val;
+
+ val = clk_readl(c->reg + SUPER_CLK_MUX);
+ BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+ ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+ c->state = ON;
+ return c->state;
+}
+
+static int tegra20_super_clk_enable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
+ return 0;
+}
+
+static void tegra20_super_clk_disable(struct clk_hw *hw)
+{
+ pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+ /* oops - don't disable the CPU clock! */
+ BUG();
+}
+
+static u8 tegra20_super_clk_get_parent(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ int val = clk_readl(c->reg + SUPER_CLK_MUX);
+ int source;
+ int shift;
+
+ BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+ ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+ shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+ SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+ source = (val >> shift) & SUPER_SOURCE_MASK;
+ return source;
+}
+
+static int tegra20_super_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg + SUPER_CLK_MUX);
+ int shift;
+
+ BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
+ ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
+ shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
+ SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
+ val &= ~(SUPER_SOURCE_MASK << shift);
+ val |= index << shift;
+
+ clk_writel(val, c->reg);
+
+ return 0;
+}
+
+/* FIX ME: Need to switch parents to change the source PLL rate */
+static unsigned long tegra20_super_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ return prate;
+}
+
+static long tegra20_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ return *prate;
+}
+
+static int tegra20_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ return 0;
+}
+
+struct clk_ops tegra_super_ops = {
+ .is_enabled = tegra20_super_clk_is_enabled,
+ .enable = tegra20_super_clk_enable,
+ .disable = tegra20_super_clk_disable,
+ .set_parent = tegra20_super_clk_set_parent,
+ .get_parent = tegra20_super_clk_get_parent,
+ .set_rate = tegra20_super_clk_set_rate,
+ .round_rate = tegra20_super_clk_round_rate,
+ .recalc_rate = tegra20_super_clk_recalc_rate,
+};
+
+static unsigned long tegra20_twd_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = parent_rate;
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+
+ return rate;
+}
+
+struct clk_ops tegra_twd_ops = {
+ .recalc_rate = tegra20_twd_clk_recalc_rate,
+};
+
+static u8 tegra20_cop_clk_get_parent(struct clk_hw *hw)
+{
+ return 0;
+}
+
+struct clk_ops tegra_cop_ops = {
+ .get_parent = tegra20_cop_clk_get_parent,
+};
+
+/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
+ * reset the COP block (i.e. AVP) */
+void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert)
+{
+ unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
+
+ pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
+ clk_writel(1 << 1, reg);
+}
+
+/* bus clock functions */
+static int tegra20_bus_clk_is_enabled(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg);
+
+ c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
+ return c->state;
+}
+
+static int tegra20_bus_clk_enable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&clock_register_lock, flags);
+
+ val = clk_readl(c->reg);
+ val &= ~(BUS_CLK_DISABLE << c->reg_shift);
+ clk_writel(val, c->reg);
+
+ spin_unlock_irqrestore(&clock_register_lock, flags);
+
+ return 0;
+}
+
+static void tegra20_bus_clk_disable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long flags;
+ u32 val;
+
+ spin_lock_irqsave(&clock_register_lock, flags);
+
+ val = clk_readl(c->reg);
+ val |= BUS_CLK_DISABLE << c->reg_shift;
+ clk_writel(val, c->reg);
+
+ spin_unlock_irqrestore(&clock_register_lock, flags);
+}
+
+static unsigned long tegra20_bus_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg);
+ u64 rate = prate;
+
+ c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
+ c->mul = 1;
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+ return rate;
+}
+
+static int tegra20_bus_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ int ret = -EINVAL;
+ unsigned long flags;
+ u32 val;
+ int i;
+
+ spin_lock_irqsave(&clock_register_lock, flags);
+
+ val = clk_readl(c->reg);
+ for (i = 1; i <= 4; i++) {
+ if (rate == parent_rate / i) {
+ val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
+ val |= (i - 1) << c->reg_shift;
+ clk_writel(val, c->reg);
+ c->div = i;
+ c->mul = 1;
+ ret = 0;
+ break;
+ }
+ }
+
+ spin_unlock_irqrestore(&clock_register_lock, flags);
+
+ return ret;
+}
+
+static long tegra20_bus_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long parent_rate = *prate;
+ s64 divider;
+
+ if (rate >= parent_rate)
+ return rate;
+
+ divider = parent_rate;
+ divider += rate - 1;
+ do_div(divider, rate);
+
+ if (divider < 0)
+ return divider;
+
+ if (divider > 4)
+ divider = 4;
+ do_div(parent_rate, divider);
+
+ return parent_rate;
+}
+
+struct clk_ops tegra_bus_ops = {
+ .is_enabled = tegra20_bus_clk_is_enabled,
+ .enable = tegra20_bus_clk_enable,
+ .disable = tegra20_bus_clk_disable,
+ .set_rate = tegra20_bus_clk_set_rate,
+ .round_rate = tegra20_bus_clk_round_rate,
+ .recalc_rate = tegra20_bus_clk_recalc_rate,
+};
+
+/* Blink output functions */
+static int tegra20_blink_clk_is_enabled(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val;
+
+ val = pmc_readl(PMC_CTRL);
+ c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
+ return c->state;
+}
+
+static unsigned long tegra20_blink_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = prate;
+ u32 val;
+
+ c->mul = 1;
+ val = pmc_readl(c->reg);
+
+ if (val & PMC_BLINK_TIMER_ENB) {
+ unsigned int on_off;
+
+ on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
+ PMC_BLINK_TIMER_DATA_ON_MASK;
+ val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+ val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+ on_off += val;
+ /* each tick in the blink timer is 4 32KHz clocks */
+ c->div = on_off * 4;
+ } else {
+ c->div = 1;
+ }
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+ return rate;
+}
+
+static int tegra20_blink_clk_enable(struct clk_hw *hw)
+{
+ u32 val;
+
+ val = pmc_readl(PMC_DPD_PADS_ORIDE);
+ pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+
+ val = pmc_readl(PMC_CTRL);
+ pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
+
+ return 0;
+}
+
+static void tegra20_blink_clk_disable(struct clk_hw *hw)
+{
+ u32 val;
+
+ val = pmc_readl(PMC_CTRL);
+ pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
+
+ val = pmc_readl(PMC_DPD_PADS_ORIDE);
+ pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
+}
+
+static int tegra20_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
+ if (rate >= parent_rate) {
+ c->div = 1;
+ pmc_writel(0, c->reg);
+ } else {
+ unsigned int on_off;
+ u32 val;
+
+ on_off = DIV_ROUND_UP(parent_rate / 8, rate);
+ c->div = on_off * 8;
+
+ val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
+ PMC_BLINK_TIMER_DATA_ON_SHIFT;
+ on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+ on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+ val |= on_off;
+ val |= PMC_BLINK_TIMER_ENB;
+ pmc_writel(val, c->reg);
+ }
+
+ return 0;
+}
+
+static long tegra20_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ int div;
+ int mul;
+ long round_rate = *prate;
+
+ mul = 1;
+
+ if (rate >= *prate) {
+ div = 1;
+ } else {
+ div = DIV_ROUND_UP(*prate / 8, rate);
+ div *= 8;
+ }
+
+ round_rate *= mul;
+ round_rate += div - 1;
+ do_div(round_rate, div);
+
+ return round_rate;
+}
+
+struct clk_ops tegra_blink_clk_ops = {
+ .is_enabled = tegra20_blink_clk_is_enabled,
+ .enable = tegra20_blink_clk_enable,
+ .disable = tegra20_blink_clk_disable,
+ .set_rate = tegra20_blink_clk_set_rate,
+ .round_rate = tegra20_blink_clk_round_rate,
+ .recalc_rate = tegra20_blink_clk_recalc_rate,
+};
+
+/* PLL Functions */
+static int tegra20_pll_clk_wait_for_lock(struct clk_tegra *c)
+{
+ udelay(c->u.pll.lock_delay);
+ return 0;
+}
+
+static int tegra20_pll_clk_is_enabled(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg + PLL_BASE);
+
+ c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
+ return c->state;
+}
+
+static unsigned long tegra20_pll_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg + PLL_BASE);
+ u64 rate = prate;
+
+ if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+ const struct clk_pll_freq_table *sel;
+ for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+ if (sel->input_rate == prate &&
+ sel->output_rate == c->u.pll.fixed_rate) {
+ c->mul = sel->n;
+ c->div = sel->m * sel->p;
+ break;
+ }
+ }
+ pr_err("Clock %s has unknown fixed frequency\n",
+ __clk_get_name(hw->clk));
+ BUG();
+ } else if (val & PLL_BASE_BYPASS) {
+ c->mul = 1;
+ c->div = 1;
+ } else {
+ c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+ c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+ if (c->flags & PLLU)
+ c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+ else
+ c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
+ }
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+ return rate;
+}
+
+static int tegra20_pll_clk_enable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val;
+ pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+ val = clk_readl(c->reg + PLL_BASE);
+ val &= ~PLL_BASE_BYPASS;
+ val |= PLL_BASE_ENABLE;
+ clk_writel(val, c->reg + PLL_BASE);
+
+ tegra20_pll_clk_wait_for_lock(c);
+
+ return 0;
+}
+
+static void tegra20_pll_clk_disable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val;
+ pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+ val = clk_readl(c->reg);
+ val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
+ clk_writel(val, c->reg);
+}
+
+static int tegra20_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long input_rate = parent_rate;
+ const struct clk_pll_freq_table *sel;
+ u32 val;
+
+ pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+ if (c->flags & PLL_FIXED) {
+ int ret = 0;
+ if (rate != c->u.pll.fixed_rate) {
+ pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
+ __func__, __clk_get_name(hw->clk),
+ c->u.pll.fixed_rate, rate);
+ ret = -EINVAL;
+ }
+ return ret;
+ }
+
+ for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+ if (sel->input_rate == input_rate && sel->output_rate == rate) {
+ c->mul = sel->n;
+ c->div = sel->m * sel->p;
+
+ val = clk_readl(c->reg + PLL_BASE);
+ if (c->flags & PLL_FIXED)
+ val |= PLL_BASE_OVERRIDE;
+ val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
+ PLL_BASE_DIVM_MASK);
+ val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
+ (sel->n << PLL_BASE_DIVN_SHIFT);
+ BUG_ON(sel->p < 1 || sel->p > 2);
+ if (c->flags & PLLU) {
+ if (sel->p == 1)
+ val |= PLLU_BASE_POST_DIV;
+ } else {
+ if (sel->p == 2)
+ val |= 1 << PLL_BASE_DIVP_SHIFT;
+ }
+ clk_writel(val, c->reg + PLL_BASE);
+
+ if (c->flags & PLL_HAS_CPCON) {
+ val = clk_readl(c->reg + PLL_MISC(c));
+ val &= ~PLL_MISC_CPCON_MASK;
+ val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
+ clk_writel(val, c->reg + PLL_MISC(c));
+ }
+
+ if (c->state == ON)
+ tegra20_pll_clk_enable(hw);
+ return 0;
+ }
+ }
+ return -EINVAL;
+}
+
+static long tegra20_pll_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ const struct clk_pll_freq_table *sel;
+ unsigned long input_rate = *prate;
+ u64 output_rate = *prate;
+ int mul;
+ int div;
+
+ if (c->flags & PLL_FIXED)
+ return c->u.pll.fixed_rate;
+
+ for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++)
+ if (sel->input_rate == input_rate && sel->output_rate == rate) {
+ mul = sel->n;
+ div = sel->m * sel->p;
+ break;
+ }
+
+ if (sel->input_rate == 0)
+ return -EINVAL;
+
+ output_rate *= mul;
+ output_rate += div - 1; /* round up */
+ do_div(output_rate, div);
+
+ return output_rate;
+}
+
+struct clk_ops tegra_pll_ops = {
+ .is_enabled = tegra20_pll_clk_is_enabled,
+ .enable = tegra20_pll_clk_enable,
+ .disable = tegra20_pll_clk_disable,
+ .set_rate = tegra20_pll_clk_set_rate,
+ .recalc_rate = tegra20_pll_clk_recalc_rate,
+ .round_rate = tegra20_pll_clk_round_rate,
+};
+
+static void tegra20_pllx_clk_init(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
+ if (tegra_sku_id == 7)
+ c->max_rate = 750000000;
+}
+
+struct clk_ops tegra_pllx_ops = {
+ .init = tegra20_pllx_clk_init,
+ .is_enabled = tegra20_pll_clk_is_enabled,
+ .enable = tegra20_pll_clk_enable,
+ .disable = tegra20_pll_clk_disable,
+ .set_rate = tegra20_pll_clk_set_rate,
+ .recalc_rate = tegra20_pll_clk_recalc_rate,
+ .round_rate = tegra20_pll_clk_round_rate,
+};
+
+static int tegra20_plle_clk_enable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val;
+
+ pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+ mdelay(1);
+
+ val = clk_readl(c->reg + PLL_BASE);
+ if (!(val & PLLE_MISC_READY))
+ return -EBUSY;
+
+ val = clk_readl(c->reg + PLL_BASE);
+ val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
+ clk_writel(val, c->reg + PLL_BASE);
+
+ return 0;
+}
+
+struct clk_ops tegra_plle_ops = {
+ .is_enabled = tegra20_pll_clk_is_enabled,
+ .enable = tegra20_plle_clk_enable,
+ .set_rate = tegra20_pll_clk_set_rate,
+ .recalc_rate = tegra20_pll_clk_recalc_rate,
+ .round_rate = tegra20_pll_clk_round_rate,
+};
+
+/* Clock divider ops */
+static int tegra20_pll_div_clk_is_enabled(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg);
+
+ val >>= c->reg_shift;
+ c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
+ if (!(val & PLL_OUT_RESET_DISABLE))
+ c->state = OFF;
+ return c->state;
+}
+
+static unsigned long tegra20_pll_div_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = prate;
+ u32 val = clk_readl(c->reg);
+ u32 divu71;
+
+ val >>= c->reg_shift;
+
+ if (c->flags & DIV_U71) {
+ divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+ c->div = (divu71 + 2);
+ c->mul = 2;
+ } else if (c->flags & DIV_2) {
+ c->div = 2;
+ c->mul = 1;
+ } else {
+ c->div = 1;
+ c->mul = 1;
+ }
+
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+
+ return rate;
+}
+
+static int tegra20_pll_div_clk_enable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long flags;
+ u32 new_val;
+ u32 val;
+
+ pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
+
+ if (c->flags & DIV_U71) {
+ spin_lock_irqsave(&clock_register_lock, flags);
+ val = clk_readl(c->reg);
+ new_val = val >> c->reg_shift;
+ new_val &= 0xFFFF;
+
+ new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
+
+ val &= ~(0xFFFF << c->reg_shift);
+ val |= new_val << c->reg_shift;
+ clk_writel(val, c->reg);
+ spin_unlock_irqrestore(&clock_register_lock, flags);
+ return 0;
+ } else if (c->flags & DIV_2) {
+ BUG_ON(!(c->flags & PLLD));
+ spin_lock_irqsave(&clock_register_lock, flags);
+ val = clk_readl(c->reg);
+ val &= ~PLLD_MISC_DIV_RST;
+ clk_writel(val, c->reg);
+ spin_unlock_irqrestore(&clock_register_lock, flags);
+ return 0;
+ }
+ return -EINVAL;
+}
+
+static void tegra20_pll_div_clk_disable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long flags;
+ u32 new_val;
+ u32 val;
+
+ pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
+
+ if (c->flags & DIV_U71) {
+ spin_lock_irqsave(&clock_register_lock, flags);
+ val = clk_readl(c->reg);
+ new_val = val >> c->reg_shift;
+ new_val &= 0xFFFF;
+
+ new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
+
+ val &= ~(0xFFFF << c->reg_shift);
+ val |= new_val << c->reg_shift;
+ clk_writel(val, c->reg);
+ spin_unlock_irqrestore(&clock_register_lock, flags);
+ } else if (c->flags & DIV_2) {
+ BUG_ON(!(c->flags & PLLD));
+ spin_lock_irqsave(&clock_register_lock, flags);
+ val = clk_readl(c->reg);
+ val |= PLLD_MISC_DIV_RST;
+ clk_writel(val, c->reg);
+ spin_unlock_irqrestore(&clock_register_lock, flags);
+ }
+}
+
+static int tegra20_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long flags;
+ int divider_u71;
+ u32 new_val;
+ u32 val;
+
+ pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+ if (c->flags & DIV_U71) {
+ divider_u71 = clk_div71_get_divider(parent_rate, rate);
+ if (divider_u71 >= 0) {
+ spin_lock_irqsave(&clock_register_lock, flags);
+ val = clk_readl(c->reg);
+ new_val = val >> c->reg_shift;
+ new_val &= 0xFFFF;
+ if (c->flags & DIV_U71_FIXED)
+ new_val |= PLL_OUT_OVERRIDE;
+ new_val &= ~PLL_OUT_RATIO_MASK;
+ new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
+
+ val &= ~(0xFFFF << c->reg_shift);
+ val |= new_val << c->reg_shift;
+ clk_writel(val, c->reg);
+ c->div = divider_u71 + 2;
+ c->mul = 2;
+ spin_unlock_irqrestore(&clock_register_lock, flags);
+ return 0;
+ }
+ } else if (c->flags & DIV_2) {
+ if (parent_rate == rate * 2)
+ return 0;
+ }
+ return -EINVAL;
+}
+
+static long tegra20_pll_div_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long parent_rate = *prate;
+ int divider;
+
+ pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+ if (c->flags & DIV_U71) {
+ divider = clk_div71_get_divider(parent_rate, rate);
+ if (divider < 0)
+ return divider;
+ return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+ } else if (c->flags & DIV_2) {
+ return DIV_ROUND_UP(parent_rate, 2);
+ }
+ return -EINVAL;
+}
+
+struct clk_ops tegra_pll_div_ops = {
+ .is_enabled = tegra20_pll_div_clk_is_enabled,
+ .enable = tegra20_pll_div_clk_enable,
+ .disable = tegra20_pll_div_clk_disable,
+ .set_rate = tegra20_pll_div_clk_set_rate,
+ .round_rate = tegra20_pll_div_clk_round_rate,
+ .recalc_rate = tegra20_pll_div_clk_recalc_rate,
+};
+
+/* Periph clk ops */
+
+static int tegra20_periph_clk_is_enabled(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
+ c->state = ON;
+
+ if (!c->u.periph.clk_num)
+ goto out;
+
+ if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+ PERIPH_CLK_TO_ENB_BIT(c)))
+ c->state = OFF;
+
+ if (!(c->flags & PERIPH_NO_RESET))
+ if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
+ PERIPH_CLK_TO_ENB_BIT(c))
+ c->state = OFF;
+
+out:
+ return c->state;
+}
+
+static int tegra20_periph_clk_enable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long flags;
+ u32 val;
+
+ pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+ if (!c->u.periph.clk_num)
+ return 0;
+
+ tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
+ if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
+ return 0;
+
+ spin_lock_irqsave(&clock_register_lock, flags);
+
+ clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+ CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
+ if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
+ clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+ RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+ if (c->flags & PERIPH_EMC_ENB) {
+ /* The EMC peripheral clock has 2 extra enable bits */
+ /* FIXME: Do they need to be disabled? */
+ val = clk_readl(c->reg);
+ val |= 0x3 << 24;
+ clk_writel(val, c->reg);
+ }
+
+ spin_unlock_irqrestore(&clock_register_lock, flags);
+
+ return 0;
+}
+
+static void tegra20_periph_clk_disable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long flags;
+
+ pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
+
+ if (!c->u.periph.clk_num)
+ return;
+
+ tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+
+ if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
+ return;
+
+ spin_lock_irqsave(&clock_register_lock, flags);
+
+ clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+ CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+
+ spin_unlock_irqrestore(&clock_register_lock, flags);
+}
+
+void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
+
+ pr_debug("%s %s on clock %s\n", __func__,
+ assert ? "assert" : "deassert", __clk_get_name(hw->clk));
+
+ BUG_ON(!c->u.periph.clk_num);
+
+ if (!(c->flags & PERIPH_NO_RESET))
+ clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+ base + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+
+static int tegra20_periph_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val;
+ u32 mask;
+ u32 shift;
+
+ pr_debug("%s: %s %d\n", __func__, __clk_get_name(hw->clk), index);
+
+ if (c->flags & MUX_PWM) {
+ shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+ mask = PERIPH_CLK_SOURCE_PWM_MASK;
+ } else {
+ shift = PERIPH_CLK_SOURCE_SHIFT;
+ mask = PERIPH_CLK_SOURCE_MASK;
+ }
+
+ val = clk_readl(c->reg);
+ val &= ~mask;
+ val |= (index) << shift;
+
+ clk_writel(val, c->reg);
+
+ return 0;
+}
+
+static u8 tegra20_periph_clk_get_parent(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg);
+ u32 mask;
+ u32 shift;
+
+ if (c->flags & MUX_PWM) {
+ shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
+ mask = PERIPH_CLK_SOURCE_PWM_MASK;
+ } else {
+ shift = PERIPH_CLK_SOURCE_SHIFT;
+ mask = PERIPH_CLK_SOURCE_MASK;
+ }
+
+ if (c->flags & MUX)
+ return (val & mask) >> shift;
+ else
+ return 0;
+}
+
+static unsigned long tegra20_periph_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long rate = prate;
+ u32 val = clk_readl(c->reg);
+
+ if (c->flags & DIV_U71) {
+ u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+ c->div = divu71 + 2;
+ c->mul = 2;
+ } else if (c->flags & DIV_U16) {
+ u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+ c->div = divu16 + 1;
+ c->mul = 1;
+ } else {
+ c->div = 1;
+ c->mul = 1;
+ return rate;
+ }
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+
+ return rate;
+}
+
+static int tegra20_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val;
+ int divider;
+
+ val = clk_readl(c->reg);
+
+ if (c->flags & DIV_U71) {
+ divider = clk_div71_get_divider(parent_rate, rate);
+
+ if (divider >= 0) {
+ val = clk_readl(c->reg);
+ val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
+ val |= divider;
+ clk_writel(val, c->reg);
+ c->div = divider + 2;
+ c->mul = 2;
+ return 0;
+ }
+ } else if (c->flags & DIV_U16) {
+ divider = clk_div16_get_divider(parent_rate, rate);
+ if (divider >= 0) {
+ val = clk_readl(c->reg);
+ val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
+ val |= divider;
+ clk_writel(val, c->reg);
+ c->div = divider + 1;
+ c->mul = 1;
+ return 0;
+ }
+ } else if (parent_rate <= rate) {
+ c->div = 1;
+ c->mul = 1;
+ return 0;
+ }
+
+ return -EINVAL;
+}
+
+static long tegra20_periph_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long *prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
+ int divider;
+
+ pr_debug("%s: %s %lu\n", __func__, __clk_get_name(hw->clk), rate);
+
+ if (prate)
+ parent_rate = *prate;
+
+ if (c->flags & DIV_U71) {
+ divider = clk_div71_get_divider(parent_rate, rate);
+ if (divider < 0)
+ return divider;
+
+ return DIV_ROUND_UP(parent_rate * 2, divider + 2);
+ } else if (c->flags & DIV_U16) {
+ divider = clk_div16_get_divider(parent_rate, rate);
+ if (divider < 0)
+ return divider;
+ return DIV_ROUND_UP(parent_rate, divider + 1);
+ }
+ return -EINVAL;
+}
+
+struct clk_ops tegra_periph_clk_ops = {
+ .is_enabled = tegra20_periph_clk_is_enabled,
+ .enable = tegra20_periph_clk_enable,
+ .disable = tegra20_periph_clk_disable,
+ .set_parent = tegra20_periph_clk_set_parent,
+ .get_parent = tegra20_periph_clk_get_parent,
+ .set_rate = tegra20_periph_clk_set_rate,
+ .round_rate = tegra20_periph_clk_round_rate,
+ .recalc_rate = tegra20_periph_clk_recalc_rate,
+};
+
+/* External memory controller clock ops */
+static void tegra20_emc_clk_init(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ c->max_rate = __clk_get_rate(hw->clk);
+}
+
+static long tegra20_emc_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ long emc_rate;
+ long clk_rate;
+
+ /*
+ * The slowest entry in the EMC clock table that is at least as
+ * fast as rate.
+ */
+ emc_rate = tegra_emc_round_rate(rate);
+ if (emc_rate < 0)
+ return c->max_rate;
+
+ /*
+ * The fastest rate the PLL will generate that is at most the
+ * requested rate.
+ */
+ clk_rate = tegra20_periph_clk_round_rate(hw, emc_rate, NULL);
+
+ /*
+ * If this fails, and emc_rate > clk_rate, it's because the maximum
+ * rate in the EMC tables is larger than the maximum rate of the EMC
+ * clock. The EMC clock's max rate is the rate it was running when the
+ * kernel booted. Such a mismatch is probably due to using the wrong
+ * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
+ */
+ WARN_ONCE(emc_rate != clk_rate,
+ "emc_rate %ld != clk_rate %ld",
+ emc_rate, clk_rate);
+
+ return emc_rate;
+}
+
+static int tegra20_emc_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ int ret;
+
+ /*
+ * The Tegra2 memory controller has an interlock with the clock
+ * block that allows memory shadowed registers to be updated,
+ * and then transfer them to the main registers at the same
+ * time as the clock update without glitches.
+ */
+ ret = tegra_emc_set_rate(rate);
+ if (ret < 0)
+ return ret;
+
+ ret = tegra20_periph_clk_set_rate(hw, rate, parent_rate);
+ udelay(1);
+
+ return ret;
+}
+
+struct clk_ops tegra_emc_clk_ops = {
+ .init = tegra20_emc_clk_init,
+ .is_enabled = tegra20_periph_clk_is_enabled,
+ .enable = tegra20_periph_clk_enable,
+ .disable = tegra20_periph_clk_disable,
+ .set_parent = tegra20_periph_clk_set_parent,
+ .get_parent = tegra20_periph_clk_get_parent,
+ .set_rate = tegra20_emc_clk_set_rate,
+ .round_rate = tegra20_emc_clk_round_rate,
+ .recalc_rate = tegra20_periph_clk_recalc_rate,
+};
+
+/* Clock doubler ops */
+static int tegra20_clk_double_is_enabled(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
+ c->state = ON;
+
+ if (!c->u.periph.clk_num)
+ goto out;
+
+ if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+ PERIPH_CLK_TO_ENB_BIT(c)))
+ c->state = OFF;
+
+out:
+ return c->state;
+};
+
+static unsigned long tegra20_clk_double_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = prate;
+
+ c->mul = 2;
+ c->div = 1;
+
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+
+ return rate;
+}
+
+static long tegra20_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long output_rate = *prate;
+
+ do_div(output_rate, 2);
+ return output_rate;
+}
+
+static int tegra20_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ if (rate != 2 * parent_rate)
+ return -EINVAL;
+ return 0;
+}
+
+struct clk_ops tegra_clk_double_ops = {
+ .is_enabled = tegra20_clk_double_is_enabled,
+ .enable = tegra20_periph_clk_enable,
+ .disable = tegra20_periph_clk_disable,
+ .set_rate = tegra20_clk_double_set_rate,
+ .recalc_rate = tegra20_clk_double_recalc_rate,
+ .round_rate = tegra20_clk_double_round_rate,
+};
+
+/* Audio sync clock ops */
+static int tegra20_audio_sync_clk_is_enabled(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg);
+
+ c->state = (val & (1<<4)) ? OFF : ON;
+ return c->state;
+}
+
+static int tegra20_audio_sync_clk_enable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
+ clk_writel(0, c->reg);
+ return 0;
+}
+
+static void tegra20_audio_sync_clk_disable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ clk_writel(1, c->reg);
+}
+
+static u8 tegra20_audio_sync_clk_get_parent(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg);
+ int source;
+
+ source = val & 0xf;
+ return source;
+}
+
+static int tegra20_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val;
+
+ val = clk_readl(c->reg);
+ val &= ~0xf;
+ val |= index;
+
+ clk_writel(val, c->reg);
+
+ return 0;
+}
+
+struct clk_ops tegra_audio_sync_clk_ops = {
+ .is_enabled = tegra20_audio_sync_clk_is_enabled,
+ .enable = tegra20_audio_sync_clk_enable,
+ .disable = tegra20_audio_sync_clk_disable,
+ .set_parent = tegra20_audio_sync_clk_set_parent,
+ .get_parent = tegra20_audio_sync_clk_get_parent,
+};
+
+/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
+
+static int tegra20_cdev_clk_is_enabled(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
+ * currently done in the pinmux code. */
+ c->state = ON;
+
+ BUG_ON(!c->u.periph.clk_num);
+
+ if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
+ PERIPH_CLK_TO_ENB_BIT(c)))
+ c->state = OFF;
+ return c->state;
+}
+
+static int tegra20_cdev_clk_enable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ BUG_ON(!c->u.periph.clk_num);
+
+ clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+ CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
+ return 0;
+}
+
+static void tegra20_cdev_clk_disable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ BUG_ON(!c->u.periph.clk_num);
+
+ clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
+ CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
+}
+
+static unsigned long tegra20_cdev_recalc_rate(struct clk_hw *hw,
+ unsigned long prate)
+{
+ return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra_cdev_clk_ops = {
+ .is_enabled = tegra20_cdev_clk_is_enabled,
+ .enable = tegra20_cdev_clk_enable,
+ .disable = tegra20_cdev_clk_disable,
+ .recalc_rate = tegra20_cdev_recalc_rate,
+};
+
+/* Tegra20 CPU clock and reset control functions */
+static void tegra20_wait_cpu_in_reset(u32 cpu)
+{
+ unsigned int reg;
+
+ do {
+ reg = readl(reg_clk_base +
+ TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+ cpu_relax();
+ } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
+
+ return;
+}
+
+static void tegra20_put_cpu_in_reset(u32 cpu)
+{
+ writel(CPU_RESET(cpu),
+ reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+ dmb();
+}
+
+static void tegra20_cpu_out_of_reset(u32 cpu)
+{
+ writel(CPU_RESET(cpu),
+ reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+ wmb();
+}
+
+static void tegra20_enable_cpu_clock(u32 cpu)
+{
+ unsigned int reg;
+
+ reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+ writel(reg & ~CPU_CLOCK(cpu),
+ reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+ barrier();
+ reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static void tegra20_disable_cpu_clock(u32 cpu)
+{
+ unsigned int reg;
+
+ reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+ writel(reg | CPU_CLOCK(cpu),
+ reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
+
+static struct tegra_cpu_car_ops tegra20_cpu_car_ops = {
+ .wait_for_reset = tegra20_wait_cpu_in_reset,
+ .put_in_reset = tegra20_put_cpu_in_reset,
+ .out_of_reset = tegra20_cpu_out_of_reset,
+ .enable_clock = tegra20_enable_cpu_clock,
+ .disable_clock = tegra20_disable_cpu_clock,
+};
+
+void __init tegra20_cpu_car_ops_init(void)
+{
+ tegra_cpu_car_ops = &tegra20_cpu_car_ops;
+}
diff --git a/arch/arm/mach-tegra/tegra20_clocks.h b/arch/arm/mach-tegra/tegra20_clocks.h
new file mode 100644
index 0000000..8bfd31b
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA20_CLOCK_H
+#define __MACH_TEGRA20_CLOCK_H
+
+extern struct clk_ops tegra_clk_32k_ops;
+extern struct clk_ops tegra_pll_ops;
+extern struct clk_ops tegra_clk_m_ops;
+extern struct clk_ops tegra_pll_div_ops;
+extern struct clk_ops tegra_pllx_ops;
+extern struct clk_ops tegra_plle_ops;
+extern struct clk_ops tegra_clk_double_ops;
+extern struct clk_ops tegra_cdev_clk_ops;
+extern struct clk_ops tegra_audio_sync_clk_ops;
+extern struct clk_ops tegra_super_ops;
+extern struct clk_ops tegra_cpu_ops;
+extern struct clk_ops tegra_twd_ops;
+extern struct clk_ops tegra_cop_ops;
+extern struct clk_ops tegra_bus_ops;
+extern struct clk_ops tegra_blink_clk_ops;
+extern struct clk_ops tegra_emc_clk_ops;
+extern struct clk_ops tegra_periph_clk_ops;
+extern struct clk_ops tegra_clk_shared_bus_ops;
+
+void tegra2_periph_clk_reset(struct clk_hw *hw, bool assert);
+void tegra2_cop_clk_reset(struct clk_hw *hw, bool assert);
+
+#endif
diff --git a/arch/arm/mach-tegra/tegra20_clocks_data.c b/arch/arm/mach-tegra/tegra20_clocks_data.c
new file mode 100644
index 0000000..e81dcd2
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra20_clocks_data.c
@@ -0,0 +1,1144 @@
+/*
+ * arch/arm/mach-tegra/tegra2_clocks.c
+ *
+ * Copyright (C) 2010 Google, Inc.
+ * Copyright (c) 2012 NVIDIA CORPORATION. All rights reserved.
+ *
+ * Author:
+ * Colin Cross <ccross@google.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/clk-private.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+
+#include <mach/iomap.h>
+#include <mach/suspend.h>
+
+#include "clock.h"
+#include "fuse.h"
+#include "tegra2_emc.h"
+#include "tegra20_clocks.h"
+#include "tegra_cpu_car.h"
+
+/* Clock definitions */
+
+#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
+ _parent_names, _parents, _parent) \
+ static struct clk tegra_##_name = { \
+ .hw = &tegra_##_name##_hw.hw, \
+ .name = #_name, \
+ .rate = _rate, \
+ .ops = _ops, \
+ .flags = _flags, \
+ .parent_names = _parent_names, \
+ .parents = _parents, \
+ .num_parents = ARRAY_SIZE(_parent_names), \
+ .parent = _parent, \
+ };
+
+static struct clk tegra_clk_32k;
+static struct clk_tegra tegra_clk_32k_hw = {
+ .hw = {
+ .clk = &tegra_clk_32k,
+ },
+ .fixed_rate = 32768,
+};
+
+static struct clk tegra_clk_32k = {
+ .name = "clk_32k",
+ .rate = 32768,
+ .ops = &tegra_clk_32k_ops,
+ .hw = &tegra_clk_32k_hw.hw,
+ .flags = CLK_IS_ROOT,
+};
+
+static struct clk tegra_clk_m;
+static struct clk_tegra tegra_clk_m_hw = {
+ .hw = {
+ .clk = &tegra_clk_m,
+ },
+ .flags = ENABLE_ON_INIT,
+ .reg = 0x1fc,
+ .reg_shift = 28,
+ .max_rate = 26000000,
+ .fixed_rate = 0,
+};
+
+static struct clk tegra_clk_m = {
+ .name = "clk_m",
+ .ops = &tegra_clk_m_ops,
+ .hw = &tegra_clk_m_hw.hw,
+ .flags = CLK_IS_ROOT,
+};
+
+#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
+ _input_max, _cf_min, _cf_max, _vco_min, \
+ _vco_max, _freq_table, _lock_delay, _ops, \
+ _fixed_rate, _parent) \
+ static const char *tegra_##_name##_parent_names[] = { \
+ #_parent, \
+ }; \
+ static struct clk *tegra_##_name##_parents[] = { \
+ &tegra_##_parent, \
+ }; \
+ static struct clk tegra_##_name; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .flags = _flags, \
+ .reg = _reg, \
+ .max_rate = _max_rate, \
+ .u.pll = { \
+ .input_min = _input_min, \
+ .input_max = _input_max, \
+ .cf_min = _cf_min, \
+ .cf_max = _cf_max, \
+ .vco_min = _vco_min, \
+ .vco_max = _vco_max, \
+ .freq_table = _freq_table, \
+ .lock_delay = _lock_delay, \
+ .fixed_rate = _fixed_rate, \
+ }, \
+ }; \
+ static struct clk tegra_##_name = { \
+ .name = #_name, \
+ .ops = &_ops, \
+ .hw = &tegra_##_name##_hw.hw, \
+ .parent = &tegra_##_parent, \
+ .parent_names = tegra_##_name##_parent_names, \
+ .parents = tegra_##_name##_parents, \
+ .num_parents = 1, \
+ };
+
+#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
+ _max_rate, _ops, _parent, _clk_flags) \
+ static const char *tegra_##_name##_parent_names[] = { \
+ #_parent, \
+ }; \
+ static struct clk *tegra_##_name##_parents[] = { \
+ &tegra_##_parent, \
+ }; \
+ static struct clk tegra_##_name; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .flags = _flags, \
+ .reg = _reg, \
+ .max_rate = _max_rate, \
+ .reg_shift = _reg_shift, \
+ }; \
+ static struct clk tegra_##_name = { \
+ .name = #_name, \
+ .ops = &tegra_pll_div_ops, \
+ .hw = &tegra_##_name##_hw.hw, \
+ .parent = &tegra_##_parent, \
+ .parent_names = tegra_##_name##_parent_names, \
+ .parents = tegra_##_name##_parents, \
+ .num_parents = 1, \
+ .flags = _clk_flags, \
+ };
+
+
+static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
+ {32768, 12000000, 366, 1, 1, 0},
+ {32768, 13000000, 397, 1, 1, 0},
+ {32768, 19200000, 586, 1, 1, 0},
+ {32768, 26000000, 793, 1, 1, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+DEFINE_PLL(pll_s, PLL_ALT_MISC_REG, 0xf0, 26000000, 32768, 32768, 0,
+ 0, 12000000, 26000000, tegra_pll_s_freq_table, 300,
+ tegra_pll_ops, 0, clk_32k);
+
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+ { 12000000, 600000000, 600, 12, 1, 8 },
+ { 13000000, 600000000, 600, 13, 1, 8 },
+ { 19200000, 600000000, 500, 16, 1, 6 },
+ { 26000000, 600000000, 600, 26, 1, 8 },
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 600000000, 2000000, 31000000, 1000000,
+ 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
+ tegra_pll_ops, 0, clk_m);
+
+DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 600000000,
+ tegra_pll_div_ops, pll_c, 0);
+
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+ { 12000000, 666000000, 666, 12, 1, 8},
+ { 13000000, 666000000, 666, 13, 1, 8},
+ { 19200000, 666000000, 555, 16, 1, 8},
+ { 26000000, 666000000, 666, 26, 1, 8},
+ { 12000000, 600000000, 600, 12, 1, 8},
+ { 13000000, 600000000, 600, 13, 1, 8},
+ { 19200000, 600000000, 375, 12, 1, 6},
+ { 26000000, 600000000, 600, 26, 1, 8},
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_m, PLL_HAS_CPCON, 0x90, 800000000, 2000000, 31000000, 1000000,
+ 6000000, 20000000, 1200000000, tegra_pll_m_freq_table, 300,
+ tegra_pll_ops, 0, clk_m);
+
+DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
+ tegra_pll_div_ops, pll_m, 0);
+
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+ { 12000000, 216000000, 432, 12, 2, 8},
+ { 13000000, 216000000, 432, 13, 2, 8},
+ { 19200000, 216000000, 90, 4, 2, 1},
+ { 26000000, 216000000, 432, 26, 2, 8},
+ { 12000000, 432000000, 432, 12, 1, 8},
+ { 13000000, 432000000, 432, 13, 1, 8},
+ { 19200000, 432000000, 90, 4, 1, 1},
+ { 26000000, 432000000, 432, 26, 1, 8},
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+
+DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
+ 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
+ tegra_pll_p_freq_table, 300, tegra_pll_ops, 216000000, clk_m);
+
+DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 0,
+ 432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4, 16,
+ 432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 0,
+ 432000000, tegra_pll_div_ops, pll_p, 0);
+DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8, 16,
+ 432000000, tegra_pll_div_ops, pll_p, 0);
+
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+ { 28800000, 56448000, 49, 25, 1, 1},
+ { 28800000, 73728000, 64, 25, 1, 1},
+ { 28800000, 24000000, 5, 6, 1, 1},
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 73728000, 2000000, 31000000, 1000000,
+ 6000000, 20000000, 1400000000, tegra_pll_a_freq_table, 300,
+ tegra_pll_ops, 0, pll_p_out1);
+
+DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 73728000,
+ tegra_pll_div_ops, pll_a, 0);
+
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+ { 12000000, 216000000, 216, 12, 1, 4},
+ { 13000000, 216000000, 216, 13, 1, 4},
+ { 19200000, 216000000, 135, 12, 1, 3},
+ { 26000000, 216000000, 216, 26, 1, 4},
+
+ { 12000000, 594000000, 594, 12, 1, 8},
+ { 13000000, 594000000, 594, 13, 1, 8},
+ { 19200000, 594000000, 495, 16, 1, 8},
+ { 26000000, 594000000, 594, 26, 1, 8},
+
+ { 12000000, 1000000000, 1000, 12, 1, 12},
+ { 13000000, 1000000000, 1000, 13, 1, 12},
+ { 19200000, 1000000000, 625, 12, 1, 8},
+ { 26000000, 1000000000, 1000, 26, 1, 12},
+
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
+ 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
+ 1000, tegra_pll_ops, 0, clk_m);
+
+DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000,
+ tegra_pll_div_ops, pll_d, CLK_SET_RATE_PARENT);
+
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+ { 12000000, 480000000, 960, 12, 2, 0},
+ { 13000000, 480000000, 960, 13, 2, 0},
+ { 19200000, 480000000, 200, 4, 2, 0},
+ { 26000000, 480000000, 960, 26, 2, 0},
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_u, PLLU, 0xc0, 480000000, 2000000, 40000000, 1000000, 6000000,
+ 48000000, 960000000, tegra_pll_u_freq_table, 1000,
+ tegra_pll_ops, 0, clk_m);
+
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+ /* 1 GHz */
+ { 12000000, 1000000000, 1000, 12, 1, 12},
+ { 13000000, 1000000000, 1000, 13, 1, 12},
+ { 19200000, 1000000000, 625, 12, 1, 8},
+ { 26000000, 1000000000, 1000, 26, 1, 12},
+
+ /* 912 MHz */
+ { 12000000, 912000000, 912, 12, 1, 12},
+ { 13000000, 912000000, 912, 13, 1, 12},
+ { 19200000, 912000000, 760, 16, 1, 8},
+ { 26000000, 912000000, 912, 26, 1, 12},
+
+ /* 816 MHz */
+ { 12000000, 816000000, 816, 12, 1, 12},
+ { 13000000, 816000000, 816, 13, 1, 12},
+ { 19200000, 816000000, 680, 16, 1, 8},
+ { 26000000, 816000000, 816, 26, 1, 12},
+
+ /* 760 MHz */
+ { 12000000, 760000000, 760, 12, 1, 12},
+ { 13000000, 760000000, 760, 13, 1, 12},
+ { 19200000, 760000000, 950, 24, 1, 8},
+ { 26000000, 760000000, 760, 26, 1, 12},
+
+ /* 750 MHz */
+ { 12000000, 750000000, 750, 12, 1, 12},
+ { 13000000, 750000000, 750, 13, 1, 12},
+ { 19200000, 750000000, 625, 16, 1, 8},
+ { 26000000, 750000000, 750, 26, 1, 12},
+
+ /* 608 MHz */
+ { 12000000, 608000000, 608, 12, 1, 12},
+ { 13000000, 608000000, 608, 13, 1, 12},
+ { 19200000, 608000000, 380, 12, 1, 8},
+ { 26000000, 608000000, 608, 26, 1, 12},
+
+ /* 456 MHz */
+ { 12000000, 456000000, 456, 12, 1, 12},
+ { 13000000, 456000000, 456, 13, 1, 12},
+ { 19200000, 456000000, 380, 16, 1, 8},
+ { 26000000, 456000000, 456, 26, 1, 12},
+
+ /* 312 MHz */
+ { 12000000, 312000000, 312, 12, 1, 12},
+ { 13000000, 312000000, 312, 13, 1, 12},
+ { 19200000, 312000000, 260, 16, 1, 8},
+ { 26000000, 312000000, 312, 26, 1, 12},
+
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG, 0xe0, 1000000000, 2000000,
+ 31000000, 1000000, 6000000, 20000000, 1200000000,
+ tegra_pll_x_freq_table, 300, tegra_pllx_ops, 0, clk_m);
+
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+ { 12000000, 100000000, 200, 24, 1, 0 },
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 12000000, 12000000, 0, 0,
+ 0, 0, tegra_pll_e_freq_table, 0, tegra_plle_ops, 0, clk_m);
+
+static const char *tegra_common_parent_names[] = {
+ "clk_m",
+};
+
+static struct clk *tegra_common_parents[] = {
+ &tegra_clk_m,
+};
+
+static struct clk tegra_clk_d;
+static struct clk_tegra tegra_clk_d_hw = {
+ .hw = {
+ .clk = &tegra_clk_d,
+ },
+ .flags = PERIPH_NO_RESET,
+ .reg = 0x34,
+ .reg_shift = 12,
+ .max_rate = 52000000,
+ .u.periph = {
+ .clk_num = 90,
+ },
+};
+
+static struct clk tegra_clk_d = {
+ .name = "clk_d",
+ .hw = &tegra_clk_d_hw.hw,
+ .ops = &tegra_clk_double_ops,
+ .parent = &tegra_clk_m,
+ .parent_names = tegra_common_parent_names,
+ .parents = tegra_common_parents,
+ .num_parents = ARRAY_SIZE(tegra_common_parent_names),
+};
+
+static struct clk tegra_cdev1;
+static struct clk_tegra tegra_cdev1_hw = {
+ .hw = {
+ .clk = &tegra_cdev1,
+ },
+ .fixed_rate = 26000000,
+ .u.periph = {
+ .clk_num = 94,
+ },
+};
+static struct clk tegra_cdev1 = {
+ .name = "cdev1",
+ .hw = &tegra_cdev1_hw.hw,
+ .ops = &tegra_cdev_clk_ops,
+ .flags = CLK_IS_ROOT,
+};
+
+/* dap_mclk2, belongs to the cdev2 pingroup. */
+static struct clk tegra_cdev2;
+static struct clk_tegra tegra_cdev2_hw = {
+ .hw = {
+ .clk = &tegra_cdev2,
+ },
+ .fixed_rate = 26000000,
+ .u.periph = {
+ .clk_num = 93,
+ },
+};
+static struct clk tegra_cdev2 = {
+ .name = "cdev2",
+ .hw = &tegra_cdev2_hw.hw,
+ .ops = &tegra_cdev_clk_ops,
+ .flags = CLK_IS_ROOT,
+};
+
+/* initialized before peripheral clocks */
+static struct clk_mux_sel mux_audio_sync_clk[8+1];
+static const struct audio_sources {
+ const char *name;
+ int value;
+} mux_audio_sync_clk_sources[] = {
+ { .name = "spdif_in", .value = 0 },
+ { .name = "i2s1", .value = 1 },
+ { .name = "i2s2", .value = 2 },
+ { .name = "pll_a_out0", .value = 4 },
+#if 0 /* FIXME: not implemented */
+ { .name = "ac97", .value = 3 },
+ { .name = "ext_audio_clk2", .value = 5 },
+ { .name = "ext_audio_clk1", .value = 6 },
+ { .name = "ext_vimclk", .value = 7 },
+#endif
+ { NULL, 0 }
+};
+
+static const char *audio_parent_names[] = {
+ "spdif_in",
+ "i2s1",
+ "i2s2",
+ "dummy",
+ "pll_a_out0",
+ "dummy",
+ "dummy",
+ "dummy",
+};
+
+static struct clk *audio_parents[] = {
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+ NULL,
+};
+
+static struct clk tegra_audio;
+static struct clk_tegra tegra_audio_hw = {
+ .hw = {
+ .clk = &tegra_audio,
+ },
+ .reg = 0x38,
+ .max_rate = 73728000,
+};
+DEFINE_CLK_TEGRA(audio, 0, &tegra_audio_sync_clk_ops, 0, audio_parent_names,
+ audio_parents, NULL);
+
+static const char *audio_2x_parent_names[] = {
+ "audio",
+};
+
+static struct clk *audio_2x_parents[] = {
+ &tegra_audio,
+};
+
+static struct clk tegra_audio_2x;
+static struct clk_tegra tegra_audio_2x_hw = {
+ .hw = {
+ .clk = &tegra_audio_2x,
+ },
+ .flags = PERIPH_NO_RESET,
+ .max_rate = 48000000,
+ .reg = 0x34,
+ .reg_shift = 8,
+ .u.periph = {
+ .clk_num = 89,
+ },
+};
+DEFINE_CLK_TEGRA(audio_2x, 0, &tegra_clk_double_ops, 0, audio_2x_parent_names,
+ audio_2x_parents, &tegra_audio);
+
+static struct clk_lookup tegra_audio_clk_lookups[] = {
+ { .con_id = "audio", .clk = &tegra_audio },
+ { .con_id = "audio_2x", .clk = &tegra_audio_2x }
+};
+
+/* This is called after peripheral clocks are initialized, as the
+ * audio_sync clock depends on some of the peripheral clocks.
+ */
+
+static void init_audio_sync_clock_mux(void)
+{
+ int i;
+ struct clk_mux_sel *sel = mux_audio_sync_clk;
+ const struct audio_sources *src = mux_audio_sync_clk_sources;
+ struct clk_lookup *lookup;
+
+ for (i = 0; src->name; i++, sel++, src++) {
+ sel->input = tegra_get_clock_by_name(src->name);
+ if (!sel->input)
+ pr_err("%s: could not find clk %s\n", __func__,
+ src->name);
+ audio_parents[src->value] = sel->input;
+ sel->value = src->value;
+ }
+
+ lookup = tegra_audio_clk_lookups;
+ for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
+ struct clk *c = lookup->clk;
+ struct clk_tegra *clk = to_clk_tegra(c->hw);
+ __clk_init(NULL, c);
+ INIT_LIST_HEAD(&clk->shared_bus_list);
+ clk->lookup.con_id = lookup->con_id;
+ clk->lookup.clk = c;
+ clkdev_add(&clk->lookup);
+ tegra_clk_add(c);
+ }
+}
+
+static const char *mux_cclk[] = {
+ "clk_m",
+ "pll_c",
+ "clk_32k",
+ "pll_m",
+ "pll_p",
+ "pll_p_out4",
+ "pll_p_out3",
+ "clk_d",
+ "pll_x",
+};
+
+
+static struct clk *mux_cclk_p[] = {
+ &tegra_clk_m,
+ &tegra_pll_c,
+ &tegra_clk_32k,
+ &tegra_pll_m,
+ &tegra_pll_p,
+ &tegra_pll_p_out4,
+ &tegra_pll_p_out3,
+ &tegra_clk_d,
+ &tegra_pll_x,
+};
+
+static const char *mux_sclk[] = {
+ "clk_m",
+ "pll_c_out1",
+ "pll_p_out4",
+ "pllp_p_out3",
+ "pll_p_out2",
+ "clk_d",
+ "clk_32k",
+ "pll_m_out1",
+};
+
+static struct clk *mux_sclk_p[] = {
+ &tegra_clk_m,
+ &tegra_pll_c_out1,
+ &tegra_pll_p_out4,
+ &tegra_pll_p_out3,
+ &tegra_pll_p_out2,
+ &tegra_clk_d,
+ &tegra_clk_32k,
+ &tegra_pll_m_out1,
+};
+
+static struct clk tegra_cclk;
+static struct clk_tegra tegra_cclk_hw = {
+ .hw = {
+ .clk = &tegra_cclk,
+ },
+ .reg = 0x20,
+ .max_rate = 1000000000,
+};
+DEFINE_CLK_TEGRA(cclk, 0, &tegra_super_ops, 0, mux_cclk,
+ mux_cclk_p, NULL);
+
+static const char *mux_twd[] = {
+ "cclk",
+};
+
+static struct clk *mux_twd_p[] = {
+ &tegra_cclk,
+};
+
+static struct clk tegra_clk_twd;
+static struct clk_tegra tegra_clk_twd_hw = {
+ .hw = {
+ .clk = &tegra_clk_twd,
+ },
+ .max_rate = 1000000000,
+ .mul = 1,
+ .div = 4,
+};
+
+static struct clk tegra_clk_twd = {
+ .name = "twd",
+ .ops = &tegra_twd_ops,
+ .hw = &tegra_clk_twd_hw.hw,
+ .parent = &tegra_cclk,
+ .parent_names = mux_twd,
+ .parents = mux_twd_p,
+ .num_parents = ARRAY_SIZE(mux_twd),
+};
+
+static struct clk tegra_sclk;
+static struct clk_tegra tegra_sclk_hw = {
+ .hw = {
+ .clk = &tegra_sclk,
+ },
+ .reg = 0x28,
+ .max_rate = 240000000,
+ .min_rate = 120000000,
+};
+DEFINE_CLK_TEGRA(sclk, 0, &tegra_super_ops, 0, mux_sclk,
+ mux_sclk_p, NULL);
+
+static const char *tegra_cop_parent_names[] = {
+ "tegra_sclk",
+};
+
+static struct clk *tegra_cop_parents[] = {
+ &tegra_sclk,
+};
+
+static struct clk tegra_cop;
+static struct clk_tegra tegra_cop_hw = {
+ .hw = {
+ .clk = &tegra_cop,
+ },
+ .max_rate = 240000000,
+ .reset = &tegra2_cop_clk_reset,
+};
+DEFINE_CLK_TEGRA(cop, 0, &tegra_cop_ops, CLK_SET_RATE_PARENT,
+ tegra_cop_parent_names, tegra_cop_parents, &tegra_sclk);
+
+static const char *tegra_hclk_parent_names[] = {
+ "tegra_sclk",
+};
+
+static struct clk *tegra_hclk_parents[] = {
+ &tegra_sclk,
+};
+
+static struct clk tegra_hclk;
+static struct clk_tegra tegra_hclk_hw = {
+ .hw = {
+ .clk = &tegra_hclk,
+ },
+ .flags = DIV_BUS,
+ .reg = 0x30,
+ .reg_shift = 4,
+ .max_rate = 240000000,
+};
+DEFINE_CLK_TEGRA(hclk, 0, &tegra_bus_ops, 0, tegra_hclk_parent_names,
+ tegra_hclk_parents, &tegra_sclk);
+
+static const char *tegra_pclk_parent_names[] = {
+ "tegra_hclk",
+};
+
+static struct clk *tegra_pclk_parents[] = {
+ &tegra_hclk,
+};
+
+static struct clk tegra_pclk;
+static struct clk_tegra tegra_pclk_hw = {
+ .hw = {
+ .clk = &tegra_pclk,
+ },
+ .flags = DIV_BUS,
+ .reg = 0x30,
+ .reg_shift = 0,
+ .max_rate = 120000000,
+};
+DEFINE_CLK_TEGRA(pclk, 0, &tegra_bus_ops, 0, tegra_pclk_parent_names,
+ tegra_pclk_parents, &tegra_hclk);
+
+static const char *tegra_blink_parent_names[] = {
+ "clk_32k",
+};
+
+static struct clk *tegra_blink_parents[] = {
+ &tegra_clk_32k,
+};
+
+static struct clk tegra_blink;
+static struct clk_tegra tegra_blink_hw = {
+ .hw = {
+ .clk = &tegra_blink,
+ },
+ .reg = 0x40,
+ .max_rate = 32768,
+};
+DEFINE_CLK_TEGRA(blink, 0, &tegra_blink_clk_ops, 0, tegra_blink_parent_names,
+ tegra_blink_parents, &tegra_clk_32k);
+
+static const char *mux_pllm_pllc_pllp_plla[] = {
+ "pll_m",
+ "pll_c",
+ "pll_p",
+ "pll_a_out0",
+};
+
+static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
+ &tegra_pll_m,
+ &tegra_pll_c,
+ &tegra_pll_p,
+ &tegra_pll_a_out0,
+};
+
+static const char *mux_pllm_pllc_pllp_clkm[] = {
+ "pll_m",
+ "pll_c",
+ "pll_p",
+ "clk_m",
+};
+
+static struct clk *mux_pllm_pllc_pllp_clkm_p[] = {
+ &tegra_pll_m,
+ &tegra_pll_c,
+ &tegra_pll_p,
+ &tegra_clk_m,
+};
+
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+ "pll_p",
+ "pll_c",
+ "pll_m",
+ "clk_m",
+};
+
+static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_c,
+ &tegra_pll_m,
+ &tegra_clk_m,
+};
+
+static const char *mux_pllaout0_audio2x_pllp_clkm[] = {
+ "pll_a_out0",
+ "audio_2x",
+ "pll_p",
+ "clk_m",
+};
+
+static struct clk *mux_pllaout0_audio2x_pllp_clkm_p[] = {
+ &tegra_pll_a_out0,
+ &tegra_audio_2x,
+ &tegra_pll_p,
+ &tegra_clk_m,
+};
+
+static const char *mux_pllp_plld_pllc_clkm[] = {
+ "pllp",
+ "pll_d_out0",
+ "pll_c",
+ "clk_m",
+};
+
+static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_d_out0,
+ &tegra_pll_c,
+ &tegra_clk_m,
+};
+
+static const char *mux_pllp_pllc_audio_clkm_clk32[] = {
+ "pll_p",
+ "pll_c",
+ "audio",
+ "clk_m",
+ "clk_32k",
+};
+
+static struct clk *mux_pllp_pllc_audio_clkm_clk32_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_c,
+ &tegra_audio,
+ &tegra_clk_m,
+ &tegra_clk_32k,
+};
+
+static const char *mux_pllp_pllc_pllm[] = {
+ "pll_p",
+ "pll_c",
+ "pll_m"
+};
+
+static struct clk *mux_pllp_pllc_pllm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_c,
+ &tegra_pll_m,
+};
+
+static const char *mux_clk_m[] = {
+ "clk_m",
+};
+
+static struct clk *mux_clk_m_p[] = {
+ &tegra_clk_m,
+};
+
+static const char *mux_pllp_out3[] = {
+ "pll_p_out3",
+};
+
+static struct clk *mux_pllp_out3_p[] = {
+ &tegra_pll_p_out3,
+};
+
+static const char *mux_plld[] = {
+ "pll_d",
+};
+
+static struct clk *mux_plld_p[] = {
+ &tegra_pll_d,
+};
+
+static const char *mux_clk_32k[] = {
+ "clk_32k",
+};
+
+static struct clk *mux_clk_32k_p[] = {
+ &tegra_clk_32k,
+};
+
+static const char *mux_pclk[] = {
+ "pclk",
+};
+
+static struct clk *mux_pclk_p[] = {
+ &tegra_pclk,
+};
+
+static struct clk tegra_emc;
+static struct clk_tegra tegra_emc_hw = {
+ .hw = {
+ .clk = &tegra_emc,
+ },
+ .reg = 0x19c,
+ .max_rate = 800000000,
+ .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
+ .reset = &tegra2_periph_clk_reset,
+ .u.periph = {
+ .clk_num = 57,
+ },
+};
+DEFINE_CLK_TEGRA(emc, 0, &tegra_emc_clk_ops, 0, mux_pllm_pllc_pllp_clkm,
+ mux_pllm_pllc_pllp_clkm_p, NULL);
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
+ _max, _inputs, _flags) \
+ static struct clk tegra_##_name; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .lookup = { \
+ .dev_id = _dev, \
+ .con_id = _con, \
+ }, \
+ .reg = _reg, \
+ .flags = _flags, \
+ .max_rate = _max, \
+ .u.periph = { \
+ .clk_num = _clk_num, \
+ }, \
+ .reset = tegra2_periph_clk_reset, \
+ }; \
+ static struct clk tegra_##_name = { \
+ .name = #_name, \
+ .ops = &tegra_periph_clk_ops, \
+ .hw = &tegra_##_name##_hw.hw, \
+ .parent_names = _inputs, \
+ .parents = _inputs##_p, \
+ .num_parents = ARRAY_SIZE(_inputs), \
+ };
+
+PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0);
+PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET);
+PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
+PERIPH_CLK(i2s1, "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
+PERIPH_CLK(i2s2, "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
+PERIPH_CLK(spdif_out, "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71);
+PERIPH_CLK(spdif_in, "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71);
+PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM);
+PERIPH_CLK(spi, "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(xio, "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(twc, "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(ide, "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(vde, "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
+/* FIXME: what is la? */
+PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
+PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
+PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
+PERIPH_CLK(dvc, "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16);
+PERIPH_CLK(i2c1_i2c, "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
+PERIPH_CLK(i2c2_i2c, "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
+PERIPH_CLK(i2c3_i2c, "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
+PERIPH_CLK(dvc_i2c, "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0);
+PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
+PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
+PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
+PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
+PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX);
+PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET); /* scales with voltage and process_id */
+PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET); /* scales with voltage and process_id */
+PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71); /* scales with voltage and process_id */
+PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
+PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX); /* scales with voltage and process_id */
+PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
+PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
+PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
+PERIPH_CLK(dsi, "dsi", NULL, 48, 0, 500000000, mux_plld, 0); /* scales with voltage */
+PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0);
+PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
+PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
+PERIPH_CLK(pex, NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
+PERIPH_CLK(afi, NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
+PERIPH_CLK(pcie_xclk, NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET);
+
+static struct clk *tegra_list_clks[] = {
+ &tegra_apbdma,
+ &tegra_rtc,
+ &tegra_i2s1,
+ &tegra_i2s2,
+ &tegra_spdif_out,
+ &tegra_spdif_in,
+ &tegra_pwm,
+ &tegra_spi,
+ &tegra_xio,
+ &tegra_twc,
+ &tegra_sbc1,
+ &tegra_sbc2,
+ &tegra_sbc3,
+ &tegra_sbc4,
+ &tegra_ide,
+ &tegra_ndflash,
+ &tegra_vfir,
+ &tegra_sdmmc1,
+ &tegra_sdmmc2,
+ &tegra_sdmmc3,
+ &tegra_sdmmc4,
+ &tegra_vcp,
+ &tegra_bsea,
+ &tegra_bsev,
+ &tegra_vde,
+ &tegra_csite,
+ &tegra_la,
+ &tegra_owr,
+ &tegra_nor,
+ &tegra_mipi,
+ &tegra_i2c1,
+ &tegra_i2c2,
+ &tegra_i2c3,
+ &tegra_dvc,
+ &tegra_i2c1_i2c,
+ &tegra_i2c2_i2c,
+ &tegra_i2c3_i2c,
+ &tegra_dvc_i2c,
+ &tegra_uarta,
+ &tegra_uartb,
+ &tegra_uartc,
+ &tegra_uartd,
+ &tegra_uarte,
+ &tegra_3d,
+ &tegra_2d,
+ &tegra_vi,
+ &tegra_vi_sensor,
+ &tegra_epp,
+ &tegra_mpe,
+ &tegra_host1x,
+ &tegra_cve,
+ &tegra_tvo,
+ &tegra_hdmi,
+ &tegra_tvdac,
+ &tegra_disp1,
+ &tegra_disp2,
+ &tegra_usbd,
+ &tegra_usb2,
+ &tegra_usb3,
+ &tegra_dsi,
+ &tegra_csi,
+ &tegra_isp,
+ &tegra_csus,
+ &tegra_pex,
+ &tegra_afi,
+ &tegra_pcie_xclk,
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con) \
+ { \
+ .name = _name, \
+ .lookup = { \
+ .dev_id = _dev, \
+ .con_id = _con, \
+ }, \
+ }
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration. List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+static struct clk_duplicate tegra_clk_duplicates[] = {
+ CLK_DUPLICATE("uarta", "serial8250.0", NULL),
+ CLK_DUPLICATE("uartb", "serial8250.1", NULL),
+ CLK_DUPLICATE("uartc", "serial8250.2", NULL),
+ CLK_DUPLICATE("uartd", "serial8250.3", NULL),
+ CLK_DUPLICATE("uarte", "serial8250.4", NULL),
+ CLK_DUPLICATE("usbd", "utmip-pad", NULL),
+ CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
+ CLK_DUPLICATE("usbd", "tegra-otg", NULL),
+ CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
+ CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
+ CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
+ CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
+ CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
+ CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
+ CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
+ CLK_DUPLICATE("cop", "tegra-avp", "cop"),
+ CLK_DUPLICATE("vde", "tegra-aes", "vde"),
+ CLK_DUPLICATE("cclk", NULL, "cpu"),
+ CLK_DUPLICATE("twd", "smp_twd", NULL),
+};
+
+#define CLK(dev, con, ck) \
+ { \
+ .dev_id = dev, \
+ .con_id = con, \
+ .clk = ck, \
+ }
+
+static struct clk *tegra_ptr_clks[] = {
+ &tegra_clk_32k,
+ &tegra_pll_s,
+ &tegra_clk_m,
+ &tegra_pll_m,
+ &tegra_pll_m_out1,
+ &tegra_pll_c,
+ &tegra_pll_c_out1,
+ &tegra_pll_p,
+ &tegra_pll_p_out1,
+ &tegra_pll_p_out2,
+ &tegra_pll_p_out3,
+ &tegra_pll_p_out4,
+ &tegra_pll_a,
+ &tegra_pll_a_out0,
+ &tegra_pll_d,
+ &tegra_pll_d_out0,
+ &tegra_pll_u,
+ &tegra_pll_x,
+ &tegra_pll_e,
+ &tegra_cclk,
+ &tegra_clk_twd,
+ &tegra_sclk,
+ &tegra_hclk,
+ &tegra_pclk,
+ &tegra_clk_d,
+ &tegra_cdev1,
+ &tegra_cdev2,
+ &tegra_blink,
+ &tegra_cop,
+ &tegra_emc,
+};
+
+static void tegra2_init_one_clock(struct clk *c)
+{
+ struct clk_tegra *clk = to_clk_tegra(c->hw);
+ int ret;
+
+ ret = __clk_init(NULL, c);
+ if (ret)
+ pr_err("clk init failed %s\n", __clk_get_name(c));
+
+ INIT_LIST_HEAD(&clk->shared_bus_list);
+ if (!clk->lookup.dev_id && !clk->lookup.con_id)
+ clk->lookup.con_id = c->name;
+ clk->lookup.clk = c;
+ clkdev_add(&clk->lookup);
+ tegra_clk_add(c);
+}
+
+void __init tegra2_init_clocks(void)
+{
+ int i;
+ struct clk *c;
+
+ for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+ tegra2_init_one_clock(tegra_ptr_clks[i]);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+ tegra2_init_one_clock(tegra_list_clks[i]);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+ c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+ if (!c) {
+ pr_err("%s: Unknown duplicate clock %s\n", __func__,
+ tegra_clk_duplicates[i].name);
+ continue;
+ }
+
+ tegra_clk_duplicates[i].lookup.clk = c;
+ clkdev_add(&tegra_clk_duplicates[i].lookup);
+ }
+
+ init_audio_sync_clock_mux();
+ tegra20_cpu_car_ops_init();
+}
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
deleted file mode 100644
index a703844..0000000
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ /dev/null
@@ -1,2484 +0,0 @@
-/*
- * arch/arm/mach-tegra/tegra2_clocks.c
- *
- * Copyright (C) 2010 Google, Inc.
- *
- * Author:
- * Colin Cross <ccross@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-#include <linux/clk.h>
-
-#include <mach/iomap.h>
-#include <mach/suspend.h>
-
-#include "clock.h"
-#include "fuse.h"
-#include "tegra2_emc.h"
-
-#define RST_DEVICES 0x004
-#define RST_DEVICES_SET 0x300
-#define RST_DEVICES_CLR 0x304
-#define RST_DEVICES_NUM 3
-
-#define CLK_OUT_ENB 0x010
-#define CLK_OUT_ENB_SET 0x320
-#define CLK_OUT_ENB_CLR 0x324
-#define CLK_OUT_ENB_NUM 3
-
-#define CLK_MASK_ARM 0x44
-#define MISC_CLK_ENB 0x48
-
-#define OSC_CTRL 0x50
-#define OSC_CTRL_OSC_FREQ_MASK (3<<30)
-#define OSC_CTRL_OSC_FREQ_13MHZ (0<<30)
-#define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30)
-#define OSC_CTRL_OSC_FREQ_12MHZ (2<<30)
-#define OSC_CTRL_OSC_FREQ_26MHZ (3<<30)
-#define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK)
-
-#define OSC_FREQ_DET 0x58
-#define OSC_FREQ_DET_TRIG (1<<31)
-
-#define OSC_FREQ_DET_STATUS 0x5C
-#define OSC_FREQ_DET_BUSY (1<<31)
-#define OSC_FREQ_DET_CNT_MASK 0xFFFF
-
-#define PERIPH_CLK_SOURCE_I2S1 0x100
-#define PERIPH_CLK_SOURCE_EMC 0x19c
-#define PERIPH_CLK_SOURCE_OSC 0x1fc
-#define PERIPH_CLK_SOURCE_NUM \
- ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4)
-
-#define PERIPH_CLK_SOURCE_MASK (3<<30)
-#define PERIPH_CLK_SOURCE_SHIFT 30
-#define PERIPH_CLK_SOURCE_PWM_MASK (7<<28)
-#define PERIPH_CLK_SOURCE_PWM_SHIFT 28
-#define PERIPH_CLK_SOURCE_ENABLE (1<<28)
-#define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF
-#define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF
-#define PERIPH_CLK_SOURCE_DIV_SHIFT 0
-
-#define SDMMC_CLK_INT_FB_SEL (1 << 23)
-#define SDMMC_CLK_INT_FB_DLY_SHIFT 16
-#define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT)
-
-#define PLL_BASE 0x0
-#define PLL_BASE_BYPASS (1<<31)
-#define PLL_BASE_ENABLE (1<<30)
-#define PLL_BASE_REF_ENABLE (1<<29)
-#define PLL_BASE_OVERRIDE (1<<28)
-#define PLL_BASE_DIVP_MASK (0x7<<20)
-#define PLL_BASE_DIVP_SHIFT 20
-#define PLL_BASE_DIVN_MASK (0x3FF<<8)
-#define PLL_BASE_DIVN_SHIFT 8
-#define PLL_BASE_DIVM_MASK (0x1F)
-#define PLL_BASE_DIVM_SHIFT 0
-
-#define PLL_OUT_RATIO_MASK (0xFF<<8)
-#define PLL_OUT_RATIO_SHIFT 8
-#define PLL_OUT_OVERRIDE (1<<2)
-#define PLL_OUT_CLKEN (1<<1)
-#define PLL_OUT_RESET_DISABLE (1<<0)
-
-#define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc)
-
-#define PLL_MISC_DCCON_SHIFT 20
-#define PLL_MISC_CPCON_SHIFT 8
-#define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT)
-#define PLL_MISC_LFCON_SHIFT 4
-#define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT)
-#define PLL_MISC_VCOCON_SHIFT 0
-#define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT)
-
-#define PLLU_BASE_POST_DIV (1<<20)
-
-#define PLLD_MISC_CLKENABLE (1<<30)
-#define PLLD_MISC_DIV_RST (1<<23)
-#define PLLD_MISC_DCCON_SHIFT 12
-
-#define PLLE_MISC_READY (1 << 15)
-
-#define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4)
-#define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8)
-#define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32))
-
-#define SUPER_CLK_MUX 0x00
-#define SUPER_STATE_SHIFT 28
-#define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT)
-#define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT)
-#define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT)
-#define SUPER_SOURCE_MASK 0xF
-#define SUPER_FIQ_SOURCE_SHIFT 12
-#define SUPER_IRQ_SOURCE_SHIFT 8
-#define SUPER_RUN_SOURCE_SHIFT 4
-#define SUPER_IDLE_SOURCE_SHIFT 0
-
-#define SUPER_CLK_DIVIDER 0x04
-
-#define BUS_CLK_DISABLE (1<<3)
-#define BUS_CLK_DIV_MASK 0x3
-
-#define PMC_CTRL 0x0
- #define PMC_CTRL_BLINK_ENB (1 << 7)
-
-#define PMC_DPD_PADS_ORIDE 0x1c
- #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20)
-
-#define PMC_BLINK_TIMER_DATA_ON_SHIFT 0
-#define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff
-#define PMC_BLINK_TIMER_ENB (1 << 15)
-#define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16
-#define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff
-
-static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE);
-static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE);
-
-/*
- * Some clocks share a register with other clocks. Any clock op that
- * non-atomically modifies a register used by another clock must lock
- * clock_register_lock first.
- */
-static DEFINE_SPINLOCK(clock_register_lock);
-
-/*
- * Some peripheral clocks share an enable bit, so refcount the enable bits
- * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U
- */
-static int tegra_periph_clk_enable_refcount[3 * 32];
-
-#define clk_writel(value, reg) \
- __raw_writel(value, reg_clk_base + (reg))
-#define clk_readl(reg) \
- __raw_readl(reg_clk_base + (reg))
-#define pmc_writel(value, reg) \
- __raw_writel(value, reg_pmc_base + (reg))
-#define pmc_readl(reg) \
- __raw_readl(reg_pmc_base + (reg))
-
-static unsigned long clk_measure_input_freq(void)
-{
- u32 clock_autodetect;
- clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET);
- do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY);
- clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS);
- if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) {
- return 12000000;
- } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) {
- return 13000000;
- } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) {
- return 19200000;
- } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) {
- return 26000000;
- } else {
- pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect);
- BUG();
- return 0;
- }
-}
-
-static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate)
-{
- s64 divider_u71 = parent_rate * 2;
- divider_u71 += rate - 1;
- do_div(divider_u71, rate);
-
- if (divider_u71 - 2 < 0)
- return 0;
-
- if (divider_u71 - 2 > 255)
- return -EINVAL;
-
- return divider_u71 - 2;
-}
-
-static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate)
-{
- s64 divider_u16;
-
- divider_u16 = parent_rate;
- divider_u16 += rate - 1;
- do_div(divider_u16, rate);
-
- if (divider_u16 - 1 < 0)
- return 0;
-
- if (divider_u16 - 1 > 255)
- return -EINVAL;
-
- return divider_u16 - 1;
-}
-
-/* clk_m functions */
-static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c)
-{
- u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK;
-
- c->rate = clk_measure_input_freq();
- switch (c->rate) {
- case 12000000:
- auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
- break;
- case 13000000:
- auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ;
- break;
- case 19200000:
- auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ;
- break;
- case 26000000:
- auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ;
- break;
- default:
- pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
- BUG();
- }
- clk_writel(auto_clock_control, OSC_CTRL);
- return c->rate;
-}
-
-static void tegra2_clk_m_init(struct clk *c)
-{
- pr_debug("%s on clock %s\n", __func__, c->name);
- tegra2_clk_m_autodetect_rate(c);
-}
-
-static int tegra2_clk_m_enable(struct clk *c)
-{
- pr_debug("%s on clock %s\n", __func__, c->name);
- return 0;
-}
-
-static void tegra2_clk_m_disable(struct clk *c)
-{
- pr_debug("%s on clock %s\n", __func__, c->name);
- BUG();
-}
-
-static struct clk_ops tegra_clk_m_ops = {
- .init = tegra2_clk_m_init,
- .enable = tegra2_clk_m_enable,
- .disable = tegra2_clk_m_disable,
-};
-
-/* super clock functions */
-/* "super clocks" on tegra have two-stage muxes and a clock skipping
- * super divider. We will ignore the clock skipping divider, since we
- * can't lower the voltage when using the clock skip, but we can if we
- * lower the PLL frequency.
- */
-static void tegra2_super_clk_init(struct clk *c)
-{
- u32 val;
- int source;
- int shift;
- const struct clk_mux_sel *sel;
- val = clk_readl(c->reg + SUPER_CLK_MUX);
- c->state = ON;
- BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
- ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
- shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
- SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
- source = (val >> shift) & SUPER_SOURCE_MASK;
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (sel->value == source)
- break;
- }
- BUG_ON(sel->input == NULL);
- c->parent = sel->input;
-}
-
-static int tegra2_super_clk_enable(struct clk *c)
-{
- clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
- return 0;
-}
-
-static void tegra2_super_clk_disable(struct clk *c)
-{
- pr_debug("%s on clock %s\n", __func__, c->name);
-
- /* oops - don't disable the CPU clock! */
- BUG();
-}
-
-static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p)
-{
- u32 val;
- const struct clk_mux_sel *sel;
- int shift;
-
- val = clk_readl(c->reg + SUPER_CLK_MUX);
- BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
- ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
- shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
- SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (sel->input == p) {
- val &= ~(SUPER_SOURCE_MASK << shift);
- val |= sel->value << shift;
-
- if (c->refcnt)
- clk_enable(p);
-
- clk_writel(val, c->reg);
-
- if (c->refcnt && c->parent)
- clk_disable(c->parent);
-
- clk_reparent(c, p);
- return 0;
- }
- }
- return -EINVAL;
-}
-
-/*
- * Super clocks have "clock skippers" instead of dividers. Dividing using
- * a clock skipper does not allow the voltage to be scaled down, so instead
- * adjust the rate of the parent clock. This requires that the parent of a
- * super clock have no other children, otherwise the rate will change
- * underneath the other children.
- */
-static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate)
-{
- return clk_set_rate(c->parent, rate);
-}
-
-static struct clk_ops tegra_super_ops = {
- .init = tegra2_super_clk_init,
- .enable = tegra2_super_clk_enable,
- .disable = tegra2_super_clk_disable,
- .set_parent = tegra2_super_clk_set_parent,
- .set_rate = tegra2_super_clk_set_rate,
-};
-
-/* virtual cpu clock functions */
-/* some clocks can not be stopped (cpu, memory bus) while the SoC is running.
- To change the frequency of these clocks, the parent pll may need to be
- reprogrammed, so the clock must be moved off the pll, the pll reprogrammed,
- and then the clock moved back to the pll. To hide this sequence, a virtual
- clock handles it.
- */
-static void tegra2_cpu_clk_init(struct clk *c)
-{
-}
-
-static int tegra2_cpu_clk_enable(struct clk *c)
-{
- return 0;
-}
-
-static void tegra2_cpu_clk_disable(struct clk *c)
-{
- pr_debug("%s on clock %s\n", __func__, c->name);
-
- /* oops - don't disable the CPU clock! */
- BUG();
-}
-
-static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate)
-{
- int ret;
- /*
- * Take an extra reference to the main pll so it doesn't turn
- * off when we move the cpu off of it
- */
- clk_enable(c->u.cpu.main);
-
- ret = clk_set_parent(c->parent, c->u.cpu.backup);
- if (ret) {
- pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name);
- goto out;
- }
-
- if (rate == clk_get_rate(c->u.cpu.backup))
- goto out;
-
- ret = clk_set_rate(c->u.cpu.main, rate);
- if (ret) {
- pr_err("Failed to change cpu pll to %lu\n", rate);
- goto out;
- }
-
- ret = clk_set_parent(c->parent, c->u.cpu.main);
- if (ret) {
- pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name);
- goto out;
- }
-
-out:
- clk_disable(c->u.cpu.main);
- return ret;
-}
-
-static struct clk_ops tegra_cpu_ops = {
- .init = tegra2_cpu_clk_init,
- .enable = tegra2_cpu_clk_enable,
- .disable = tegra2_cpu_clk_disable,
- .set_rate = tegra2_cpu_clk_set_rate,
-};
-
-/* virtual cop clock functions. Used to acquire the fake 'cop' clock to
- * reset the COP block (i.e. AVP) */
-static void tegra2_cop_clk_reset(struct clk *c, bool assert)
-{
- unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
-
- pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert");
- clk_writel(1 << 1, reg);
-}
-
-static struct clk_ops tegra_cop_ops = {
- .reset = tegra2_cop_clk_reset,
-};
-
-/* bus clock functions */
-static void tegra2_bus_clk_init(struct clk *c)
-{
- u32 val = clk_readl(c->reg);
- c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON;
- c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1;
- c->mul = 1;
-}
-
-static int tegra2_bus_clk_enable(struct clk *c)
-{
- u32 val;
- unsigned long flags;
-
- spin_lock_irqsave(&clock_register_lock, flags);
-
- val = clk_readl(c->reg);
- val &= ~(BUS_CLK_DISABLE << c->reg_shift);
- clk_writel(val, c->reg);
-
- spin_unlock_irqrestore(&clock_register_lock, flags);
-
- return 0;
-}
-
-static void tegra2_bus_clk_disable(struct clk *c)
-{
- u32 val;
- unsigned long flags;
-
- spin_lock_irqsave(&clock_register_lock, flags);
-
- val = clk_readl(c->reg);
- val |= BUS_CLK_DISABLE << c->reg_shift;
- clk_writel(val, c->reg);
-
- spin_unlock_irqrestore(&clock_register_lock, flags);
-}
-
-static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate)
-{
- u32 val;
- unsigned long parent_rate = clk_get_rate(c->parent);
- unsigned long flags;
- int ret = -EINVAL;
- int i;
-
- spin_lock_irqsave(&clock_register_lock, flags);
-
- val = clk_readl(c->reg);
- for (i = 1; i <= 4; i++) {
- if (rate == parent_rate / i) {
- val &= ~(BUS_CLK_DIV_MASK << c->reg_shift);
- val |= (i - 1) << c->reg_shift;
- clk_writel(val, c->reg);
- c->div = i;
- c->mul = 1;
- ret = 0;
- break;
- }
- }
-
- spin_unlock_irqrestore(&clock_register_lock, flags);
-
- return ret;
-}
-
-static struct clk_ops tegra_bus_ops = {
- .init = tegra2_bus_clk_init,
- .enable = tegra2_bus_clk_enable,
- .disable = tegra2_bus_clk_disable,
- .set_rate = tegra2_bus_clk_set_rate,
-};
-
-/* Blink output functions */
-
-static void tegra2_blink_clk_init(struct clk *c)
-{
- u32 val;
-
- val = pmc_readl(PMC_CTRL);
- c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
- c->mul = 1;
- val = pmc_readl(c->reg);
-
- if (val & PMC_BLINK_TIMER_ENB) {
- unsigned int on_off;
-
- on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
- PMC_BLINK_TIMER_DATA_ON_MASK;
- val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
- val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
- on_off += val;
- /* each tick in the blink timer is 4 32KHz clocks */
- c->div = on_off * 4;
- } else {
- c->div = 1;
- }
-}
-
-static int tegra2_blink_clk_enable(struct clk *c)
-{
- u32 val;
-
- val = pmc_readl(PMC_DPD_PADS_ORIDE);
- pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-
- val = pmc_readl(PMC_CTRL);
- pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL);
-
- return 0;
-}
-
-static void tegra2_blink_clk_disable(struct clk *c)
-{
- u32 val;
-
- val = pmc_readl(PMC_CTRL);
- pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL);
-
- val = pmc_readl(PMC_DPD_PADS_ORIDE);
- pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
-}
-
-static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate)
-{
- unsigned long parent_rate = clk_get_rate(c->parent);
- if (rate >= parent_rate) {
- c->div = 1;
- pmc_writel(0, c->reg);
- } else {
- unsigned int on_off;
- u32 val;
-
- on_off = DIV_ROUND_UP(parent_rate / 8, rate);
- c->div = on_off * 8;
-
- val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) <<
- PMC_BLINK_TIMER_DATA_ON_SHIFT;
- on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK;
- on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
- val |= on_off;
- val |= PMC_BLINK_TIMER_ENB;
- pmc_writel(val, c->reg);
- }
-
- return 0;
-}
-
-static struct clk_ops tegra_blink_clk_ops = {
- .init = &tegra2_blink_clk_init,
- .enable = &tegra2_blink_clk_enable,
- .disable = &tegra2_blink_clk_disable,
- .set_rate = &tegra2_blink_clk_set_rate,
-};
-
-/* PLL Functions */
-static int tegra2_pll_clk_wait_for_lock(struct clk *c)
-{
- udelay(c->u.pll.lock_delay);
-
- return 0;
-}
-
-static void tegra2_pll_clk_init(struct clk *c)
-{
- u32 val = clk_readl(c->reg + PLL_BASE);
-
- c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
-
- if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
- pr_warning("Clock %s has unknown fixed frequency\n", c->name);
- c->mul = 1;
- c->div = 1;
- } else if (val & PLL_BASE_BYPASS) {
- c->mul = 1;
- c->div = 1;
- } else {
- c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
- c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
- if (c->flags & PLLU)
- c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
- else
- c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1;
- }
-}
-
-static int tegra2_pll_clk_enable(struct clk *c)
-{
- u32 val;
- pr_debug("%s on clock %s\n", __func__, c->name);
-
- val = clk_readl(c->reg + PLL_BASE);
- val &= ~PLL_BASE_BYPASS;
- val |= PLL_BASE_ENABLE;
- clk_writel(val, c->reg + PLL_BASE);
-
- tegra2_pll_clk_wait_for_lock(c);
-
- return 0;
-}
-
-static void tegra2_pll_clk_disable(struct clk *c)
-{
- u32 val;
- pr_debug("%s on clock %s\n", __func__, c->name);
-
- val = clk_readl(c->reg);
- val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
- clk_writel(val, c->reg);
-}
-
-static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate)
-{
- u32 val;
- unsigned long input_rate;
- const struct clk_pll_freq_table *sel;
-
- pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
- input_rate = clk_get_rate(c->parent);
- for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
- if (sel->input_rate == input_rate && sel->output_rate == rate) {
- c->mul = sel->n;
- c->div = sel->m * sel->p;
-
- val = clk_readl(c->reg + PLL_BASE);
- if (c->flags & PLL_FIXED)
- val |= PLL_BASE_OVERRIDE;
- val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK |
- PLL_BASE_DIVM_MASK);
- val |= (sel->m << PLL_BASE_DIVM_SHIFT) |
- (sel->n << PLL_BASE_DIVN_SHIFT);
- BUG_ON(sel->p < 1 || sel->p > 2);
- if (c->flags & PLLU) {
- if (sel->p == 1)
- val |= PLLU_BASE_POST_DIV;
- } else {
- if (sel->p == 2)
- val |= 1 << PLL_BASE_DIVP_SHIFT;
- }
- clk_writel(val, c->reg + PLL_BASE);
-
- if (c->flags & PLL_HAS_CPCON) {
- val = clk_readl(c->reg + PLL_MISC(c));
- val &= ~PLL_MISC_CPCON_MASK;
- val |= sel->cpcon << PLL_MISC_CPCON_SHIFT;
- clk_writel(val, c->reg + PLL_MISC(c));
- }
-
- if (c->state == ON)
- tegra2_pll_clk_enable(c);
-
- return 0;
- }
- }
- return -EINVAL;
-}
-
-static struct clk_ops tegra_pll_ops = {
- .init = tegra2_pll_clk_init,
- .enable = tegra2_pll_clk_enable,
- .disable = tegra2_pll_clk_disable,
- .set_rate = tegra2_pll_clk_set_rate,
-};
-
-static void tegra2_pllx_clk_init(struct clk *c)
-{
- tegra2_pll_clk_init(c);
-
- if (tegra_sku_id == 7)
- c->max_rate = 750000000;
-}
-
-static struct clk_ops tegra_pllx_ops = {
- .init = tegra2_pllx_clk_init,
- .enable = tegra2_pll_clk_enable,
- .disable = tegra2_pll_clk_disable,
- .set_rate = tegra2_pll_clk_set_rate,
-};
-
-static int tegra2_plle_clk_enable(struct clk *c)
-{
- u32 val;
-
- pr_debug("%s on clock %s\n", __func__, c->name);
-
- mdelay(1);
-
- val = clk_readl(c->reg + PLL_BASE);
- if (!(val & PLLE_MISC_READY))
- return -EBUSY;
-
- val = clk_readl(c->reg + PLL_BASE);
- val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS;
- clk_writel(val, c->reg + PLL_BASE);
-
- return 0;
-}
-
-static struct clk_ops tegra_plle_ops = {
- .init = tegra2_pll_clk_init,
- .enable = tegra2_plle_clk_enable,
- .set_rate = tegra2_pll_clk_set_rate,
-};
-
-/* Clock divider ops */
-static void tegra2_pll_div_clk_init(struct clk *c)
-{
- u32 val = clk_readl(c->reg);
- u32 divu71;
- val >>= c->reg_shift;
- c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
- if (!(val & PLL_OUT_RESET_DISABLE))
- c->state = OFF;
-
- if (c->flags & DIV_U71) {
- divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
- c->div = (divu71 + 2);
- c->mul = 2;
- } else if (c->flags & DIV_2) {
- c->div = 2;
- c->mul = 1;
- } else {
- c->div = 1;
- c->mul = 1;
- }
-}
-
-static int tegra2_pll_div_clk_enable(struct clk *c)
-{
- u32 val;
- u32 new_val;
- unsigned long flags;
-
- pr_debug("%s: %s\n", __func__, c->name);
- if (c->flags & DIV_U71) {
- spin_lock_irqsave(&clock_register_lock, flags);
- val = clk_readl(c->reg);
- new_val = val >> c->reg_shift;
- new_val &= 0xFFFF;
-
- new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE;
-
- val &= ~(0xFFFF << c->reg_shift);
- val |= new_val << c->reg_shift;
- clk_writel(val, c->reg);
- spin_unlock_irqrestore(&clock_register_lock, flags);
- return 0;
- } else if (c->flags & DIV_2) {
- BUG_ON(!(c->flags & PLLD));
- spin_lock_irqsave(&clock_register_lock, flags);
- val = clk_readl(c->reg);
- val &= ~PLLD_MISC_DIV_RST;
- clk_writel(val, c->reg);
- spin_unlock_irqrestore(&clock_register_lock, flags);
- return 0;
- }
- return -EINVAL;
-}
-
-static void tegra2_pll_div_clk_disable(struct clk *c)
-{
- u32 val;
- u32 new_val;
- unsigned long flags;
-
- pr_debug("%s: %s\n", __func__, c->name);
- if (c->flags & DIV_U71) {
- spin_lock_irqsave(&clock_register_lock, flags);
- val = clk_readl(c->reg);
- new_val = val >> c->reg_shift;
- new_val &= 0xFFFF;
-
- new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE);
-
- val &= ~(0xFFFF << c->reg_shift);
- val |= new_val << c->reg_shift;
- clk_writel(val, c->reg);
- spin_unlock_irqrestore(&clock_register_lock, flags);
- } else if (c->flags & DIV_2) {
- BUG_ON(!(c->flags & PLLD));
- spin_lock_irqsave(&clock_register_lock, flags);
- val = clk_readl(c->reg);
- val |= PLLD_MISC_DIV_RST;
- clk_writel(val, c->reg);
- spin_unlock_irqrestore(&clock_register_lock, flags);
- }
-}
-
-static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
-{
- u32 val;
- u32 new_val;
- int divider_u71;
- unsigned long parent_rate = clk_get_rate(c->parent);
- unsigned long flags;
-
- pr_debug("%s: %s %lu\n", __func__, c->name, rate);
- if (c->flags & DIV_U71) {
- divider_u71 = clk_div71_get_divider(parent_rate, rate);
- if (divider_u71 >= 0) {
- spin_lock_irqsave(&clock_register_lock, flags);
- val = clk_readl(c->reg);
- new_val = val >> c->reg_shift;
- new_val &= 0xFFFF;
- if (c->flags & DIV_U71_FIXED)
- new_val |= PLL_OUT_OVERRIDE;
- new_val &= ~PLL_OUT_RATIO_MASK;
- new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT;
-
- val &= ~(0xFFFF << c->reg_shift);
- val |= new_val << c->reg_shift;
- clk_writel(val, c->reg);
- c->div = divider_u71 + 2;
- c->mul = 2;
- spin_unlock_irqrestore(&clock_register_lock, flags);
- return 0;
- }
- } else if (c->flags & DIV_2) {
- if (parent_rate == rate * 2)
- return 0;
- }
- return -EINVAL;
-}
-
-static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
-{
- int divider;
- unsigned long parent_rate = clk_get_rate(c->parent);
- pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
- if (c->flags & DIV_U71) {
- divider = clk_div71_get_divider(parent_rate, rate);
- if (divider < 0)
- return divider;
- return DIV_ROUND_UP(parent_rate * 2, divider + 2);
- } else if (c->flags & DIV_2) {
- return DIV_ROUND_UP(parent_rate, 2);
- }
- return -EINVAL;
-}
-
-static struct clk_ops tegra_pll_div_ops = {
- .init = tegra2_pll_div_clk_init,
- .enable = tegra2_pll_div_clk_enable,
- .disable = tegra2_pll_div_clk_disable,
- .set_rate = tegra2_pll_div_clk_set_rate,
- .round_rate = tegra2_pll_div_clk_round_rate,
-};
-
-/* Periph clk ops */
-
-static void tegra2_periph_clk_init(struct clk *c)
-{
- u32 val = clk_readl(c->reg);
- const struct clk_mux_sel *mux = NULL;
- const struct clk_mux_sel *sel;
- u32 shift;
- u32 mask;
-
- if (c->flags & MUX_PWM) {
- shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
- mask = PERIPH_CLK_SOURCE_PWM_MASK;
- } else {
- shift = PERIPH_CLK_SOURCE_SHIFT;
- mask = PERIPH_CLK_SOURCE_MASK;
- }
-
- if (c->flags & MUX) {
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if ((val & mask) >> shift == sel->value)
- mux = sel;
- }
- BUG_ON(!mux);
-
- c->parent = mux->input;
- } else {
- c->parent = c->inputs[0].input;
- }
-
- if (c->flags & DIV_U71) {
- u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
- c->div = divu71 + 2;
- c->mul = 2;
- } else if (c->flags & DIV_U16) {
- u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
- c->div = divu16 + 1;
- c->mul = 1;
- } else {
- c->div = 1;
- c->mul = 1;
- }
-
- c->state = ON;
-
- if (!c->u.periph.clk_num)
- return;
-
- if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
- PERIPH_CLK_TO_ENB_BIT(c)))
- c->state = OFF;
-
- if (!(c->flags & PERIPH_NO_RESET))
- if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) &
- PERIPH_CLK_TO_ENB_BIT(c))
- c->state = OFF;
-}
-
-static int tegra2_periph_clk_enable(struct clk *c)
-{
- u32 val;
- unsigned long flags;
- int refcount;
- pr_debug("%s on clock %s\n", __func__, c->name);
-
- if (!c->u.periph.clk_num)
- return 0;
-
- spin_lock_irqsave(&clock_register_lock, flags);
-
- refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
-
- if (refcount > 1)
- goto out;
-
- clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
- CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
- if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET))
- clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
- RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
- if (c->flags & PERIPH_EMC_ENB) {
- /* The EMC peripheral clock has 2 extra enable bits */
- /* FIXME: Do they need to be disabled? */
- val = clk_readl(c->reg);
- val |= 0x3 << 24;
- clk_writel(val, c->reg);
- }
-
-out:
- spin_unlock_irqrestore(&clock_register_lock, flags);
-
- return 0;
-}
-
-static void tegra2_periph_clk_disable(struct clk *c)
-{
- unsigned long flags;
-
- pr_debug("%s on clock %s\n", __func__, c->name);
-
- if (!c->u.periph.clk_num)
- return;
-
- spin_lock_irqsave(&clock_register_lock, flags);
-
- if (c->refcnt)
- tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
-
- if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0)
- clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
- CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-
- spin_unlock_irqrestore(&clock_register_lock, flags);
-}
-
-static void tegra2_periph_clk_reset(struct clk *c, bool assert)
-{
- unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR;
-
- pr_debug("%s %s on clock %s\n", __func__,
- assert ? "assert" : "deassert", c->name);
-
- BUG_ON(!c->u.periph.clk_num);
-
- if (!(c->flags & PERIPH_NO_RESET))
- clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
- base + PERIPH_CLK_TO_ENB_SET_REG(c));
-}
-
-static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p)
-{
- u32 val;
- const struct clk_mux_sel *sel;
- u32 mask, shift;
-
- pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-
- if (c->flags & MUX_PWM) {
- shift = PERIPH_CLK_SOURCE_PWM_SHIFT;
- mask = PERIPH_CLK_SOURCE_PWM_MASK;
- } else {
- shift = PERIPH_CLK_SOURCE_SHIFT;
- mask = PERIPH_CLK_SOURCE_MASK;
- }
-
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (sel->input == p) {
- val = clk_readl(c->reg);
- val &= ~mask;
- val |= (sel->value) << shift;
-
- if (c->refcnt)
- clk_enable(p);
-
- clk_writel(val, c->reg);
-
- if (c->refcnt && c->parent)
- clk_disable(c->parent);
-
- clk_reparent(c, p);
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
-static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate)
-{
- u32 val;
- int divider;
- unsigned long parent_rate = clk_get_rate(c->parent);
-
- if (c->flags & DIV_U71) {
- divider = clk_div71_get_divider(parent_rate, rate);
- if (divider >= 0) {
- val = clk_readl(c->reg);
- val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK;
- val |= divider;
- clk_writel(val, c->reg);
- c->div = divider + 2;
- c->mul = 2;
- return 0;
- }
- } else if (c->flags & DIV_U16) {
- divider = clk_div16_get_divider(parent_rate, rate);
- if (divider >= 0) {
- val = clk_readl(c->reg);
- val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK;
- val |= divider;
- clk_writel(val, c->reg);
- c->div = divider + 1;
- c->mul = 1;
- return 0;
- }
- } else if (parent_rate <= rate) {
- c->div = 1;
- c->mul = 1;
- return 0;
- }
- return -EINVAL;
-}
-
-static long tegra2_periph_clk_round_rate(struct clk *c,
- unsigned long rate)
-{
- int divider;
- unsigned long parent_rate = clk_get_rate(c->parent);
- pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
- if (c->flags & DIV_U71) {
- divider = clk_div71_get_divider(parent_rate, rate);
- if (divider < 0)
- return divider;
-
- return DIV_ROUND_UP(parent_rate * 2, divider + 2);
- } else if (c->flags & DIV_U16) {
- divider = clk_div16_get_divider(parent_rate, rate);
- if (divider < 0)
- return divider;
- return DIV_ROUND_UP(parent_rate, divider + 1);
- }
- return -EINVAL;
-}
-
-static struct clk_ops tegra_periph_clk_ops = {
- .init = &tegra2_periph_clk_init,
- .enable = &tegra2_periph_clk_enable,
- .disable = &tegra2_periph_clk_disable,
- .set_parent = &tegra2_periph_clk_set_parent,
- .set_rate = &tegra2_periph_clk_set_rate,
- .round_rate = &tegra2_periph_clk_round_rate,
- .reset = &tegra2_periph_clk_reset,
-};
-
-/* The SDMMC controllers have extra bits in the clock source register that
- * adjust the delay between the clock and data to compenstate for delays
- * on the PCB. */
-void tegra2_sdmmc_tap_delay(struct clk *c, int delay)
-{
- u32 reg;
- unsigned long flags;
-
- spin_lock_irqsave(&c->spinlock, flags);
-
- delay = clamp(delay, 0, 15);
- reg = clk_readl(c->reg);
- reg &= ~SDMMC_CLK_INT_FB_DLY_MASK;
- reg |= SDMMC_CLK_INT_FB_SEL;
- reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT;
- clk_writel(reg, c->reg);
-
- spin_unlock_irqrestore(&c->spinlock, flags);
-}
-
-/* External memory controller clock ops */
-static void tegra2_emc_clk_init(struct clk *c)
-{
- tegra2_periph_clk_init(c);
- c->max_rate = clk_get_rate_locked(c);
-}
-
-static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
-{
- long emc_rate;
- long clk_rate;
-
- /*
- * The slowest entry in the EMC clock table that is at least as
- * fast as rate.
- */
- emc_rate = tegra_emc_round_rate(rate);
- if (emc_rate < 0)
- return c->max_rate;
-
- /*
- * The fastest rate the PLL will generate that is at most the
- * requested rate.
- */
- clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
-
- /*
- * If this fails, and emc_rate > clk_rate, it's because the maximum
- * rate in the EMC tables is larger than the maximum rate of the EMC
- * clock. The EMC clock's max rate is the rate it was running when the
- * kernel booted. Such a mismatch is probably due to using the wrong
- * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
- */
- WARN_ONCE(emc_rate != clk_rate,
- "emc_rate %ld != clk_rate %ld",
- emc_rate, clk_rate);
-
- return emc_rate;
-}
-
-static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)
-{
- int ret;
- /*
- * The Tegra2 memory controller has an interlock with the clock
- * block that allows memory shadowed registers to be updated,
- * and then transfer them to the main registers at the same
- * time as the clock update without glitches.
- */
- ret = tegra_emc_set_rate(rate);
- if (ret < 0)
- return ret;
-
- ret = tegra2_periph_clk_set_rate(c, rate);
- udelay(1);
-
- return ret;
-}
-
-static struct clk_ops tegra_emc_clk_ops = {
- .init = &tegra2_emc_clk_init,
- .enable = &tegra2_periph_clk_enable,
- .disable = &tegra2_periph_clk_disable,
- .set_parent = &tegra2_periph_clk_set_parent,
- .set_rate = &tegra2_emc_clk_set_rate,
- .round_rate = &tegra2_emc_clk_round_rate,
- .reset = &tegra2_periph_clk_reset,
-};
-
-/* Clock doubler ops */
-static void tegra2_clk_double_init(struct clk *c)
-{
- c->mul = 2;
- c->div = 1;
- c->state = ON;
-
- if (!c->u.periph.clk_num)
- return;
-
- if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
- PERIPH_CLK_TO_ENB_BIT(c)))
- c->state = OFF;
-};
-
-static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate)
-{
- if (rate != 2 * clk_get_rate(c->parent))
- return -EINVAL;
- c->mul = 2;
- c->div = 1;
- return 0;
-}
-
-static struct clk_ops tegra_clk_double_ops = {
- .init = &tegra2_clk_double_init,
- .enable = &tegra2_periph_clk_enable,
- .disable = &tegra2_periph_clk_disable,
- .set_rate = &tegra2_clk_double_set_rate,
-};
-
-/* Audio sync clock ops */
-static void tegra2_audio_sync_clk_init(struct clk *c)
-{
- int source;
- const struct clk_mux_sel *sel;
- u32 val = clk_readl(c->reg);
- c->state = (val & (1<<4)) ? OFF : ON;
- source = val & 0xf;
- for (sel = c->inputs; sel->input != NULL; sel++)
- if (sel->value == source)
- break;
- BUG_ON(sel->input == NULL);
- c->parent = sel->input;
-}
-
-static int tegra2_audio_sync_clk_enable(struct clk *c)
-{
- clk_writel(0, c->reg);
- return 0;
-}
-
-static void tegra2_audio_sync_clk_disable(struct clk *c)
-{
- clk_writel(1, c->reg);
-}
-
-static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
-{
- u32 val;
- const struct clk_mux_sel *sel;
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (sel->input == p) {
- val = clk_readl(c->reg);
- val &= ~0xf;
- val |= sel->value;
-
- if (c->refcnt)
- clk_enable(p);
-
- clk_writel(val, c->reg);
-
- if (c->refcnt && c->parent)
- clk_disable(c->parent);
-
- clk_reparent(c, p);
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
-static struct clk_ops tegra_audio_sync_clk_ops = {
- .init = tegra2_audio_sync_clk_init,
- .enable = tegra2_audio_sync_clk_enable,
- .disable = tegra2_audio_sync_clk_disable,
- .set_parent = tegra2_audio_sync_clk_set_parent,
-};
-
-/* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */
-
-static void tegra2_cdev_clk_init(struct clk *c)
-{
- /* We could un-tristate the cdev1 or cdev2 pingroup here; this is
- * currently done in the pinmux code. */
- c->state = ON;
-
- BUG_ON(!c->u.periph.clk_num);
-
- if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) &
- PERIPH_CLK_TO_ENB_BIT(c)))
- c->state = OFF;
-}
-
-static int tegra2_cdev_clk_enable(struct clk *c)
-{
- BUG_ON(!c->u.periph.clk_num);
-
- clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
- CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c));
- return 0;
-}
-
-static void tegra2_cdev_clk_disable(struct clk *c)
-{
- BUG_ON(!c->u.periph.clk_num);
-
- clk_writel(PERIPH_CLK_TO_ENB_BIT(c),
- CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c));
-}
-
-static struct clk_ops tegra_cdev_clk_ops = {
- .init = &tegra2_cdev_clk_init,
- .enable = &tegra2_cdev_clk_enable,
- .disable = &tegra2_cdev_clk_disable,
-};
-
-/* shared bus ops */
-/*
- * Some clocks may have multiple downstream users that need to request a
- * higher clock rate. Shared bus clocks provide a unique shared_bus_user
- * clock to each user. The frequency of the bus is set to the highest
- * enabled shared_bus_user clock, with a minimum value set by the
- * shared bus.
- */
-static int tegra_clk_shared_bus_update(struct clk *bus)
-{
- struct clk *c;
- unsigned long rate = bus->min_rate;
-
- list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node)
- if (c->u.shared_bus_user.enabled)
- rate = max(c->u.shared_bus_user.rate, rate);
-
- if (rate == clk_get_rate_locked(bus))
- return 0;
-
- return clk_set_rate_locked(bus, rate);
-};
-
-static void tegra_clk_shared_bus_init(struct clk *c)
-{
- unsigned long flags;
-
- c->max_rate = c->parent->max_rate;
- c->u.shared_bus_user.rate = c->parent->max_rate;
- c->state = OFF;
- c->set = true;
-
- spin_lock_irqsave(&c->parent->spinlock, flags);
-
- list_add_tail(&c->u.shared_bus_user.node,
- &c->parent->shared_bus_list);
-
- spin_unlock_irqrestore(&c->parent->spinlock, flags);
-}
-
-static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate)
-{
- unsigned long flags;
- int ret;
- long new_rate = rate;
-
- new_rate = clk_round_rate(c->parent, new_rate);
- if (new_rate < 0)
- return new_rate;
-
- spin_lock_irqsave(&c->parent->spinlock, flags);
-
- c->u.shared_bus_user.rate = new_rate;
- ret = tegra_clk_shared_bus_update(c->parent);
-
- spin_unlock_irqrestore(&c->parent->spinlock, flags);
-
- return ret;
-}
-
-static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate)
-{
- return clk_round_rate(c->parent, rate);
-}
-
-static int tegra_clk_shared_bus_enable(struct clk *c)
-{
- unsigned long flags;
- int ret;
-
- spin_lock_irqsave(&c->parent->spinlock, flags);
-
- c->u.shared_bus_user.enabled = true;
- ret = tegra_clk_shared_bus_update(c->parent);
-
- spin_unlock_irqrestore(&c->parent->spinlock, flags);
-
- return ret;
-}
-
-static void tegra_clk_shared_bus_disable(struct clk *c)
-{
- unsigned long flags;
- int ret;
-
- spin_lock_irqsave(&c->parent->spinlock, flags);
-
- c->u.shared_bus_user.enabled = false;
- ret = tegra_clk_shared_bus_update(c->parent);
- WARN_ON_ONCE(ret);
-
- spin_unlock_irqrestore(&c->parent->spinlock, flags);
-}
-
-static struct clk_ops tegra_clk_shared_bus_ops = {
- .init = tegra_clk_shared_bus_init,
- .enable = tegra_clk_shared_bus_enable,
- .disable = tegra_clk_shared_bus_disable,
- .set_rate = tegra_clk_shared_bus_set_rate,
- .round_rate = tegra_clk_shared_bus_round_rate,
-};
-
-
-/* Clock definitions */
-static struct clk tegra_clk_32k = {
- .name = "clk_32k",
- .rate = 32768,
- .ops = NULL,
- .max_rate = 32768,
-};
-
-static struct clk_pll_freq_table tegra_pll_s_freq_table[] = {
- {32768, 12000000, 366, 1, 1, 0},
- {32768, 13000000, 397, 1, 1, 0},
- {32768, 19200000, 586, 1, 1, 0},
- {32768, 26000000, 793, 1, 1, 0},
- {0, 0, 0, 0, 0, 0},
-};
-
-static struct clk tegra_pll_s = {
- .name = "pll_s",
- .flags = PLL_ALT_MISC_REG,
- .ops = &tegra_pll_ops,
- .parent = &tegra_clk_32k,
- .max_rate = 26000000,
- .reg = 0xf0,
- .u.pll = {
- .input_min = 32768,
- .input_max = 32768,
- .cf_min = 0, /* FIXME */
- .cf_max = 0, /* FIXME */
- .vco_min = 12000000,
- .vco_max = 26000000,
- .freq_table = tegra_pll_s_freq_table,
- .lock_delay = 300,
- },
-};
-
-static struct clk_mux_sel tegra_clk_m_sel[] = {
- { .input = &tegra_clk_32k, .value = 0},
- { .input = &tegra_pll_s, .value = 1},
- { NULL , 0},
-};
-
-static struct clk tegra_clk_m = {
- .name = "clk_m",
- .flags = ENABLE_ON_INIT,
- .ops = &tegra_clk_m_ops,
- .inputs = tegra_clk_m_sel,
- .reg = 0x1fc,
- .reg_shift = 28,
- .max_rate = 26000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
- { 12000000, 600000000, 600, 12, 1, 8 },
- { 13000000, 600000000, 600, 13, 1, 8 },
- { 19200000, 600000000, 500, 16, 1, 6 },
- { 26000000, 600000000, 600, 26, 1, 8 },
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_c = {
- .name = "pll_c",
- .flags = PLL_HAS_CPCON,
- .ops = &tegra_pll_ops,
- .reg = 0x80,
- .parent = &tegra_clk_m,
- .max_rate = 600000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1400000000,
- .freq_table = tegra_pll_c_freq_table,
- .lock_delay = 300,
- },
-};
-
-static struct clk tegra_pll_c_out1 = {
- .name = "pll_c_out1",
- .ops = &tegra_pll_div_ops,
- .flags = DIV_U71,
- .parent = &tegra_pll_c,
- .reg = 0x84,
- .reg_shift = 0,
- .max_rate = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
- { 12000000, 666000000, 666, 12, 1, 8},
- { 13000000, 666000000, 666, 13, 1, 8},
- { 19200000, 666000000, 555, 16, 1, 8},
- { 26000000, 666000000, 666, 26, 1, 8},
- { 12000000, 600000000, 600, 12, 1, 8},
- { 13000000, 600000000, 600, 13, 1, 8},
- { 19200000, 600000000, 375, 12, 1, 6},
- { 26000000, 600000000, 600, 26, 1, 8},
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_m = {
- .name = "pll_m",
- .flags = PLL_HAS_CPCON,
- .ops = &tegra_pll_ops,
- .reg = 0x90,
- .parent = &tegra_clk_m,
- .max_rate = 800000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1200000000,
- .freq_table = tegra_pll_m_freq_table,
- .lock_delay = 300,
- },
-};
-
-static struct clk tegra_pll_m_out1 = {
- .name = "pll_m_out1",
- .ops = &tegra_pll_div_ops,
- .flags = DIV_U71,
- .parent = &tegra_pll_m,
- .reg = 0x94,
- .reg_shift = 0,
- .max_rate = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
- { 12000000, 216000000, 432, 12, 2, 8},
- { 13000000, 216000000, 432, 13, 2, 8},
- { 19200000, 216000000, 90, 4, 2, 1},
- { 26000000, 216000000, 432, 26, 2, 8},
- { 12000000, 432000000, 432, 12, 1, 8},
- { 13000000, 432000000, 432, 13, 1, 8},
- { 19200000, 432000000, 90, 4, 1, 1},
- { 26000000, 432000000, 432, 26, 1, 8},
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_p = {
- .name = "pll_p",
- .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
- .ops = &tegra_pll_ops,
- .reg = 0xa0,
- .parent = &tegra_clk_m,
- .max_rate = 432000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1400000000,
- .freq_table = tegra_pll_p_freq_table,
- .lock_delay = 300,
- },
-};
-
-static struct clk tegra_pll_p_out1 = {
- .name = "pll_p_out1",
- .ops = &tegra_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa4,
- .reg_shift = 0,
- .max_rate = 432000000,
-};
-
-static struct clk tegra_pll_p_out2 = {
- .name = "pll_p_out2",
- .ops = &tegra_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa4,
- .reg_shift = 16,
- .max_rate = 432000000,
-};
-
-static struct clk tegra_pll_p_out3 = {
- .name = "pll_p_out3",
- .ops = &tegra_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa8,
- .reg_shift = 0,
- .max_rate = 432000000,
-};
-
-static struct clk tegra_pll_p_out4 = {
- .name = "pll_p_out4",
- .ops = &tegra_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa8,
- .reg_shift = 16,
- .max_rate = 432000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
- { 28800000, 56448000, 49, 25, 1, 1},
- { 28800000, 73728000, 64, 25, 1, 1},
- { 28800000, 24000000, 5, 6, 1, 1},
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_a = {
- .name = "pll_a",
- .flags = PLL_HAS_CPCON,
- .ops = &tegra_pll_ops,
- .reg = 0xb0,
- .parent = &tegra_pll_p_out1,
- .max_rate = 73728000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1400000000,
- .freq_table = tegra_pll_a_freq_table,
- .lock_delay = 300,
- },
-};
-
-static struct clk tegra_pll_a_out0 = {
- .name = "pll_a_out0",
- .ops = &tegra_pll_div_ops,
- .flags = DIV_U71,
- .parent = &tegra_pll_a,
- .reg = 0xb4,
- .reg_shift = 0,
- .max_rate = 73728000,
-};
-
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
- { 12000000, 216000000, 216, 12, 1, 4},
- { 13000000, 216000000, 216, 13, 1, 4},
- { 19200000, 216000000, 135, 12, 1, 3},
- { 26000000, 216000000, 216, 26, 1, 4},
-
- { 12000000, 594000000, 594, 12, 1, 8},
- { 13000000, 594000000, 594, 13, 1, 8},
- { 19200000, 594000000, 495, 16, 1, 8},
- { 26000000, 594000000, 594, 26, 1, 8},
-
- { 12000000, 1000000000, 1000, 12, 1, 12},
- { 13000000, 1000000000, 1000, 13, 1, 12},
- { 19200000, 1000000000, 625, 12, 1, 8},
- { 26000000, 1000000000, 1000, 26, 1, 12},
-
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_d = {
- .name = "pll_d",
- .flags = PLL_HAS_CPCON | PLLD,
- .ops = &tegra_pll_ops,
- .reg = 0xd0,
- .parent = &tegra_clk_m,
- .max_rate = 1000000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 40000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 40000000,
- .vco_max = 1000000000,
- .freq_table = tegra_pll_d_freq_table,
- .lock_delay = 1000,
- },
-};
-
-static struct clk tegra_pll_d_out0 = {
- .name = "pll_d_out0",
- .ops = &tegra_pll_div_ops,
- .flags = DIV_2 | PLLD,
- .parent = &tegra_pll_d,
- .max_rate = 500000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
- { 12000000, 480000000, 960, 12, 2, 0},
- { 13000000, 480000000, 960, 13, 2, 0},
- { 19200000, 480000000, 200, 4, 2, 0},
- { 26000000, 480000000, 960, 26, 2, 0},
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_u = {
- .name = "pll_u",
- .flags = PLLU,
- .ops = &tegra_pll_ops,
- .reg = 0xc0,
- .parent = &tegra_clk_m,
- .max_rate = 480000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 40000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 480000000,
- .vco_max = 960000000,
- .freq_table = tegra_pll_u_freq_table,
- .lock_delay = 1000,
- },
-};
-
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
- /* 1 GHz */
- { 12000000, 1000000000, 1000, 12, 1, 12},
- { 13000000, 1000000000, 1000, 13, 1, 12},
- { 19200000, 1000000000, 625, 12, 1, 8},
- { 26000000, 1000000000, 1000, 26, 1, 12},
-
- /* 912 MHz */
- { 12000000, 912000000, 912, 12, 1, 12},
- { 13000000, 912000000, 912, 13, 1, 12},
- { 19200000, 912000000, 760, 16, 1, 8},
- { 26000000, 912000000, 912, 26, 1, 12},
-
- /* 816 MHz */
- { 12000000, 816000000, 816, 12, 1, 12},
- { 13000000, 816000000, 816, 13, 1, 12},
- { 19200000, 816000000, 680, 16, 1, 8},
- { 26000000, 816000000, 816, 26, 1, 12},
-
- /* 760 MHz */
- { 12000000, 760000000, 760, 12, 1, 12},
- { 13000000, 760000000, 760, 13, 1, 12},
- { 19200000, 760000000, 950, 24, 1, 8},
- { 26000000, 760000000, 760, 26, 1, 12},
-
- /* 750 MHz */
- { 12000000, 750000000, 750, 12, 1, 12},
- { 13000000, 750000000, 750, 13, 1, 12},
- { 19200000, 750000000, 625, 16, 1, 8},
- { 26000000, 750000000, 750, 26, 1, 12},
-
- /* 608 MHz */
- { 12000000, 608000000, 608, 12, 1, 12},
- { 13000000, 608000000, 608, 13, 1, 12},
- { 19200000, 608000000, 380, 12, 1, 8},
- { 26000000, 608000000, 608, 26, 1, 12},
-
- /* 456 MHz */
- { 12000000, 456000000, 456, 12, 1, 12},
- { 13000000, 456000000, 456, 13, 1, 12},
- { 19200000, 456000000, 380, 16, 1, 8},
- { 26000000, 456000000, 456, 26, 1, 12},
-
- /* 312 MHz */
- { 12000000, 312000000, 312, 12, 1, 12},
- { 13000000, 312000000, 312, 13, 1, 12},
- { 19200000, 312000000, 260, 16, 1, 8},
- { 26000000, 312000000, 312, 26, 1, 12},
-
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_x = {
- .name = "pll_x",
- .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG,
- .ops = &tegra_pllx_ops,
- .reg = 0xe0,
- .parent = &tegra_clk_m,
- .max_rate = 1000000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1200000000,
- .freq_table = tegra_pll_x_freq_table,
- .lock_delay = 300,
- },
-};
-
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
- { 12000000, 100000000, 200, 24, 1, 0 },
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_e = {
- .name = "pll_e",
- .flags = PLL_ALT_MISC_REG,
- .ops = &tegra_plle_ops,
- .parent = &tegra_clk_m,
- .reg = 0xe8,
- .max_rate = 100000000,
- .u.pll = {
- .input_min = 12000000,
- .input_max = 12000000,
- .freq_table = tegra_pll_e_freq_table,
- },
-};
-
-static struct clk tegra_clk_d = {
- .name = "clk_d",
- .flags = PERIPH_NO_RESET,
- .ops = &tegra_clk_double_ops,
- .reg = 0x34,
- .reg_shift = 12,
- .parent = &tegra_clk_m,
- .max_rate = 52000000,
- .u.periph = {
- .clk_num = 90,
- },
-};
-
-/* dap_mclk1, belongs to the cdev1 pingroup. */
-static struct clk tegra_clk_cdev1 = {
- .name = "cdev1",
- .ops = &tegra_cdev_clk_ops,
- .rate = 26000000,
- .max_rate = 26000000,
- .u.periph = {
- .clk_num = 94,
- },
-};
-
-/* dap_mclk2, belongs to the cdev2 pingroup. */
-static struct clk tegra_clk_cdev2 = {
- .name = "cdev2",
- .ops = &tegra_cdev_clk_ops,
- .rate = 26000000,
- .max_rate = 26000000,
- .u.periph = {
- .clk_num = 93,
- },
-};
-
-/* initialized before peripheral clocks */
-static struct clk_mux_sel mux_audio_sync_clk[8+1];
-static const struct audio_sources {
- const char *name;
- int value;
-} mux_audio_sync_clk_sources[] = {
- { .name = "spdif_in", .value = 0 },
- { .name = "i2s1", .value = 1 },
- { .name = "i2s2", .value = 2 },
- { .name = "pll_a_out0", .value = 4 },
-#if 0 /* FIXME: not implemented */
- { .name = "ac97", .value = 3 },
- { .name = "ext_audio_clk2", .value = 5 },
- { .name = "ext_audio_clk1", .value = 6 },
- { .name = "ext_vimclk", .value = 7 },
-#endif
- { NULL, 0 }
-};
-
-static struct clk tegra_clk_audio = {
- .name = "audio",
- .inputs = mux_audio_sync_clk,
- .reg = 0x38,
- .max_rate = 73728000,
- .ops = &tegra_audio_sync_clk_ops
-};
-
-static struct clk tegra_clk_audio_2x = {
- .name = "audio_2x",
- .flags = PERIPH_NO_RESET,
- .max_rate = 48000000,
- .ops = &tegra_clk_double_ops,
- .reg = 0x34,
- .reg_shift = 8,
- .parent = &tegra_clk_audio,
- .u.periph = {
- .clk_num = 89,
- },
-};
-
-static struct clk_lookup tegra_audio_clk_lookups[] = {
- { .con_id = "audio", .clk = &tegra_clk_audio },
- { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x }
-};
-
-/* This is called after peripheral clocks are initialized, as the
- * audio_sync clock depends on some of the peripheral clocks.
- */
-
-static void init_audio_sync_clock_mux(void)
-{
- int i;
- struct clk_mux_sel *sel = mux_audio_sync_clk;
- const struct audio_sources *src = mux_audio_sync_clk_sources;
- struct clk_lookup *lookup;
-
- for (i = 0; src->name; i++, sel++, src++) {
- sel->input = tegra_get_clock_by_name(src->name);
- if (!sel->input)
- pr_err("%s: could not find clk %s\n", __func__,
- src->name);
- sel->value = src->value;
- }
-
- lookup = tegra_audio_clk_lookups;
- for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) {
- clk_init(lookup->clk);
- clkdev_add(lookup);
- }
-}
-
-static struct clk_mux_sel mux_cclk[] = {
- { .input = &tegra_clk_m, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_clk_32k, .value = 2},
- { .input = &tegra_pll_m, .value = 3},
- { .input = &tegra_pll_p, .value = 4},
- { .input = &tegra_pll_p_out4, .value = 5},
- { .input = &tegra_pll_p_out3, .value = 6},
- { .input = &tegra_clk_d, .value = 7},
- { .input = &tegra_pll_x, .value = 8},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_sclk[] = {
- { .input = &tegra_clk_m, .value = 0},
- { .input = &tegra_pll_c_out1, .value = 1},
- { .input = &tegra_pll_p_out4, .value = 2},
- { .input = &tegra_pll_p_out3, .value = 3},
- { .input = &tegra_pll_p_out2, .value = 4},
- { .input = &tegra_clk_d, .value = 5},
- { .input = &tegra_clk_32k, .value = 6},
- { .input = &tegra_pll_m_out1, .value = 7},
- { NULL, 0},
-};
-
-static struct clk tegra_clk_cclk = {
- .name = "cclk",
- .inputs = mux_cclk,
- .reg = 0x20,
- .ops = &tegra_super_ops,
- .max_rate = 1000000000,
-};
-
-static struct clk tegra_clk_sclk = {
- .name = "sclk",
- .inputs = mux_sclk,
- .reg = 0x28,
- .ops = &tegra_super_ops,
- .max_rate = 240000000,
- .min_rate = 120000000,
-};
-
-static struct clk tegra_clk_virtual_cpu = {
- .name = "cpu",
- .parent = &tegra_clk_cclk,
- .ops = &tegra_cpu_ops,
- .max_rate = 1000000000,
- .u.cpu = {
- .main = &tegra_pll_x,
- .backup = &tegra_pll_p,
- },
-};
-
-static struct clk tegra_clk_cop = {
- .name = "cop",
- .parent = &tegra_clk_sclk,
- .ops = &tegra_cop_ops,
- .max_rate = 240000000,
-};
-
-static struct clk tegra_clk_hclk = {
- .name = "hclk",
- .flags = DIV_BUS,
- .parent = &tegra_clk_sclk,
- .reg = 0x30,
- .reg_shift = 4,
- .ops = &tegra_bus_ops,
- .max_rate = 240000000,
-};
-
-static struct clk tegra_clk_pclk = {
- .name = "pclk",
- .flags = DIV_BUS,
- .parent = &tegra_clk_hclk,
- .reg = 0x30,
- .reg_shift = 0,
- .ops = &tegra_bus_ops,
- .max_rate = 120000000,
-};
-
-static struct clk tegra_clk_blink = {
- .name = "blink",
- .parent = &tegra_clk_32k,
- .reg = 0x40,
- .ops = &tegra_blink_clk_ops,
- .max_rate = 32768,
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
- { .input = &tegra_pll_m, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_pll_p, .value = 2},
- { .input = &tegra_pll_a_out0, .value = 3},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = {
- { .input = &tegra_pll_m, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_pll_p, .value = 2},
- { .input = &tegra_clk_m, .value = 3},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
- { .input = &tegra_pll_p, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_pll_m, .value = 2},
- { .input = &tegra_clk_m, .value = 3},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = {
- {.input = &tegra_pll_a_out0, .value = 0},
- {.input = &tegra_clk_audio_2x, .value = 1},
- {.input = &tegra_pll_p, .value = 2},
- {.input = &tegra_clk_m, .value = 3},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_d_out0, .value = 1},
- {.input = &tegra_pll_c, .value = 2},
- {.input = &tegra_clk_m, .value = 3},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_c, .value = 1},
- {.input = &tegra_clk_audio, .value = 2},
- {.input = &tegra_clk_m, .value = 3},
- {.input = &tegra_clk_32k, .value = 4},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_c, .value = 1},
- {.input = &tegra_pll_m, .value = 2},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_clk_m[] = {
- { .input = &tegra_clk_m, .value = 0},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pllp_out3[] = {
- { .input = &tegra_pll_p_out3, .value = 0},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_plld[] = {
- { .input = &tegra_pll_d, .value = 0},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_clk_32k[] = {
- { .input = &tegra_clk_32k, .value = 0},
- { NULL, 0},
-};
-
-static struct clk_mux_sel mux_pclk[] = {
- { .input = &tegra_clk_pclk, .value = 0},
- { NULL, 0},
-};
-
-static struct clk tegra_clk_emc = {
- .name = "emc",
- .ops = &tegra_emc_clk_ops,
- .reg = 0x19c,
- .max_rate = 800000000,
- .inputs = mux_pllm_pllc_pllp_clkm,
- .flags = MUX | DIV_U71 | PERIPH_EMC_ENB,
- .u.periph = {
- .clk_num = 57,
- },
-};
-
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
- { \
- .name = _name, \
- .lookup = { \
- .dev_id = _dev, \
- .con_id = _con, \
- }, \
- .ops = &tegra_periph_clk_ops, \
- .reg = _reg, \
- .inputs = _inputs, \
- .flags = _flags, \
- .max_rate = _max, \
- .u.periph = { \
- .clk_num = _clk_num, \
- }, \
- }
-
-#define SHARED_CLK(_name, _dev, _con, _parent) \
- { \
- .name = _name, \
- .lookup = { \
- .dev_id = _dev, \
- .con_id = _con, \
- }, \
- .ops = &tegra_clk_shared_bus_ops, \
- .parent = _parent, \
- }
-
-static struct clk tegra_list_clks[] = {
- PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 108000000, mux_pclk, 0),
- PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET),
- PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
- PERIPH_CLK("i2s1", "tegra20-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("i2s2", "tegra20-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71),
- PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71 | MUX_PWM),
- PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */
- PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
- /* FIXME: what is la? */
- PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
- PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
- PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
- PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16),
- PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
- PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
- PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
- PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0),
- PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
- PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
- PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
- PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
- PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX),
- PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */
- PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
- PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
- PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */
- PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
- PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
- PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */
- PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
- PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX), /* scales with voltage and process_id */
- PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
- PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
- PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
- PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */
- PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0),
- PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
- PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
- PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
- PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
- PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET),
-
- SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk),
- SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc),
- SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc),
- SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc),
- SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc),
- SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc),
- SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc),
- SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc),
- SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc),
- SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc),
- SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc),
-};
-
-#define CLK_DUPLICATE(_name, _dev, _con) \
- { \
- .name = _name, \
- .lookup = { \
- .dev_id = _dev, \
- .con_id = _con, \
- }, \
- }
-
-/* Some clocks may be used by different drivers depending on the board
- * configuration. List those here to register them twice in the clock lookup
- * table under two names.
- */
-static struct clk_duplicate tegra_clk_duplicates[] = {
- CLK_DUPLICATE("uarta", "serial8250.0", NULL),
- CLK_DUPLICATE("uartb", "serial8250.1", NULL),
- CLK_DUPLICATE("uartc", "serial8250.2", NULL),
- CLK_DUPLICATE("uartd", "serial8250.3", NULL),
- CLK_DUPLICATE("uarte", "serial8250.4", NULL),
- CLK_DUPLICATE("usbd", "utmip-pad", NULL),
- CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
- CLK_DUPLICATE("usbd", "tegra-otg", NULL),
- CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
- CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
- CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"),
- CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"),
- CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"),
- CLK_DUPLICATE("epp", "tegra_grhost", "epp"),
- CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"),
- CLK_DUPLICATE("cop", "tegra-avp", "cop"),
- CLK_DUPLICATE("vde", "tegra-aes", "vde"),
-};
-
-#define CLK(dev, con, ck) \
- { \
- .dev_id = dev, \
- .con_id = con, \
- .clk = ck, \
- }
-
-static struct clk *tegra_ptr_clks[] = {
- &tegra_clk_32k,
- &tegra_pll_s,
- &tegra_clk_m,
- &tegra_pll_m,
- &tegra_pll_m_out1,
- &tegra_pll_c,
- &tegra_pll_c_out1,
- &tegra_pll_p,
- &tegra_pll_p_out1,
- &tegra_pll_p_out2,
- &tegra_pll_p_out3,
- &tegra_pll_p_out4,
- &tegra_pll_a,
- &tegra_pll_a_out0,
- &tegra_pll_d,
- &tegra_pll_d_out0,
- &tegra_pll_u,
- &tegra_pll_x,
- &tegra_pll_e,
- &tegra_clk_cclk,
- &tegra_clk_sclk,
- &tegra_clk_hclk,
- &tegra_clk_pclk,
- &tegra_clk_d,
- &tegra_clk_cdev1,
- &tegra_clk_cdev2,
- &tegra_clk_virtual_cpu,
- &tegra_clk_blink,
- &tegra_clk_cop,
- &tegra_clk_emc,
-};
-
-static void tegra2_init_one_clock(struct clk *c)
-{
- clk_init(c);
- INIT_LIST_HEAD(&c->shared_bus_list);
- if (!c->lookup.dev_id && !c->lookup.con_id)
- c->lookup.con_id = c->name;
- c->lookup.clk = c;
- clkdev_add(&c->lookup);
-}
-
-void __init tegra2_init_clocks(void)
-{
- int i;
- struct clk *c;
-
- for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
- tegra2_init_one_clock(tegra_ptr_clks[i]);
-
- for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
- tegra2_init_one_clock(&tegra_list_clks[i]);
-
- for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
- c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
- if (!c) {
- pr_err("%s: Unknown duplicate clock %s\n", __func__,
- tegra_clk_duplicates[i].name);
- continue;
- }
-
- tegra_clk_duplicates[i].lookup.clk = c;
- clkdev_add(&tegra_clk_duplicates[i].lookup);
- }
-
- init_audio_sync_clock_mux();
-}
-
-#ifdef CONFIG_PM
-static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM +
- PERIPH_CLK_SOURCE_NUM + 22];
-
-void tegra_clk_suspend(void)
-{
- unsigned long off, i;
- u32 *ctx = clk_rst_suspend;
-
- *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK;
- *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE);
- *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
- *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE);
- *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
- *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE);
- *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
- *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE);
- *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
- *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE);
- *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
-
- *ctx++ = clk_readl(tegra_pll_m_out1.reg);
- *ctx++ = clk_readl(tegra_pll_a_out0.reg);
- *ctx++ = clk_readl(tegra_pll_c_out1.reg);
-
- *ctx++ = clk_readl(tegra_clk_cclk.reg);
- *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
-
- *ctx++ = clk_readl(tegra_clk_sclk.reg);
- *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
- *ctx++ = clk_readl(tegra_clk_pclk.reg);
-
- *ctx++ = clk_readl(tegra_clk_audio.reg);
-
- for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
- off += 4) {
- if (off == PERIPH_CLK_SOURCE_EMC)
- continue;
- *ctx++ = clk_readl(off);
- }
-
- off = RST_DEVICES;
- for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
- *ctx++ = clk_readl(off);
-
- off = CLK_OUT_ENB;
- for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
- *ctx++ = clk_readl(off);
-
- *ctx++ = clk_readl(MISC_CLK_ENB);
- *ctx++ = clk_readl(CLK_MASK_ARM);
-
- BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend));
-}
-
-void tegra_clk_resume(void)
-{
- unsigned long off, i;
- const u32 *ctx = clk_rst_suspend;
- u32 val;
-
- val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK;
- val |= *ctx++;
- clk_writel(val, OSC_CTRL);
-
- clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE);
- clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c));
- clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE);
- clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a));
- clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE);
- clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s));
- clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE);
- clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d));
- clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE);
- clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u));
- udelay(1000);
-
- clk_writel(*ctx++, tegra_pll_m_out1.reg);
- clk_writel(*ctx++, tegra_pll_a_out0.reg);
- clk_writel(*ctx++, tegra_pll_c_out1.reg);
-
- clk_writel(*ctx++, tegra_clk_cclk.reg);
- clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER);
-
- clk_writel(*ctx++, tegra_clk_sclk.reg);
- clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER);
- clk_writel(*ctx++, tegra_clk_pclk.reg);
-
- clk_writel(*ctx++, tegra_clk_audio.reg);
-
- /* enable all clocks before configuring clock sources */
- clk_writel(0xbffffff9ul, CLK_OUT_ENB);
- clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4);
- clk_writel(0x77f01bfful, CLK_OUT_ENB + 8);
- wmb();
-
- for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC;
- off += 4) {
- if (off == PERIPH_CLK_SOURCE_EMC)
- continue;
- clk_writel(*ctx++, off);
- }
- wmb();
-
- off = RST_DEVICES;
- for (i = 0; i < RST_DEVICES_NUM; i++, off += 4)
- clk_writel(*ctx++, off);
- wmb();
-
- off = CLK_OUT_ENB;
- for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4)
- clk_writel(*ctx++, off);
- wmb();
-
- clk_writel(*ctx++, MISC_CLK_ENB);
- clk_writel(*ctx++, CLK_MASK_ARM);
-}
-#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks.c b/arch/arm/mach-tegra/tegra30_clocks.c
index 6674f10..5cd502c 100644
--- a/arch/arm/mach-tegra/tegra30_clocks.c
+++ b/arch/arm/mach-tegra/tegra30_clocks.c
@@ -1,7 +1,7 @@
/*
* arch/arm/mach-tegra/tegra30_clocks.c
*
- * Copyright (c) 2010-2011 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -35,6 +35,7 @@
#include "clock.h"
#include "fuse.h"
+#include "tegra_cpu_car.h"
#define USE_PLL_LOCK_BITS 0
@@ -299,6 +300,16 @@
/* FIXME: recommended safety delay after lock is detected */
#define PLL_POST_LOCK_DELAY 100
+/* Tegra CPU clock and reset control regs */
+#define TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX 0x4c
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET 0x340
+#define TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR 0x344
+#define TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR 0x34c
+#define TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS 0x470
+
+#define CPU_CLOCK(cpu) (0x1 << (8 + cpu))
+#define CPU_RESET(cpu) (0x1111ul << (cpu))
+
/**
* Structure defining the fields for USB UTMI clocks Parameters.
*/
@@ -365,30 +376,32 @@
static int tegra_periph_clk_enable_refcount[CLK_OUT_ENB_NUM * 32];
#define clk_writel(value, reg) \
- __raw_writel(value, (u32)reg_clk_base + (reg))
+ __raw_writel(value, reg_clk_base + (reg))
#define clk_readl(reg) \
- __raw_readl((u32)reg_clk_base + (reg))
+ __raw_readl(reg_clk_base + (reg))
#define pmc_writel(value, reg) \
- __raw_writel(value, (u32)reg_pmc_base + (reg))
+ __raw_writel(value, reg_pmc_base + (reg))
#define pmc_readl(reg) \
- __raw_readl((u32)reg_pmc_base + (reg))
+ __raw_readl(reg_pmc_base + (reg))
#define chipid_readl() \
- __raw_readl((u32)misc_gp_hidrev_base + MISC_GP_HIDREV)
+ __raw_readl(misc_gp_hidrev_base + MISC_GP_HIDREV)
#define clk_writel_delay(value, reg) \
do { \
- __raw_writel((value), (u32)reg_clk_base + (reg)); \
+ __raw_writel((value), reg_clk_base + (reg)); \
udelay(2); \
} while (0)
-
-static inline int clk_set_div(struct clk *c, u32 n)
+static inline int clk_set_div(struct clk_tegra *c, u32 n)
{
- return clk_set_rate(c, (clk_get_rate(c->parent) + n-1) / n);
+ struct clk *clk = c->hw.clk;
+
+ return clk_set_rate(clk,
+ (__clk_get_rate(__clk_get_parent(clk)) + n - 1) / n);
}
static inline u32 periph_clk_to_reg(
- struct clk *c, u32 reg_L, u32 reg_V, int offs)
+ struct clk_tegra *c, u32 reg_L, u32 reg_V, int offs)
{
u32 reg = c->u.periph.clk_num / 32;
BUG_ON(reg >= RST_DEVICES_NUM);
@@ -470,15 +483,32 @@
return divider_u16 - 1;
}
+static unsigned long tegra30_clk_fixed_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ return to_clk_tegra(hw)->fixed_rate;
+}
+
+struct clk_ops tegra30_clk_32k_ops = {
+ .recalc_rate = tegra30_clk_fixed_recalc_rate,
+};
+
/* clk_m functions */
-static unsigned long tegra30_clk_m_autodetect_rate(struct clk *c)
+static unsigned long tegra30_clk_m_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ if (!to_clk_tegra(hw)->fixed_rate)
+ to_clk_tegra(hw)->fixed_rate = clk_measure_input_freq();
+ return to_clk_tegra(hw)->fixed_rate;
+}
+
+static void tegra30_clk_m_init(struct clk_hw *hw)
{
u32 osc_ctrl = clk_readl(OSC_CTRL);
u32 auto_clock_control = osc_ctrl & ~OSC_CTRL_OSC_FREQ_MASK;
u32 pll_ref_div = osc_ctrl & OSC_CTRL_PLL_REF_DIV_MASK;
- c->rate = clk_measure_input_freq();
- switch (c->rate) {
+ switch (to_clk_tegra(hw)->fixed_rate) {
case 12000000:
auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ;
BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_1);
@@ -508,46 +538,44 @@
BUG_ON(pll_ref_div != OSC_CTRL_PLL_REF_DIV_4);
break;
default:
- pr_err("%s: Unexpected clock rate %ld", __func__, c->rate);
+ pr_err("%s: Unexpected clock rate %ld", __func__,
+ to_clk_tegra(hw)->fixed_rate);
BUG();
}
clk_writel(auto_clock_control, OSC_CTRL);
- return c->rate;
}
-static void tegra30_clk_m_init(struct clk *c)
-{
- pr_debug("%s on clock %s\n", __func__, c->name);
- tegra30_clk_m_autodetect_rate(c);
-}
-
-static int tegra30_clk_m_enable(struct clk *c)
-{
- pr_debug("%s on clock %s\n", __func__, c->name);
- return 0;
-}
-
-static void tegra30_clk_m_disable(struct clk *c)
-{
- pr_debug("%s on clock %s\n", __func__, c->name);
- WARN(1, "Attempting to disable main SoC clock\n");
-}
-
-static struct clk_ops tegra_clk_m_ops = {
- .init = tegra30_clk_m_init,
- .enable = tegra30_clk_m_enable,
- .disable = tegra30_clk_m_disable,
+struct clk_ops tegra30_clk_m_ops = {
+ .init = tegra30_clk_m_init,
+ .recalc_rate = tegra30_clk_m_recalc_rate,
};
-static struct clk_ops tegra_clk_m_div_ops = {
- .enable = tegra30_clk_m_enable,
+static unsigned long tegra30_clk_m_div_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = parent_rate;
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+
+ return rate;
+}
+
+struct clk_ops tegra_clk_m_div_ops = {
+ .recalc_rate = tegra30_clk_m_div_recalc_rate,
};
/* PLL reference divider functions */
-static void tegra30_pll_ref_init(struct clk *c)
+static unsigned long tegra30_pll_ref_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long rate = parent_rate;
u32 pll_ref_div = clk_readl(OSC_CTRL) & OSC_CTRL_PLL_REF_DIV_MASK;
- pr_debug("%s on clock %s\n", __func__, c->name);
switch (pll_ref_div) {
case OSC_CTRL_PLL_REF_DIV_1:
@@ -564,13 +592,18 @@
BUG();
}
c->mul = 1;
- c->state = ON;
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+
+ return rate;
}
-static struct clk_ops tegra_pll_ref_ops = {
- .init = tegra30_pll_ref_init,
- .enable = tegra30_clk_m_enable,
- .disable = tegra30_clk_m_disable,
+struct clk_ops tegra_pll_ref_ops = {
+ .recalc_rate = tegra30_pll_ref_recalc_rate,
};
/* super clock functions */
@@ -581,14 +614,33 @@
* only when its parent is a fixed rate PLL, since we can't change PLL rate
* in this case.
*/
-static void tegra30_super_clk_init(struct clk *c)
+static void tegra30_super_clk_init(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ struct clk_tegra *p =
+ to_clk_tegra(__clk_get_hw(__clk_get_parent(hw->clk)));
+
+ c->state = ON;
+ if (c->flags & DIV_U71) {
+ /* Init safe 7.1 divider value (does not affect PLLX path) */
+ clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
+ c->reg + SUPER_CLK_DIVIDER);
+ c->mul = 2;
+ c->div = 2;
+ if (!(p->flags & PLLX))
+ c->div += SUPER_CLOCK_DIV_U71_MIN;
+ } else
+ clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
+}
+
+static u8 tegra30_super_clk_get_parent(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
int source;
int shift;
- const struct clk_mux_sel *sel;
+
val = clk_readl(c->reg + SUPER_CLK_MUX);
- c->state = ON;
BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) &&
((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
@@ -596,41 +648,16 @@
source = (val >> shift) & SUPER_SOURCE_MASK;
if (c->flags & DIV_2)
source |= val & SUPER_LP_DIV2_BYPASS;
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (sel->value == source)
- break;
- }
- BUG_ON(sel->input == NULL);
- c->parent = sel->input;
- if (c->flags & DIV_U71) {
- /* Init safe 7.1 divider value (does not affect PLLX path) */
- clk_writel(SUPER_CLOCK_DIV_U71_MIN << SUPER_CLOCK_DIV_U71_SHIFT,
- c->reg + SUPER_CLK_DIVIDER);
- c->mul = 2;
- c->div = 2;
- if (!(c->parent->flags & PLLX))
- c->div += SUPER_CLOCK_DIV_U71_MIN;
- } else
- clk_writel(0, c->reg + SUPER_CLK_DIVIDER);
+ return source;
}
-static int tegra30_super_clk_enable(struct clk *c)
+static int tegra30_super_clk_set_parent(struct clk_hw *hw, u8 index)
{
- return 0;
-}
-
-static void tegra30_super_clk_disable(struct clk *c)
-{
- /* since tegra 3 has 2 CPU super clocks - low power lp-mode clock and
- geared up g-mode super clock - mode switch may request to disable
- either of them; accept request with no affect on h/w */
-}
-
-static int tegra30_super_clk_set_parent(struct clk *c, struct clk *p)
-{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ struct clk_tegra *p =
+ to_clk_tegra(__clk_get_hw(clk_get_parent(hw->clk)));
u32 val;
- const struct clk_mux_sel *sel;
int shift;
val = clk_readl(c->reg + SUPER_CLK_MUX);
@@ -638,48 +665,36 @@
((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE));
shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ?
SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT;
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (sel->input == p) {
- /* For LP mode super-clock switch between PLLX direct
- and divided-by-2 outputs is allowed only when other
- than PLLX clock source is current parent */
- if ((c->flags & DIV_2) && (p->flags & PLLX) &&
- ((sel->value ^ val) & SUPER_LP_DIV2_BYPASS)) {
- if (c->parent->flags & PLLX)
- return -EINVAL;
- val ^= SUPER_LP_DIV2_BYPASS;
- clk_writel_delay(val, c->reg);
- }
- val &= ~(SUPER_SOURCE_MASK << shift);
- val |= (sel->value & SUPER_SOURCE_MASK) << shift;
- /* 7.1 divider for CPU super-clock does not affect
- PLLX path */
- if (c->flags & DIV_U71) {
- u32 div = 0;
- if (!(p->flags & PLLX)) {
- div = clk_readl(c->reg +
- SUPER_CLK_DIVIDER);
- div &= SUPER_CLOCK_DIV_U71_MASK;
- div >>= SUPER_CLOCK_DIV_U71_SHIFT;
- }
- c->div = div + 2;
- c->mul = 2;
- }
-
- if (c->refcnt)
- clk_enable(p);
-
- clk_writel_delay(val, c->reg);
-
- if (c->refcnt && c->parent)
- clk_disable(c->parent);
-
- clk_reparent(c, p);
- return 0;
- }
+ /* For LP mode super-clock switch between PLLX direct
+ and divided-by-2 outputs is allowed only when other
+ than PLLX clock source is current parent */
+ if ((c->flags & DIV_2) && (p->flags & PLLX) &&
+ ((index ^ val) & SUPER_LP_DIV2_BYPASS)) {
+ if (p->flags & PLLX)
+ return -EINVAL;
+ val ^= SUPER_LP_DIV2_BYPASS;
+ clk_writel_delay(val, c->reg);
}
- return -EINVAL;
+ val &= ~(SUPER_SOURCE_MASK << shift);
+ val |= (index & SUPER_SOURCE_MASK) << shift;
+
+ /* 7.1 divider for CPU super-clock does not affect
+ PLLX path */
+ if (c->flags & DIV_U71) {
+ u32 div = 0;
+ if (!(p->flags & PLLX)) {
+ div = clk_readl(c->reg +
+ SUPER_CLK_DIVIDER);
+ div &= SUPER_CLOCK_DIV_U71_MASK;
+ div >>= SUPER_CLOCK_DIV_U71_SHIFT;
+ }
+ c->div = div + 2;
+ c->mul = 2;
+ }
+ clk_writel_delay(val, c->reg);
+
+ return 0;
}
/*
@@ -691,10 +706,15 @@
* rate of this PLL can't be changed, and it has many other children. In
* this case use 7.1 fractional divider to adjust the super clock rate.
*/
-static int tegra30_super_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_super_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
{
- if ((c->flags & DIV_U71) && (c->parent->flags & PLL_FIXED)) {
- int div = clk_div71_get_divider(c->parent->u.pll.fixed_rate,
+ struct clk_tegra *c = to_clk_tegra(hw);
+ struct clk *parent = __clk_get_parent(hw->clk);
+ struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
+
+ if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
+ int div = clk_div71_get_divider(parent_rate,
rate, c->flags, ROUND_DIVIDER_DOWN);
div = max(div, SUPER_CLOCK_DIV_U71_MIN);
@@ -704,55 +724,86 @@
c->mul = 2;
return 0;
}
- return clk_set_rate(c->parent, rate);
-}
-
-static struct clk_ops tegra_super_ops = {
- .init = tegra30_super_clk_init,
- .enable = tegra30_super_clk_enable,
- .disable = tegra30_super_clk_disable,
- .set_parent = tegra30_super_clk_set_parent,
- .set_rate = tegra30_super_clk_set_rate,
-};
-
-static int tegra30_twd_clk_set_rate(struct clk *c, unsigned long rate)
-{
- /* The input value 'rate' is the clock rate of the CPU complex. */
- c->rate = (rate * c->mul) / c->div;
return 0;
}
-static struct clk_ops tegra30_twd_ops = {
- .set_rate = tegra30_twd_clk_set_rate,
+static unsigned long tegra30_super_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = parent_rate;
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+
+ return rate;
+}
+
+static long tegra30_super_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ struct clk *parent = __clk_get_parent(hw->clk);
+ struct clk_tegra *cparent = to_clk_tegra(__clk_get_hw(parent));
+ int mul = 2;
+ int div;
+
+ if ((c->flags & DIV_U71) && (cparent->flags & PLL_FIXED)) {
+ div = clk_div71_get_divider(*prate,
+ rate, c->flags, ROUND_DIVIDER_DOWN);
+ div = max(div, SUPER_CLOCK_DIV_U71_MIN) + 2;
+ rate = *prate * mul;
+ rate += div - 1; /* round up */
+ do_div(rate, c->div);
+
+ return rate;
+ }
+ return *prate;
+}
+
+struct clk_ops tegra30_super_ops = {
+ .init = tegra30_super_clk_init,
+ .set_parent = tegra30_super_clk_set_parent,
+ .get_parent = tegra30_super_clk_get_parent,
+ .recalc_rate = tegra30_super_clk_recalc_rate,
+ .round_rate = tegra30_super_clk_round_rate,
+ .set_rate = tegra30_super_clk_set_rate,
+};
+
+static unsigned long tegra30_twd_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = parent_rate;
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+
+ return rate;
+}
+
+struct clk_ops tegra30_twd_ops = {
+ .recalc_rate = tegra30_twd_clk_recalc_rate,
};
/* Blink output functions */
-
-static void tegra30_blink_clk_init(struct clk *c)
+static int tegra30_blink_clk_is_enabled(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
val = pmc_readl(PMC_CTRL);
c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF;
- c->mul = 1;
- val = pmc_readl(c->reg);
-
- if (val & PMC_BLINK_TIMER_ENB) {
- unsigned int on_off;
-
- on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
- PMC_BLINK_TIMER_DATA_ON_MASK;
- val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
- val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
- on_off += val;
- /* each tick in the blink timer is 4 32KHz clocks */
- c->div = on_off * 4;
- } else {
- c->div = 1;
- }
+ return c->state;
}
-static int tegra30_blink_clk_enable(struct clk *c)
+static int tegra30_blink_clk_enable(struct clk_hw *hw)
{
u32 val;
@@ -765,7 +816,7 @@
return 0;
}
-static void tegra30_blink_clk_disable(struct clk *c)
+static void tegra30_blink_clk_disable(struct clk_hw *hw)
{
u32 val;
@@ -776,9 +827,11 @@
pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE);
}
-static int tegra30_blink_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_blink_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
{
- unsigned long parent_rate = clk_get_rate(c->parent);
+ struct clk_tegra *c = to_clk_tegra(hw);
+
if (rate >= parent_rate) {
c->div = 1;
pmc_writel(0, c->reg);
@@ -801,41 +854,77 @@
return 0;
}
-static struct clk_ops tegra_blink_clk_ops = {
- .init = &tegra30_blink_clk_init,
- .enable = &tegra30_blink_clk_enable,
- .disable = &tegra30_blink_clk_disable,
- .set_rate = &tegra30_blink_clk_set_rate,
-};
-
-/* PLL Functions */
-static int tegra30_pll_clk_wait_for_lock(struct clk *c, u32 lock_reg,
- u32 lock_bit)
+static unsigned long tegra30_blink_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
{
-#if USE_PLL_LOCK_BITS
- int i;
- for (i = 0; i < c->u.pll.lock_delay; i++) {
- if (clk_readl(lock_reg) & lock_bit) {
- udelay(PLL_POST_LOCK_DELAY);
- return 0;
- }
- udelay(2); /* timeout = 2 * lock time */
- }
- pr_err("Timed out waiting for lock bit on pll %s", c->name);
- return -1;
-#endif
- udelay(c->u.pll.lock_delay);
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = parent_rate;
+ u32 val;
+ u32 mul;
+ u32 div;
+ u32 on_off;
- return 0;
+ mul = 1;
+ val = pmc_readl(c->reg);
+
+ if (val & PMC_BLINK_TIMER_ENB) {
+ on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) &
+ PMC_BLINK_TIMER_DATA_ON_MASK;
+ val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT;
+ val &= PMC_BLINK_TIMER_DATA_OFF_MASK;
+ on_off += val;
+ /* each tick in the blink timer is 4 32KHz clocks */
+ div = on_off * 4;
+ } else {
+ div = 1;
+ }
+
+ if (mul != 0 && div != 0) {
+ rate *= mul;
+ rate += div - 1; /* round up */
+ do_div(rate, div);
+ }
+ return rate;
}
-
-static void tegra30_utmi_param_configure(struct clk *c)
+static long tegra30_blink_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
+ int div;
+ int mul;
+ long round_rate = *prate;
+
+ mul = 1;
+
+ if (rate >= *prate) {
+ div = 1;
+ } else {
+ div = DIV_ROUND_UP(*prate / 8, rate);
+ div *= 8;
+ }
+
+ round_rate *= mul;
+ round_rate += div - 1;
+ do_div(round_rate, div);
+
+ return round_rate;
+}
+
+struct clk_ops tegra30_blink_clk_ops = {
+ .is_enabled = tegra30_blink_clk_is_enabled,
+ .enable = tegra30_blink_clk_enable,
+ .disable = tegra30_blink_clk_disable,
+ .recalc_rate = tegra30_blink_clk_recalc_rate,
+ .round_rate = tegra30_blink_clk_round_rate,
+ .set_rate = tegra30_blink_clk_set_rate,
+};
+
+static void tegra30_utmi_param_configure(struct clk_hw *hw)
+{
+ unsigned long main_rate =
+ __clk_get_rate(__clk_get_parent(__clk_get_parent(hw->clk)));
u32 reg;
int i;
- unsigned long main_rate =
- clk_get_rate(c->parent->parent);
for (i = 0; i < ARRAY_SIZE(utmi_parameters); i++) {
if (main_rate == utmi_parameters[i].osc_frequency)
@@ -886,50 +975,52 @@
clk_writel(reg, UTMIP_PLL_CFG1);
}
-static void tegra30_pll_clk_init(struct clk *c)
+/* PLL Functions */
+static int tegra30_pll_clk_wait_for_lock(struct clk_tegra *c, u32 lock_reg,
+ u32 lock_bit)
{
+ int ret = 0;
+
+#if USE_PLL_LOCK_BITS
+ int i;
+ for (i = 0; i < c->u.pll.lock_delay; i++) {
+ if (clk_readl(lock_reg) & lock_bit) {
+ udelay(PLL_POST_LOCK_DELAY);
+ return 0;
+ }
+ udelay(2); /* timeout = 2 * lock time */
+ }
+ pr_err("Timed out waiting for lock bit on pll %s",
+ __clk_get_name(hw->clk));
+ ret = -1;
+#else
+ udelay(c->u.pll.lock_delay);
+#endif
+ return ret;
+}
+
+static int tegra30_pll_clk_is_enabled(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val = clk_readl(c->reg + PLL_BASE);
c->state = (val & PLL_BASE_ENABLE) ? ON : OFF;
-
- if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
- const struct clk_pll_freq_table *sel;
- unsigned long input_rate = clk_get_rate(c->parent);
- for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
- if (sel->input_rate == input_rate &&
- sel->output_rate == c->u.pll.fixed_rate) {
- c->mul = sel->n;
- c->div = sel->m * sel->p;
- return;
- }
- }
- pr_err("Clock %s has unknown fixed frequency\n", c->name);
- BUG();
- } else if (val & PLL_BASE_BYPASS) {
- c->mul = 1;
- c->div = 1;
- } else {
- c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
- c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
- if (c->flags & PLLU)
- c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
- else
- c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
- PLL_BASE_DIVP_SHIFT));
- if (c->flags & PLL_FIXED) {
- unsigned long rate = clk_get_rate_locked(c);
- BUG_ON(rate != c->u.pll.fixed_rate);
- }
- }
-
- if (c->flags & PLLU)
- tegra30_utmi_param_configure(c);
+ return c->state;
}
-static int tegra30_pll_clk_enable(struct clk *c)
+static void tegra30_pll_clk_init(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
+ if (c->flags & PLLU)
+ tegra30_utmi_param_configure(hw);
+}
+
+static int tegra30_pll_clk_enable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
- pr_debug("%s on clock %s\n", __func__, c->name);
+ pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
#if USE_PLL_LOCK_BITS
val = clk_readl(c->reg + PLL_MISC(c));
@@ -952,10 +1043,11 @@
return 0;
}
-static void tegra30_pll_clk_disable(struct clk *c)
+static void tegra30_pll_clk_disable(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
- pr_debug("%s on clock %s\n", __func__, c->name);
+ pr_debug("%s on clock %s\n", __func__, __clk_get_name(hw->clk));
val = clk_readl(c->reg);
val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
@@ -968,36 +1060,36 @@
}
}
-static int tegra30_pll_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_pll_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val, p_div, old_base;
unsigned long input_rate;
const struct clk_pll_freq_table *sel;
struct clk_pll_freq_table cfg;
- pr_debug("%s: %s %lu\n", __func__, c->name, rate);
-
if (c->flags & PLL_FIXED) {
int ret = 0;
if (rate != c->u.pll.fixed_rate) {
pr_err("%s: Can not change %s fixed rate %lu to %lu\n",
- __func__, c->name, c->u.pll.fixed_rate, rate);
+ __func__, __clk_get_name(hw->clk),
+ c->u.pll.fixed_rate, rate);
ret = -EINVAL;
}
return ret;
}
if (c->flags & PLLM) {
- if (rate != clk_get_rate_locked(c)) {
+ if (rate != __clk_get_rate(hw->clk)) {
pr_err("%s: Can not change memory %s rate in flight\n",
- __func__, c->name);
+ __func__, __clk_get_name(hw->clk));
return -EINVAL;
}
- return 0;
}
p_div = 0;
- input_rate = clk_get_rate(c->parent);
+ input_rate = parent_rate;
/* Check if the target rate is tabulated */
for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
@@ -1055,7 +1147,7 @@
(p_div > (PLL_BASE_DIVP_MASK >> PLL_BASE_DIVP_SHIFT)) ||
(cfg.output_rate > c->u.pll.vco_max)) {
pr_err("%s: Failed to set %s out-of-table rate %lu\n",
- __func__, c->name, rate);
+ __func__, __clk_get_name(hw->clk), rate);
return -EINVAL;
}
p_div <<= PLL_BASE_DIVP_SHIFT;
@@ -1073,7 +1165,7 @@
return 0;
if (c->state == ON) {
- tegra30_pll_clk_disable(c);
+ tegra30_pll_clk_disable(hw);
val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE);
}
clk_writel(val, c->reg + PLL_BASE);
@@ -1095,21 +1187,149 @@
}
if (c->state == ON)
- tegra30_pll_clk_enable(c);
+ tegra30_pll_clk_enable(hw);
+
+ c->u.pll.fixed_rate = rate;
return 0;
}
-static struct clk_ops tegra_pll_ops = {
- .init = tegra30_pll_clk_init,
- .enable = tegra30_pll_clk_enable,
- .disable = tegra30_pll_clk_disable,
- .set_rate = tegra30_pll_clk_set_rate,
+static long tegra30_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long input_rate = *prate;
+ unsigned long output_rate = *prate;
+ const struct clk_pll_freq_table *sel;
+ struct clk_pll_freq_table cfg;
+ int mul;
+ int div;
+ u32 p_div;
+ u32 val;
+
+ if (c->flags & PLL_FIXED)
+ return c->u.pll.fixed_rate;
+
+ if (c->flags & PLLM)
+ return __clk_get_rate(hw->clk);
+
+ p_div = 0;
+ /* Check if the target rate is tabulated */
+ for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+ if (sel->input_rate == input_rate && sel->output_rate == rate) {
+ if (c->flags & PLLU) {
+ BUG_ON(sel->p < 1 || sel->p > 2);
+ if (sel->p == 1)
+ p_div = PLLU_BASE_POST_DIV;
+ } else {
+ BUG_ON(sel->p < 1);
+ for (val = sel->p; val > 1; val >>= 1)
+ p_div++;
+ p_div <<= PLL_BASE_DIVP_SHIFT;
+ }
+ break;
+ }
+ }
+
+ if (sel->input_rate == 0) {
+ unsigned long cfreq;
+ BUG_ON(c->flags & PLLU);
+ sel = &cfg;
+
+ switch (input_rate) {
+ case 12000000:
+ case 26000000:
+ cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2000000;
+ break;
+ case 13000000:
+ cfreq = (rate <= 1000000 * 1000) ? 1000000 : 2600000;
+ break;
+ case 16800000:
+ case 19200000:
+ cfreq = (rate <= 1200000 * 1000) ? 1200000 : 2400000;
+ break;
+ default:
+ pr_err("%s: Unexpected reference rate %lu\n",
+ __func__, input_rate);
+ BUG();
+ }
+
+ /* Raise VCO to guarantee 0.5% accuracy */
+ for (cfg.output_rate = rate; cfg.output_rate < 200 * cfreq;
+ cfg.output_rate <<= 1)
+ p_div++;
+
+ cfg.p = 0x1 << p_div;
+ cfg.m = input_rate / cfreq;
+ cfg.n = cfg.output_rate / cfreq;
+ }
+
+ mul = sel->n;
+ div = sel->m * sel->p;
+
+ output_rate *= mul;
+ output_rate += div - 1; /* round up */
+ do_div(output_rate, div);
+
+ return output_rate;
+}
+
+static unsigned long tegra30_pll_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = parent_rate;
+ u32 val = clk_readl(c->reg + PLL_BASE);
+
+ if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) {
+ const struct clk_pll_freq_table *sel;
+ for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
+ if (sel->input_rate == parent_rate &&
+ sel->output_rate == c->u.pll.fixed_rate) {
+ c->mul = sel->n;
+ c->div = sel->m * sel->p;
+ break;
+ }
+ }
+ pr_err("Clock %s has unknown fixed frequency\n",
+ __clk_get_name(hw->clk));
+ BUG();
+ } else if (val & PLL_BASE_BYPASS) {
+ c->mul = 1;
+ c->div = 1;
+ } else {
+ c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT;
+ c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT;
+ if (c->flags & PLLU)
+ c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2;
+ else
+ c->div *= (0x1 << ((val & PLL_BASE_DIVP_MASK) >>
+ PLL_BASE_DIVP_SHIFT));
+ }
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+
+ return rate;
+}
+
+struct clk_ops tegra30_pll_ops = {
+ .is_enabled = tegra30_pll_clk_is_enabled,
+ .init = tegra30_pll_clk_init,
+ .enable = tegra30_pll_clk_enable,
+ .disable = tegra30_pll_clk_disable,
+ .recalc_rate = tegra30_pll_recalc_rate,
+ .round_rate = tegra30_pll_round_rate,
+ .set_rate = tegra30_pll_clk_set_rate,
};
-static int
-tegra30_plld_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val, mask, reg;
switch (p) {
@@ -1141,41 +1361,27 @@
return 0;
}
-static struct clk_ops tegra_plld_ops = {
- .init = tegra30_pll_clk_init,
- .enable = tegra30_pll_clk_enable,
- .disable = tegra30_pll_clk_disable,
- .set_rate = tegra30_pll_clk_set_rate,
- .clk_cfg_ex = tegra30_plld_clk_cfg_ex,
-};
-
-static void tegra30_plle_clk_init(struct clk *c)
+static int tegra30_plle_clk_is_enabled(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
- val = clk_readl(PLLE_AUX);
- c->parent = (val & PLLE_AUX_PLLP_SEL) ?
- tegra_get_clock_by_name("pll_p") :
- tegra_get_clock_by_name("pll_ref");
-
val = clk_readl(c->reg + PLL_BASE);
c->state = (val & PLLE_BASE_ENABLE) ? ON : OFF;
- c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
- c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
- c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+ return c->state;
}
-static void tegra30_plle_clk_disable(struct clk *c)
+static void tegra30_plle_clk_disable(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
- pr_debug("%s on clock %s\n", __func__, c->name);
val = clk_readl(c->reg + PLL_BASE);
val &= ~(PLLE_BASE_CML_ENABLE | PLLE_BASE_ENABLE);
clk_writel(val, c->reg + PLL_BASE);
}
-static void tegra30_plle_training(struct clk *c)
+static void tegra30_plle_training(struct clk_tegra *c)
{
u32 val;
@@ -1198,12 +1404,15 @@
} while (!(val & PLLE_MISC_READY));
}
-static int tegra30_plle_configure(struct clk *c, bool force_training)
+static int tegra30_plle_configure(struct clk_hw *hw, bool force_training)
{
- u32 val;
+ struct clk_tegra *c = to_clk_tegra(hw);
+ struct clk *parent = __clk_get_parent(hw->clk);
const struct clk_pll_freq_table *sel;
+ u32 val;
+
unsigned long rate = c->u.pll.fixed_rate;
- unsigned long input_rate = clk_get_rate(c->parent);
+ unsigned long input_rate = __clk_get_rate(parent);
for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) {
if (sel->input_rate == input_rate && sel->output_rate == rate)
@@ -1214,7 +1423,7 @@
return -ENOSYS;
/* disable PLLE, clear setup fiels */
- tegra30_plle_clk_disable(c);
+ tegra30_plle_clk_disable(hw);
val = clk_readl(c->reg + PLL_MISC(c));
val &= ~(PLLE_MISC_LOCK_ENABLE | PLLE_MISC_SETUP_MASK);
@@ -1252,52 +1461,64 @@
return 0;
}
-static int tegra30_plle_clk_enable(struct clk *c)
+static int tegra30_plle_clk_enable(struct clk_hw *hw)
{
- pr_debug("%s on clock %s\n", __func__, c->name);
- return tegra30_plle_configure(c, !c->set);
+ struct clk_tegra *c = to_clk_tegra(hw);
+
+ return tegra30_plle_configure(hw, !c->set);
}
-static struct clk_ops tegra_plle_ops = {
- .init = tegra30_plle_clk_init,
- .enable = tegra30_plle_clk_enable,
- .disable = tegra30_plle_clk_disable,
+static unsigned long tegra30_plle_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long rate = parent_rate;
+ u32 val;
+
+ val = clk_readl(c->reg + PLL_BASE);
+ c->mul = (val & PLLE_BASE_DIVN_MASK) >> PLLE_BASE_DIVN_SHIFT;
+ c->div = (val & PLLE_BASE_DIVM_MASK) >> PLLE_BASE_DIVM_SHIFT;
+ c->div *= (val & PLLE_BASE_DIVP_MASK) >> PLLE_BASE_DIVP_SHIFT;
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+ return rate;
+}
+
+struct clk_ops tegra30_plle_ops = {
+ .is_enabled = tegra30_plle_clk_is_enabled,
+ .enable = tegra30_plle_clk_enable,
+ .disable = tegra30_plle_clk_disable,
+ .recalc_rate = tegra30_plle_clk_recalc_rate,
};
/* Clock divider ops */
-static void tegra30_pll_div_clk_init(struct clk *c)
+static int tegra30_pll_div_clk_is_enabled(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
if (c->flags & DIV_U71) {
- u32 divu71;
u32 val = clk_readl(c->reg);
val >>= c->reg_shift;
c->state = (val & PLL_OUT_CLKEN) ? ON : OFF;
if (!(val & PLL_OUT_RESET_DISABLE))
c->state = OFF;
-
- divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
- c->div = (divu71 + 2);
- c->mul = 2;
- } else if (c->flags & DIV_2) {
- c->state = ON;
- if (c->flags & (PLLD | PLLX)) {
- c->div = 2;
- c->mul = 1;
- } else
- BUG();
} else {
c->state = ON;
- c->div = 1;
- c->mul = 1;
}
+ return c->state;
}
-static int tegra30_pll_div_clk_enable(struct clk *c)
+static int tegra30_pll_div_clk_enable(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
u32 new_val;
- pr_debug("%s: %s\n", __func__, c->name);
+ pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
if (c->flags & DIV_U71) {
val = clk_readl(c->reg);
new_val = val >> c->reg_shift;
@@ -1315,12 +1536,13 @@
return -EINVAL;
}
-static void tegra30_pll_div_clk_disable(struct clk *c)
+static void tegra30_pll_div_clk_disable(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
u32 new_val;
- pr_debug("%s: %s\n", __func__, c->name);
+ pr_debug("%s: %s\n", __func__, __clk_get_name(hw->clk));
if (c->flags & DIV_U71) {
val = clk_readl(c->reg);
new_val = val >> c->reg_shift;
@@ -1334,14 +1556,14 @@
}
}
-static int tegra30_pll_div_clk_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_pll_div_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
u32 new_val;
int divider_u71;
- unsigned long parent_rate = clk_get_rate(c->parent);
- pr_debug("%s: %s %lu\n", __func__, c->name, rate);
if (c->flags & DIV_U71) {
divider_u71 = clk_div71_get_divider(
parent_rate, rate, c->flags, ROUND_DIVIDER_UP);
@@ -1359,19 +1581,59 @@
clk_writel_delay(val, c->reg);
c->div = divider_u71 + 2;
c->mul = 2;
+ c->fixed_rate = rate;
return 0;
}
- } else if (c->flags & DIV_2)
- return clk_set_rate(c->parent, rate * 2);
+ } else if (c->flags & DIV_2) {
+ c->fixed_rate = rate;
+ return 0;
+ }
return -EINVAL;
}
-static long tegra30_pll_div_clk_round_rate(struct clk *c, unsigned long rate)
+static unsigned long tegra30_pll_div_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = parent_rate;
+
+ if (c->flags & DIV_U71) {
+ u32 divu71;
+ u32 val = clk_readl(c->reg);
+ val >>= c->reg_shift;
+
+ divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT;
+ c->div = (divu71 + 2);
+ c->mul = 2;
+ } else if (c->flags & DIV_2) {
+ if (c->flags & (PLLD | PLLX)) {
+ c->div = 2;
+ c->mul = 1;
+ } else
+ BUG();
+ } else {
+ c->div = 1;
+ c->mul = 1;
+ }
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+
+ return rate;
+}
+
+static long tegra30_pll_div_clk_round_rate(struct clk_hw *hw,
+ unsigned long rate, unsigned long *prate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
int divider;
- unsigned long parent_rate = clk_get_rate(c->parent);
- pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+ if (prate)
+ parent_rate = *prate;
if (c->flags & DIV_U71) {
divider = clk_div71_get_divider(
@@ -1379,23 +1641,25 @@
if (divider < 0)
return divider;
return DIV_ROUND_UP(parent_rate * 2, divider + 2);
- } else if (c->flags & DIV_2)
- /* no rounding - fixed DIV_2 dividers pass rate to parent PLL */
+ } else if (c->flags & DIV_2) {
+ *prate = rate * 2;
return rate;
+ }
return -EINVAL;
}
-static struct clk_ops tegra_pll_div_ops = {
- .init = tegra30_pll_div_clk_init,
- .enable = tegra30_pll_div_clk_enable,
- .disable = tegra30_pll_div_clk_disable,
- .set_rate = tegra30_pll_div_clk_set_rate,
- .round_rate = tegra30_pll_div_clk_round_rate,
+struct clk_ops tegra30_pll_div_ops = {
+ .is_enabled = tegra30_pll_div_clk_is_enabled,
+ .enable = tegra30_pll_div_clk_enable,
+ .disable = tegra30_pll_div_clk_disable,
+ .set_rate = tegra30_pll_div_clk_set_rate,
+ .recalc_rate = tegra30_pll_div_clk_recalc_rate,
+ .round_rate = tegra30_pll_div_clk_round_rate,
};
/* Periph clk ops */
-static inline u32 periph_clk_source_mask(struct clk *c)
+static inline u32 periph_clk_source_mask(struct clk_tegra *c)
{
if (c->flags & MUX8)
return 7 << 29;
@@ -1409,7 +1673,7 @@
return 3 << 30;
}
-static inline u32 periph_clk_source_shift(struct clk *c)
+static inline u32 periph_clk_source_shift(struct clk_tegra *c)
{
if (c->flags & MUX8)
return 29;
@@ -1423,47 +1687,9 @@
return 30;
}
-static void tegra30_periph_clk_init(struct clk *c)
+static int tegra30_periph_clk_is_enabled(struct clk_hw *hw)
{
- u32 val = clk_readl(c->reg);
- const struct clk_mux_sel *mux = 0;
- const struct clk_mux_sel *sel;
- if (c->flags & MUX) {
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (((val & periph_clk_source_mask(c)) >>
- periph_clk_source_shift(c)) == sel->value)
- mux = sel;
- }
- BUG_ON(!mux);
-
- c->parent = mux->input;
- } else {
- c->parent = c->inputs[0].input;
- }
-
- if (c->flags & DIV_U71) {
- u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
- if ((c->flags & DIV_U71_UART) &&
- (!(val & PERIPH_CLK_UART_DIV_ENB))) {
- divu71 = 0;
- }
- if (c->flags & DIV_U71_IDLE) {
- val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
- PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
- val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
- PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
- clk_writel(val, c->reg);
- }
- c->div = divu71 + 2;
- c->mul = 2;
- } else if (c->flags & DIV_U16) {
- u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
- c->div = divu16 + 1;
- c->mul = 1;
- } else {
- c->div = 1;
- c->mul = 1;
- }
+ struct clk_tegra *c = to_clk_tegra(hw);
c->state = ON;
if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
@@ -1471,11 +1697,12 @@
if (!(c->flags & PERIPH_NO_RESET))
if (clk_readl(PERIPH_CLK_TO_RST_REG(c)) & PERIPH_CLK_TO_BIT(c))
c->state = OFF;
+ return c->state;
}
-static int tegra30_periph_clk_enable(struct clk *c)
+static int tegra30_periph_clk_enable(struct clk_hw *hw)
{
- pr_debug("%s on clock %s\n", __func__, c->name);
+ struct clk_tegra *c = to_clk_tegra(hw);
tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++;
if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 1)
@@ -1494,31 +1721,29 @@
return 0;
}
-static void tegra30_periph_clk_disable(struct clk *c)
+static void tegra30_periph_clk_disable(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
unsigned long val;
- pr_debug("%s on clock %s\n", __func__, c->name);
- if (c->refcnt)
- tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
+ tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--;
- if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) {
- /* If peripheral is in the APB bus then read the APB bus to
- * flush the write operation in apb bus. This will avoid the
- * peripheral access after disabling clock*/
- if (c->flags & PERIPH_ON_APB)
- val = chipid_readl();
+ if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] > 0)
+ return;
- clk_writel_delay(
- PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
- }
+ /* If peripheral is in the APB bus then read the APB bus to
+ * flush the write operation in apb bus. This will avoid the
+ * peripheral access after disabling clock*/
+ if (c->flags & PERIPH_ON_APB)
+ val = chipid_readl();
+
+ clk_writel_delay(PERIPH_CLK_TO_BIT(c), PERIPH_CLK_TO_ENB_CLR_REG(c));
}
-static void tegra30_periph_clk_reset(struct clk *c, bool assert)
+void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
unsigned long val;
- pr_debug("%s %s on clock %s\n", __func__,
- assert ? "assert" : "deassert", c->name);
if (!(c->flags & PERIPH_NO_RESET)) {
if (assert) {
@@ -1537,42 +1762,40 @@
}
}
-static int tegra30_periph_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_periph_clk_set_parent(struct clk_hw *hw, u8 index)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
- const struct clk_mux_sel *sel;
- pr_debug("%s: %s %s\n", __func__, c->name, p->name);
if (!(c->flags & MUX))
- return (p == c->parent) ? 0 : (-EINVAL);
+ return (index == 0) ? 0 : (-EINVAL);
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (sel->input == p) {
- val = clk_readl(c->reg);
- val &= ~periph_clk_source_mask(c);
- val |= (sel->value << periph_clk_source_shift(c));
-
- if (c->refcnt)
- clk_enable(p);
-
- clk_writel_delay(val, c->reg);
-
- if (c->refcnt && c->parent)
- clk_disable(c->parent);
-
- clk_reparent(c, p);
- return 0;
- }
- }
-
- return -EINVAL;
+ val = clk_readl(c->reg);
+ val &= ~periph_clk_source_mask(c);
+ val |= (index << periph_clk_source_shift(c));
+ clk_writel_delay(val, c->reg);
+ return 0;
}
-static int tegra30_periph_clk_set_rate(struct clk *c, unsigned long rate)
+static u8 tegra30_periph_clk_get_parent(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg);
+ int source = (val & periph_clk_source_mask(c)) >>
+ periph_clk_source_shift(c);
+
+ if (!(c->flags & MUX))
+ return 0;
+
+ return source;
+}
+
+static int tegra30_periph_clk_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
int divider;
- unsigned long parent_rate = clk_get_rate(c->parent);
if (c->flags & DIV_U71) {
divider = clk_div71_get_divider(
@@ -1611,12 +1834,15 @@
return -EINVAL;
}
-static long tegra30_periph_clk_round_rate(struct clk *c,
- unsigned long rate)
+static long tegra30_periph_clk_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ unsigned long parent_rate = __clk_get_rate(__clk_get_parent(hw->clk));
int divider;
- unsigned long parent_rate = clk_get_rate(c->parent);
- pr_debug("%s: %s %lu\n", __func__, c->name, rate);
+
+ if (prate)
+ parent_rate = *prate;
if (c->flags & DIV_U71) {
divider = clk_div71_get_divider(
@@ -1634,21 +1860,85 @@
return -EINVAL;
}
-static struct clk_ops tegra_periph_clk_ops = {
- .init = &tegra30_periph_clk_init,
- .enable = &tegra30_periph_clk_enable,
- .disable = &tegra30_periph_clk_disable,
- .set_parent = &tegra30_periph_clk_set_parent,
- .set_rate = &tegra30_periph_clk_set_rate,
- .round_rate = &tegra30_periph_clk_round_rate,
- .reset = &tegra30_periph_clk_reset,
+static unsigned long tegra30_periph_clk_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = parent_rate;
+ u32 val = clk_readl(c->reg);
+
+ if (c->flags & DIV_U71) {
+ u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK;
+ if ((c->flags & DIV_U71_UART) &&
+ (!(val & PERIPH_CLK_UART_DIV_ENB))) {
+ divu71 = 0;
+ }
+ if (c->flags & DIV_U71_IDLE) {
+ val &= ~(PERIPH_CLK_SOURCE_DIVU71_MASK <<
+ PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+ val |= (PERIPH_CLK_SOURCE_DIVIDLE_VAL <<
+ PERIPH_CLK_SOURCE_DIVIDLE_SHIFT);
+ clk_writel(val, c->reg);
+ }
+ c->div = divu71 + 2;
+ c->mul = 2;
+ } else if (c->flags & DIV_U16) {
+ u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK;
+ c->div = divu16 + 1;
+ c->mul = 1;
+ } else {
+ c->div = 1;
+ c->mul = 1;
+ }
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+ return rate;
+}
+
+struct clk_ops tegra30_periph_clk_ops = {
+ .is_enabled = tegra30_periph_clk_is_enabled,
+ .enable = tegra30_periph_clk_enable,
+ .disable = tegra30_periph_clk_disable,
+ .set_parent = tegra30_periph_clk_set_parent,
+ .get_parent = tegra30_periph_clk_get_parent,
+ .set_rate = tegra30_periph_clk_set_rate,
+ .round_rate = tegra30_periph_clk_round_rate,
+ .recalc_rate = tegra30_periph_clk_recalc_rate,
};
+static int tegra30_dsib_clk_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct clk *d = clk_get_sys(NULL, "pll_d");
+ /* The DSIB parent selection bit is in PLLD base
+ register - can not do direct r-m-w, must be
+ protected by PLLD lock */
+ tegra_clk_cfg_ex(
+ d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, index);
+
+ return 0;
+}
+
+struct clk_ops tegra30_dsib_clk_ops = {
+ .is_enabled = tegra30_periph_clk_is_enabled,
+ .enable = &tegra30_periph_clk_enable,
+ .disable = &tegra30_periph_clk_disable,
+ .set_parent = &tegra30_dsib_clk_set_parent,
+ .get_parent = &tegra30_periph_clk_get_parent,
+ .set_rate = &tegra30_periph_clk_set_rate,
+ .round_rate = &tegra30_periph_clk_round_rate,
+ .recalc_rate = &tegra30_periph_clk_recalc_rate,
+};
/* Periph extended clock configuration ops */
-static int
-tegra30_vi_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
if (p == TEGRA_CLK_VI_INP_SEL) {
u32 val = clk_readl(c->reg);
val &= ~PERIPH_CLK_VI_SEL_EX_MASK;
@@ -1660,20 +1950,11 @@
return -EINVAL;
}
-static struct clk_ops tegra_vi_clk_ops = {
- .init = &tegra30_periph_clk_init,
- .enable = &tegra30_periph_clk_enable,
- .disable = &tegra30_periph_clk_disable,
- .set_parent = &tegra30_periph_clk_set_parent,
- .set_rate = &tegra30_periph_clk_set_rate,
- .round_rate = &tegra30_periph_clk_round_rate,
- .clk_cfg_ex = &tegra30_vi_clk_cfg_ex,
- .reset = &tegra30_periph_clk_reset,
-};
-
-static int
-tegra30_nand_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
if (p == TEGRA_CLK_NAND_PAD_DIV2_ENB) {
u32 val = clk_readl(c->reg);
if (setting)
@@ -1686,21 +1967,11 @@
return -EINVAL;
}
-static struct clk_ops tegra_nand_clk_ops = {
- .init = &tegra30_periph_clk_init,
- .enable = &tegra30_periph_clk_enable,
- .disable = &tegra30_periph_clk_disable,
- .set_parent = &tegra30_periph_clk_set_parent,
- .set_rate = &tegra30_periph_clk_set_rate,
- .round_rate = &tegra30_periph_clk_round_rate,
- .clk_cfg_ex = &tegra30_nand_clk_cfg_ex,
- .reset = &tegra30_periph_clk_reset,
-};
-
-
-static int
-tegra30_dtv_clk_cfg_ex(struct clk *c, enum tegra_clk_ex_param p, u32 setting)
+int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
if (p == TEGRA_CLK_DTV_INVERT) {
u32 val = clk_readl(c->reg);
if (setting)
@@ -1713,91 +1984,27 @@
return -EINVAL;
}
-static struct clk_ops tegra_dtv_clk_ops = {
- .init = &tegra30_periph_clk_init,
- .enable = &tegra30_periph_clk_enable,
- .disable = &tegra30_periph_clk_disable,
- .set_parent = &tegra30_periph_clk_set_parent,
- .set_rate = &tegra30_periph_clk_set_rate,
- .round_rate = &tegra30_periph_clk_round_rate,
- .clk_cfg_ex = &tegra30_dtv_clk_cfg_ex,
- .reset = &tegra30_periph_clk_reset,
-};
-
-static int tegra30_dsib_clk_set_parent(struct clk *c, struct clk *p)
-{
- const struct clk_mux_sel *sel;
- struct clk *d = tegra_get_clock_by_name("pll_d");
-
- pr_debug("%s: %s %s\n", __func__, c->name, p->name);
-
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (sel->input == p) {
- if (c->refcnt)
- clk_enable(p);
-
- /* The DSIB parent selection bit is in PLLD base
- register - can not do direct r-m-w, must be
- protected by PLLD lock */
- tegra_clk_cfg_ex(
- d, TEGRA_CLK_PLLD_MIPI_MUX_SEL, sel->value);
-
- if (c->refcnt && c->parent)
- clk_disable(c->parent);
-
- clk_reparent(c, p);
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
-static struct clk_ops tegra_dsib_clk_ops = {
- .init = &tegra30_periph_clk_init,
- .enable = &tegra30_periph_clk_enable,
- .disable = &tegra30_periph_clk_disable,
- .set_parent = &tegra30_dsib_clk_set_parent,
- .set_rate = &tegra30_periph_clk_set_rate,
- .round_rate = &tegra30_periph_clk_round_rate,
- .reset = &tegra30_periph_clk_reset,
-};
-
-/* pciex clock support only reset function */
-static struct clk_ops tegra_pciex_clk_ops = {
- .reset = tegra30_periph_clk_reset,
-};
-
/* Output clock ops */
static DEFINE_SPINLOCK(clk_out_lock);
-static void tegra30_clk_out_init(struct clk *c)
+static int tegra30_clk_out_is_enabled(struct clk_hw *hw)
{
- const struct clk_mux_sel *mux = 0;
- const struct clk_mux_sel *sel;
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val = pmc_readl(c->reg);
c->state = (val & (0x1 << c->u.periph.clk_num)) ? ON : OFF;
c->mul = 1;
c->div = 1;
-
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (((val & periph_clk_source_mask(c)) >>
- periph_clk_source_shift(c)) == sel->value)
- mux = sel;
- }
- BUG_ON(!mux);
- c->parent = mux->input;
+ return c->state;
}
-static int tegra30_clk_out_enable(struct clk *c)
+static int tegra30_clk_out_enable(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
unsigned long flags;
- pr_debug("%s on clock %s\n", __func__, c->name);
-
spin_lock_irqsave(&clk_out_lock, flags);
val = pmc_readl(c->reg);
val |= (0x1 << c->u.periph.clk_num);
@@ -1807,13 +2014,12 @@
return 0;
}
-static void tegra30_clk_out_disable(struct clk *c)
+static void tegra30_clk_out_disable(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
unsigned long flags;
- pr_debug("%s on clock %s\n", __func__, c->name);
-
spin_lock_irqsave(&clk_out_lock, flags);
val = pmc_readl(c->reg);
val &= ~(0x1 << c->u.periph.clk_num);
@@ -1821,59 +2027,59 @@
spin_unlock_irqrestore(&clk_out_lock, flags);
}
-static int tegra30_clk_out_set_parent(struct clk *c, struct clk *p)
+static int tegra30_clk_out_set_parent(struct clk_hw *hw, u8 index)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
unsigned long flags;
- const struct clk_mux_sel *sel;
- pr_debug("%s: %s %s\n", __func__, c->name, p->name);
+ spin_lock_irqsave(&clk_out_lock, flags);
+ val = pmc_readl(c->reg);
+ val &= ~periph_clk_source_mask(c);
+ val |= (index << periph_clk_source_shift(c));
+ pmc_writel(val, c->reg);
+ spin_unlock_irqrestore(&clk_out_lock, flags);
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (sel->input == p) {
- if (c->refcnt)
- clk_enable(p);
-
- spin_lock_irqsave(&clk_out_lock, flags);
- val = pmc_readl(c->reg);
- val &= ~periph_clk_source_mask(c);
- val |= (sel->value << periph_clk_source_shift(c));
- pmc_writel(val, c->reg);
- spin_unlock_irqrestore(&clk_out_lock, flags);
-
- if (c->refcnt && c->parent)
- clk_disable(c->parent);
-
- clk_reparent(c, p);
- return 0;
- }
- }
- return -EINVAL;
+ return 0;
}
-static struct clk_ops tegra_clk_out_ops = {
- .init = &tegra30_clk_out_init,
- .enable = &tegra30_clk_out_enable,
- .disable = &tegra30_clk_out_disable,
- .set_parent = &tegra30_clk_out_set_parent,
+static u8 tegra30_clk_out_get_parent(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = pmc_readl(c->reg);
+ int source;
+
+ source = (val & periph_clk_source_mask(c)) >>
+ periph_clk_source_shift(c);
+ return source;
+}
+
+struct clk_ops tegra_clk_out_ops = {
+ .is_enabled = tegra30_clk_out_is_enabled,
+ .enable = tegra30_clk_out_enable,
+ .disable = tegra30_clk_out_disable,
+ .set_parent = tegra30_clk_out_set_parent,
+ .get_parent = tegra30_clk_out_get_parent,
+ .recalc_rate = tegra30_clk_fixed_recalc_rate,
};
-
/* Clock doubler ops */
-static void tegra30_clk_double_init(struct clk *c)
+static int tegra30_clk_double_is_enabled(struct clk_hw *hw)
{
- u32 val = clk_readl(c->reg);
- c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
- c->div = 1;
+ struct clk_tegra *c = to_clk_tegra(hw);
+
c->state = ON;
if (!(clk_readl(PERIPH_CLK_TO_ENB_REG(c)) & PERIPH_CLK_TO_BIT(c)))
c->state = OFF;
+ return c->state;
};
-static int tegra30_clk_double_set_rate(struct clk *c, unsigned long rate)
+static int tegra30_clk_double_set_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long parent_rate)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
- unsigned long parent_rate = clk_get_rate(c->parent);
+
if (rate == parent_rate) {
val = clk_readl(c->reg) | (0x1 << c->reg_shift);
clk_writel(val, c->reg);
@@ -1890,1215 +2096,200 @@
return -EINVAL;
}
-static struct clk_ops tegra_clk_double_ops = {
- .init = &tegra30_clk_double_init,
- .enable = &tegra30_periph_clk_enable,
- .disable = &tegra30_periph_clk_disable,
- .set_rate = &tegra30_clk_double_set_rate,
+static unsigned long tegra30_clk_double_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u64 rate = parent_rate;
+
+ u32 val = clk_readl(c->reg);
+ c->mul = val & (0x1 << c->reg_shift) ? 1 : 2;
+ c->div = 1;
+
+ if (c->mul != 0 && c->div != 0) {
+ rate *= c->mul;
+ rate += c->div - 1; /* round up */
+ do_div(rate, c->div);
+ }
+
+ return rate;
+}
+
+static long tegra30_clk_double_round_rate(struct clk_hw *hw, unsigned long rate,
+ unsigned long *prate)
+{
+ unsigned long output_rate = *prate;
+
+ do_div(output_rate, 2);
+ return output_rate;
+}
+
+struct clk_ops tegra30_clk_double_ops = {
+ .is_enabled = tegra30_clk_double_is_enabled,
+ .enable = tegra30_periph_clk_enable,
+ .disable = tegra30_periph_clk_disable,
+ .recalc_rate = tegra30_clk_double_recalc_rate,
+ .round_rate = tegra30_clk_double_round_rate,
+ .set_rate = tegra30_clk_double_set_rate,
};
/* Audio sync clock ops */
-static int tegra30_sync_source_set_rate(struct clk *c, unsigned long rate)
-{
- c->rate = rate;
- return 0;
-}
-
-static struct clk_ops tegra_sync_source_ops = {
- .set_rate = &tegra30_sync_source_set_rate,
+struct clk_ops tegra_sync_source_ops = {
+ .recalc_rate = tegra30_clk_fixed_recalc_rate,
};
-static void tegra30_audio_sync_clk_init(struct clk *c)
+static int tegra30_audio_sync_clk_is_enabled(struct clk_hw *hw)
{
- int source;
- const struct clk_mux_sel *sel;
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val = clk_readl(c->reg);
c->state = (val & AUDIO_SYNC_DISABLE_BIT) ? OFF : ON;
- source = val & AUDIO_SYNC_SOURCE_MASK;
- for (sel = c->inputs; sel->input != NULL; sel++)
- if (sel->value == source)
- break;
- BUG_ON(sel->input == NULL);
- c->parent = sel->input;
+ return c->state;
}
-static int tegra30_audio_sync_clk_enable(struct clk *c)
+static int tegra30_audio_sync_clk_enable(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val = clk_readl(c->reg);
clk_writel((val & (~AUDIO_SYNC_DISABLE_BIT)), c->reg);
return 0;
}
-static void tegra30_audio_sync_clk_disable(struct clk *c)
+static void tegra30_audio_sync_clk_disable(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val = clk_readl(c->reg);
clk_writel((val | AUDIO_SYNC_DISABLE_BIT), c->reg);
}
-static int tegra30_audio_sync_clk_set_parent(struct clk *c, struct clk *p)
+static int tegra30_audio_sync_clk_set_parent(struct clk_hw *hw, u8 index)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
u32 val;
- const struct clk_mux_sel *sel;
- for (sel = c->inputs; sel->input != NULL; sel++) {
- if (sel->input == p) {
- val = clk_readl(c->reg);
- val &= ~AUDIO_SYNC_SOURCE_MASK;
- val |= sel->value;
- if (c->refcnt)
- clk_enable(p);
+ val = clk_readl(c->reg);
+ val &= ~AUDIO_SYNC_SOURCE_MASK;
+ val |= index;
- clk_writel(val, c->reg);
-
- if (c->refcnt && c->parent)
- clk_disable(c->parent);
-
- clk_reparent(c, p);
- return 0;
- }
- }
-
- return -EINVAL;
-}
-
-static struct clk_ops tegra_audio_sync_clk_ops = {
- .init = tegra30_audio_sync_clk_init,
- .enable = tegra30_audio_sync_clk_enable,
- .disable = tegra30_audio_sync_clk_disable,
- .set_parent = tegra30_audio_sync_clk_set_parent,
-};
-
-/* cml0 (pcie), and cml1 (sata) clock ops */
-static void tegra30_cml_clk_init(struct clk *c)
-{
- u32 val = clk_readl(c->reg);
- c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
-}
-
-static int tegra30_cml_clk_enable(struct clk *c)
-{
- u32 val = clk_readl(c->reg);
- val |= (0x1 << c->u.periph.clk_num);
clk_writel(val, c->reg);
return 0;
}
-static void tegra30_cml_clk_disable(struct clk *c)
+static u8 tegra30_audio_sync_clk_get_parent(struct clk_hw *hw)
{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg);
+ int source;
+
+ source = val & AUDIO_SYNC_SOURCE_MASK;
+ return source;
+}
+
+struct clk_ops tegra30_audio_sync_clk_ops = {
+ .is_enabled = tegra30_audio_sync_clk_is_enabled,
+ .enable = tegra30_audio_sync_clk_enable,
+ .disable = tegra30_audio_sync_clk_disable,
+ .set_parent = tegra30_audio_sync_clk_set_parent,
+ .get_parent = tegra30_audio_sync_clk_get_parent,
+ .recalc_rate = tegra30_clk_fixed_recalc_rate,
+};
+
+/* cml0 (pcie), and cml1 (sata) clock ops */
+static int tegra30_cml_clk_is_enabled(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+ u32 val = clk_readl(c->reg);
+ c->state = val & (0x1 << c->u.periph.clk_num) ? ON : OFF;
+ return c->state;
+}
+
+static int tegra30_cml_clk_enable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
+ u32 val = clk_readl(c->reg);
+ val |= (0x1 << c->u.periph.clk_num);
+ clk_writel(val, c->reg);
+
+ return 0;
+}
+
+static void tegra30_cml_clk_disable(struct clk_hw *hw)
+{
+ struct clk_tegra *c = to_clk_tegra(hw);
+
u32 val = clk_readl(c->reg);
val &= ~(0x1 << c->u.periph.clk_num);
clk_writel(val, c->reg);
}
-static struct clk_ops tegra_cml_clk_ops = {
- .init = &tegra30_cml_clk_init,
- .enable = &tegra30_cml_clk_enable,
- .disable = &tegra30_cml_clk_disable,
+struct clk_ops tegra_cml_clk_ops = {
+ .is_enabled = tegra30_cml_clk_is_enabled,
+ .enable = tegra30_cml_clk_enable,
+ .disable = tegra30_cml_clk_disable,
+ .recalc_rate = tegra30_clk_fixed_recalc_rate,
};
-/* Clock definitions */
-static struct clk tegra_clk_32k = {
- .name = "clk_32k",
- .rate = 32768,
- .ops = NULL,
- .max_rate = 32768,
+struct clk_ops tegra_pciex_clk_ops = {
+ .recalc_rate = tegra30_clk_fixed_recalc_rate,
};
-static struct clk tegra_clk_m = {
- .name = "clk_m",
- .flags = ENABLE_ON_INIT,
- .ops = &tegra_clk_m_ops,
- .reg = 0x1fc,
- .reg_shift = 28,
- .max_rate = 48000000,
-};
-
-static struct clk tegra_clk_m_div2 = {
- .name = "clk_m_div2",
- .ops = &tegra_clk_m_div_ops,
- .parent = &tegra_clk_m,
- .mul = 1,
- .div = 2,
- .state = ON,
- .max_rate = 24000000,
-};
-
-static struct clk tegra_clk_m_div4 = {
- .name = "clk_m_div4",
- .ops = &tegra_clk_m_div_ops,
- .parent = &tegra_clk_m,
- .mul = 1,
- .div = 4,
- .state = ON,
- .max_rate = 12000000,
-};
-
-static struct clk tegra_pll_ref = {
- .name = "pll_ref",
- .flags = ENABLE_ON_INIT,
- .ops = &tegra_pll_ref_ops,
- .parent = &tegra_clk_m,
- .max_rate = 26000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
- { 12000000, 1040000000, 520, 6, 1, 8},
- { 13000000, 1040000000, 480, 6, 1, 8},
- { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
- { 19200000, 1040000000, 325, 6, 1, 6},
- { 26000000, 1040000000, 520, 13, 1, 8},
-
- { 12000000, 832000000, 416, 6, 1, 8},
- { 13000000, 832000000, 832, 13, 1, 8},
- { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
- { 19200000, 832000000, 260, 6, 1, 8},
- { 26000000, 832000000, 416, 13, 1, 8},
-
- { 12000000, 624000000, 624, 12, 1, 8},
- { 13000000, 624000000, 624, 13, 1, 8},
- { 16800000, 600000000, 520, 14, 1, 8},
- { 19200000, 624000000, 520, 16, 1, 8},
- { 26000000, 624000000, 624, 26, 1, 8},
-
- { 12000000, 600000000, 600, 12, 1, 8},
- { 13000000, 600000000, 600, 13, 1, 8},
- { 16800000, 600000000, 500, 14, 1, 8},
- { 19200000, 600000000, 375, 12, 1, 6},
- { 26000000, 600000000, 600, 26, 1, 8},
-
- { 12000000, 520000000, 520, 12, 1, 8},
- { 13000000, 520000000, 520, 13, 1, 8},
- { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
- { 19200000, 520000000, 325, 12, 1, 6},
- { 26000000, 520000000, 520, 26, 1, 8},
-
- { 12000000, 416000000, 416, 12, 1, 8},
- { 13000000, 416000000, 416, 13, 1, 8},
- { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
- { 19200000, 416000000, 260, 12, 1, 6},
- { 26000000, 416000000, 416, 26, 1, 8},
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_c = {
- .name = "pll_c",
- .flags = PLL_HAS_CPCON,
- .ops = &tegra_pll_ops,
- .reg = 0x80,
- .parent = &tegra_pll_ref,
- .max_rate = 1400000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1400000000,
- .freq_table = tegra_pll_c_freq_table,
- .lock_delay = 300,
- },
-};
-
-static struct clk tegra_pll_c_out1 = {
- .name = "pll_c_out1",
- .ops = &tegra_pll_div_ops,
- .flags = DIV_U71,
- .parent = &tegra_pll_c,
- .reg = 0x84,
- .reg_shift = 0,
- .max_rate = 700000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
- { 12000000, 666000000, 666, 12, 1, 8},
- { 13000000, 666000000, 666, 13, 1, 8},
- { 16800000, 666000000, 555, 14, 1, 8},
- { 19200000, 666000000, 555, 16, 1, 8},
- { 26000000, 666000000, 666, 26, 1, 8},
- { 12000000, 600000000, 600, 12, 1, 8},
- { 13000000, 600000000, 600, 13, 1, 8},
- { 16800000, 600000000, 500, 14, 1, 8},
- { 19200000, 600000000, 375, 12, 1, 6},
- { 26000000, 600000000, 600, 26, 1, 8},
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_m = {
- .name = "pll_m",
- .flags = PLL_HAS_CPCON | PLLM,
- .ops = &tegra_pll_ops,
- .reg = 0x90,
- .parent = &tegra_pll_ref,
- .max_rate = 800000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1200000000,
- .freq_table = tegra_pll_m_freq_table,
- .lock_delay = 300,
- },
-};
-
-static struct clk tegra_pll_m_out1 = {
- .name = "pll_m_out1",
- .ops = &tegra_pll_div_ops,
- .flags = DIV_U71,
- .parent = &tegra_pll_m,
- .reg = 0x94,
- .reg_shift = 0,
- .max_rate = 600000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
- { 12000000, 216000000, 432, 12, 2, 8},
- { 13000000, 216000000, 432, 13, 2, 8},
- { 16800000, 216000000, 360, 14, 2, 8},
- { 19200000, 216000000, 360, 16, 2, 8},
- { 26000000, 216000000, 432, 26, 2, 8},
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_p = {
- .name = "pll_p",
- .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON,
- .ops = &tegra_pll_ops,
- .reg = 0xa0,
- .parent = &tegra_pll_ref,
- .max_rate = 432000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1400000000,
- .freq_table = tegra_pll_p_freq_table,
- .lock_delay = 300,
- .fixed_rate = 408000000,
- },
-};
-
-static struct clk tegra_pll_p_out1 = {
- .name = "pll_p_out1",
- .ops = &tegra_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa4,
- .reg_shift = 0,
- .max_rate = 432000000,
-};
-
-static struct clk tegra_pll_p_out2 = {
- .name = "pll_p_out2",
- .ops = &tegra_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa4,
- .reg_shift = 16,
- .max_rate = 432000000,
-};
-
-static struct clk tegra_pll_p_out3 = {
- .name = "pll_p_out3",
- .ops = &tegra_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa8,
- .reg_shift = 0,
- .max_rate = 432000000,
-};
-
-static struct clk tegra_pll_p_out4 = {
- .name = "pll_p_out4",
- .ops = &tegra_pll_div_ops,
- .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED,
- .parent = &tegra_pll_p,
- .reg = 0xa8,
- .reg_shift = 16,
- .max_rate = 432000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
- { 9600000, 564480000, 294, 5, 1, 4},
- { 9600000, 552960000, 288, 5, 1, 4},
- { 9600000, 24000000, 5, 2, 1, 1},
-
- { 28800000, 56448000, 49, 25, 1, 1},
- { 28800000, 73728000, 64, 25, 1, 1},
- { 28800000, 24000000, 5, 6, 1, 1},
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_a = {
- .name = "pll_a",
- .flags = PLL_HAS_CPCON,
- .ops = &tegra_pll_ops,
- .reg = 0xb0,
- .parent = &tegra_pll_p_out1,
- .max_rate = 700000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1400000000,
- .freq_table = tegra_pll_a_freq_table,
- .lock_delay = 300,
- },
-};
-
-static struct clk tegra_pll_a_out0 = {
- .name = "pll_a_out0",
- .ops = &tegra_pll_div_ops,
- .flags = DIV_U71,
- .parent = &tegra_pll_a,
- .reg = 0xb4,
- .reg_shift = 0,
- .max_rate = 100000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
- { 12000000, 216000000, 216, 12, 1, 4},
- { 13000000, 216000000, 216, 13, 1, 4},
- { 16800000, 216000000, 180, 14, 1, 4},
- { 19200000, 216000000, 180, 16, 1, 4},
- { 26000000, 216000000, 216, 26, 1, 4},
-
- { 12000000, 594000000, 594, 12, 1, 8},
- { 13000000, 594000000, 594, 13, 1, 8},
- { 16800000, 594000000, 495, 14, 1, 8},
- { 19200000, 594000000, 495, 16, 1, 8},
- { 26000000, 594000000, 594, 26, 1, 8},
-
- { 12000000, 1000000000, 1000, 12, 1, 12},
- { 13000000, 1000000000, 1000, 13, 1, 12},
- { 19200000, 1000000000, 625, 12, 1, 8},
- { 26000000, 1000000000, 1000, 26, 1, 12},
-
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_d = {
- .name = "pll_d",
- .flags = PLL_HAS_CPCON | PLLD,
- .ops = &tegra_plld_ops,
- .reg = 0xd0,
- .parent = &tegra_pll_ref,
- .max_rate = 1000000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 40000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 40000000,
- .vco_max = 1000000000,
- .freq_table = tegra_pll_d_freq_table,
- .lock_delay = 1000,
- },
-};
-
-static struct clk tegra_pll_d_out0 = {
- .name = "pll_d_out0",
- .ops = &tegra_pll_div_ops,
- .flags = DIV_2 | PLLD,
- .parent = &tegra_pll_d,
- .max_rate = 500000000,
-};
-
-static struct clk tegra_pll_d2 = {
- .name = "pll_d2",
- .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD,
- .ops = &tegra_plld_ops,
- .reg = 0x4b8,
- .parent = &tegra_pll_ref,
- .max_rate = 1000000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 40000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 40000000,
- .vco_max = 1000000000,
- .freq_table = tegra_pll_d_freq_table,
- .lock_delay = 1000,
- },
-};
-
-static struct clk tegra_pll_d2_out0 = {
- .name = "pll_d2_out0",
- .ops = &tegra_pll_div_ops,
- .flags = DIV_2 | PLLD,
- .parent = &tegra_pll_d2,
- .max_rate = 500000000,
-};
-
-static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
- { 12000000, 480000000, 960, 12, 2, 12},
- { 13000000, 480000000, 960, 13, 2, 12},
- { 16800000, 480000000, 400, 7, 2, 5},
- { 19200000, 480000000, 200, 4, 2, 3},
- { 26000000, 480000000, 960, 26, 2, 12},
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_u = {
- .name = "pll_u",
- .flags = PLL_HAS_CPCON | PLLU,
- .ops = &tegra_pll_ops,
- .reg = 0xc0,
- .parent = &tegra_pll_ref,
- .max_rate = 480000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 40000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 480000000,
- .vco_max = 960000000,
- .freq_table = tegra_pll_u_freq_table,
- .lock_delay = 1000,
- },
-};
-
-static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
- /* 1.7 GHz */
- { 12000000, 1700000000, 850, 6, 1, 8},
- { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
- { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
- { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
- { 26000000, 1700000000, 850, 13, 1, 8},
-
- /* 1.6 GHz */
- { 12000000, 1600000000, 800, 6, 1, 8},
- { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
- { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
- { 19200000, 1600000000, 500, 6, 1, 8},
- { 26000000, 1600000000, 800, 13, 1, 8},
-
- /* 1.5 GHz */
- { 12000000, 1500000000, 750, 6, 1, 8},
- { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
- { 16800000, 1500000000, 625, 7, 1, 8},
- { 19200000, 1500000000, 625, 8, 1, 8},
- { 26000000, 1500000000, 750, 13, 1, 8},
-
- /* 1.4 GHz */
- { 12000000, 1400000000, 700, 6, 1, 8},
- { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
- { 16800000, 1400000000, 1000, 12, 1, 8},
- { 19200000, 1400000000, 875, 12, 1, 8},
- { 26000000, 1400000000, 700, 13, 1, 8},
-
- /* 1.3 GHz */
- { 12000000, 1300000000, 975, 9, 1, 8},
- { 13000000, 1300000000, 1000, 10, 1, 8},
- { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
- { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
- { 26000000, 1300000000, 650, 13, 1, 8},
-
- /* 1.2 GHz */
- { 12000000, 1200000000, 1000, 10, 1, 8},
- { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
- { 16800000, 1200000000, 1000, 14, 1, 8},
- { 19200000, 1200000000, 1000, 16, 1, 8},
- { 26000000, 1200000000, 600, 13, 1, 8},
-
- /* 1.1 GHz */
- { 12000000, 1100000000, 825, 9, 1, 8},
- { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
- { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
- { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
- { 26000000, 1100000000, 550, 13, 1, 8},
-
- /* 1 GHz */
- { 12000000, 1000000000, 1000, 12, 1, 8},
- { 13000000, 1000000000, 1000, 13, 1, 8},
- { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
- { 19200000, 1000000000, 625, 12, 1, 8},
- { 26000000, 1000000000, 1000, 26, 1, 8},
-
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_x = {
- .name = "pll_x",
- .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX,
- .ops = &tegra_pll_ops,
- .reg = 0xe0,
- .parent = &tegra_pll_ref,
- .max_rate = 1700000000,
- .u.pll = {
- .input_min = 2000000,
- .input_max = 31000000,
- .cf_min = 1000000,
- .cf_max = 6000000,
- .vco_min = 20000000,
- .vco_max = 1700000000,
- .freq_table = tegra_pll_x_freq_table,
- .lock_delay = 300,
- },
-};
-
-static struct clk tegra_pll_x_out0 = {
- .name = "pll_x_out0",
- .ops = &tegra_pll_div_ops,
- .flags = DIV_2 | PLLX,
- .parent = &tegra_pll_x,
- .max_rate = 850000000,
-};
-
-
-static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
- /* PLLE special case: use cpcon field to store cml divider value */
- { 12000000, 100000000, 150, 1, 18, 11},
- { 216000000, 100000000, 200, 18, 24, 13},
- { 0, 0, 0, 0, 0, 0 },
-};
-
-static struct clk tegra_pll_e = {
- .name = "pll_e",
- .flags = PLL_ALT_MISC_REG,
- .ops = &tegra_plle_ops,
- .reg = 0xe8,
- .max_rate = 100000000,
- .u.pll = {
- .input_min = 12000000,
- .input_max = 216000000,
- .cf_min = 12000000,
- .cf_max = 12000000,
- .vco_min = 1200000000,
- .vco_max = 2400000000U,
- .freq_table = tegra_pll_e_freq_table,
- .lock_delay = 300,
- .fixed_rate = 100000000,
- },
-};
-
-static struct clk tegra_cml0_clk = {
- .name = "cml0",
- .parent = &tegra_pll_e,
- .ops = &tegra_cml_clk_ops,
- .reg = PLLE_AUX,
- .max_rate = 100000000,
- .u.periph = {
- .clk_num = 0,
- },
-};
-
-static struct clk tegra_cml1_clk = {
- .name = "cml1",
- .parent = &tegra_pll_e,
- .ops = &tegra_cml_clk_ops,
- .reg = PLLE_AUX,
- .max_rate = 100000000,
- .u.periph = {
- .clk_num = 1,
- },
-};
-
-static struct clk tegra_pciex_clk = {
- .name = "pciex",
- .parent = &tegra_pll_e,
- .ops = &tegra_pciex_clk_ops,
- .max_rate = 100000000,
- .u.periph = {
- .clk_num = 74,
- },
-};
-
-/* Audio sync clocks */
-#define SYNC_SOURCE(_id) \
- { \
- .name = #_id "_sync", \
- .rate = 24000000, \
- .max_rate = 24000000, \
- .ops = &tegra_sync_source_ops \
- }
-static struct clk tegra_sync_source_list[] = {
- SYNC_SOURCE(spdif_in),
- SYNC_SOURCE(i2s0),
- SYNC_SOURCE(i2s1),
- SYNC_SOURCE(i2s2),
- SYNC_SOURCE(i2s3),
- SYNC_SOURCE(i2s4),
- SYNC_SOURCE(vimclk),
-};
-
-static struct clk_mux_sel mux_audio_sync_clk[] = {
- { .input = &tegra_sync_source_list[0], .value = 0},
- { .input = &tegra_sync_source_list[1], .value = 1},
- { .input = &tegra_sync_source_list[2], .value = 2},
- { .input = &tegra_sync_source_list[3], .value = 3},
- { .input = &tegra_sync_source_list[4], .value = 4},
- { .input = &tegra_sync_source_list[5], .value = 5},
- { .input = &tegra_pll_a_out0, .value = 6},
- { .input = &tegra_sync_source_list[6], .value = 7},
- { 0, 0 }
-};
-
-#define AUDIO_SYNC_CLK(_id, _index) \
- { \
- .name = #_id, \
- .inputs = mux_audio_sync_clk, \
- .reg = 0x4A0 + (_index) * 4, \
- .max_rate = 24000000, \
- .ops = &tegra_audio_sync_clk_ops \
- }
-static struct clk tegra_clk_audio_list[] = {
- AUDIO_SYNC_CLK(audio0, 0),
- AUDIO_SYNC_CLK(audio1, 1),
- AUDIO_SYNC_CLK(audio2, 2),
- AUDIO_SYNC_CLK(audio3, 3),
- AUDIO_SYNC_CLK(audio4, 4),
- AUDIO_SYNC_CLK(audio, 5), /* SPDIF */
-};
-
-#define AUDIO_SYNC_2X_CLK(_id, _index) \
- { \
- .name = #_id "_2x", \
- .flags = PERIPH_NO_RESET, \
- .max_rate = 48000000, \
- .ops = &tegra_clk_double_ops, \
- .reg = 0x49C, \
- .reg_shift = 24 + (_index), \
- .parent = &tegra_clk_audio_list[(_index)], \
- .u.periph = { \
- .clk_num = 113 + (_index), \
- }, \
- }
-static struct clk tegra_clk_audio_2x_list[] = {
- AUDIO_SYNC_2X_CLK(audio0, 0),
- AUDIO_SYNC_2X_CLK(audio1, 1),
- AUDIO_SYNC_2X_CLK(audio2, 2),
- AUDIO_SYNC_2X_CLK(audio3, 3),
- AUDIO_SYNC_2X_CLK(audio4, 4),
- AUDIO_SYNC_2X_CLK(audio, 5), /* SPDIF */
-};
-
-#define MUX_I2S_SPDIF(_id, _index) \
-static struct clk_mux_sel mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
- {.input = &tegra_pll_a_out0, .value = 0}, \
- {.input = &tegra_clk_audio_2x_list[(_index)], .value = 1}, \
- {.input = &tegra_pll_p, .value = 2}, \
- {.input = &tegra_clk_m, .value = 3}, \
- { 0, 0}, \
-}
-MUX_I2S_SPDIF(audio0, 0);
-MUX_I2S_SPDIF(audio1, 1);
-MUX_I2S_SPDIF(audio2, 2);
-MUX_I2S_SPDIF(audio3, 3);
-MUX_I2S_SPDIF(audio4, 4);
-MUX_I2S_SPDIF(audio, 5); /* SPDIF */
-
-/* External clock outputs (through PMC) */
-#define MUX_EXTERN_OUT(_id) \
-static struct clk_mux_sel mux_clkm_clkm2_clkm4_extern##_id[] = { \
- {.input = &tegra_clk_m, .value = 0}, \
- {.input = &tegra_clk_m_div2, .value = 1}, \
- {.input = &tegra_clk_m_div4, .value = 2}, \
- {.input = NULL, .value = 3}, /* placeholder */ \
- { 0, 0}, \
-}
-MUX_EXTERN_OUT(1);
-MUX_EXTERN_OUT(2);
-MUX_EXTERN_OUT(3);
-
-static struct clk_mux_sel *mux_extern_out_list[] = {
- mux_clkm_clkm2_clkm4_extern1,
- mux_clkm_clkm2_clkm4_extern2,
- mux_clkm_clkm2_clkm4_extern3,
-};
-
-#define CLK_OUT_CLK(_id) \
- { \
- .name = "clk_out_" #_id, \
- .lookup = { \
- .dev_id = "clk_out_" #_id, \
- .con_id = "extern" #_id, \
- }, \
- .ops = &tegra_clk_out_ops, \
- .reg = 0x1a8, \
- .inputs = mux_clkm_clkm2_clkm4_extern##_id, \
- .flags = MUX_CLK_OUT, \
- .max_rate = 216000000, \
- .u.periph = { \
- .clk_num = (_id - 1) * 8 + 2, \
- }, \
- }
-static struct clk tegra_clk_out_list[] = {
- CLK_OUT_CLK(1),
- CLK_OUT_CLK(2),
- CLK_OUT_CLK(3),
-};
-
-/* called after peripheral external clocks are initialized */
-static void init_clk_out_mux(void)
+/* Tegra30 CPU clock and reset control functions */
+static void tegra30_wait_cpu_in_reset(u32 cpu)
{
- int i;
- struct clk *c;
+ unsigned int reg;
- /* output clock con_id is the name of peripheral
- external clock connected to input 3 of the output mux */
- for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++) {
- c = tegra_get_clock_by_name(
- tegra_clk_out_list[i].lookup.con_id);
- if (!c)
- pr_err("%s: could not find clk %s\n", __func__,
- tegra_clk_out_list[i].lookup.con_id);
- mux_extern_out_list[i][3].input = c;
- }
+ do {
+ reg = readl(reg_clk_base +
+ TEGRA30_CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+ cpu_relax();
+ } while (!(reg & (1 << cpu))); /* check CPU been reset or not */
+
+ return;
}
-/* Peripheral muxes */
-static struct clk_mux_sel mux_sclk[] = {
- { .input = &tegra_clk_m, .value = 0},
- { .input = &tegra_pll_c_out1, .value = 1},
- { .input = &tegra_pll_p_out4, .value = 2},
- { .input = &tegra_pll_p_out3, .value = 3},
- { .input = &tegra_pll_p_out2, .value = 4},
- /* { .input = &tegra_clk_d, .value = 5}, - no use on tegra30 */
- { .input = &tegra_clk_32k, .value = 6},
- { .input = &tegra_pll_m_out1, .value = 7},
- { 0, 0},
-};
-
-static struct clk tegra_clk_sclk = {
- .name = "sclk",
- .inputs = mux_sclk,
- .reg = 0x28,
- .ops = &tegra_super_ops,
- .max_rate = 334000000,
- .min_rate = 40000000,
-};
-
-static struct clk tegra_clk_blink = {
- .name = "blink",
- .parent = &tegra_clk_32k,
- .reg = 0x40,
- .ops = &tegra_blink_clk_ops,
- .max_rate = 32768,
-};
-
-static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = {
- { .input = &tegra_pll_m, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_pll_p, .value = 2},
- { .input = &tegra_pll_a_out0, .value = 3},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = {
- { .input = &tegra_pll_p, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_pll_m, .value = 2},
- { .input = &tegra_clk_m, .value = 3},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_clkm[] = {
- { .input = &tegra_pll_p, .value = 0},
- { .input = &tegra_clk_m, .value = 3},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_d_out0, .value = 1},
- {.input = &tegra_pll_c, .value = 2},
- {.input = &tegra_clk_m, .value = 3},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_m, .value = 1},
- {.input = &tegra_pll_d_out0, .value = 2},
- {.input = &tegra_pll_a_out0, .value = 3},
- {.input = &tegra_pll_c, .value = 4},
- {.input = &tegra_pll_d2_out0, .value = 5},
- {.input = &tegra_clk_m, .value = 6},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_plla_pllc_pllp_clkm[] = {
- { .input = &tegra_pll_a_out0, .value = 0},
- /* { .input = &tegra_pll_c, .value = 1}, no use on tegra30 */
- { .input = &tegra_pll_p, .value = 2},
- { .input = &tegra_clk_m, .value = 3},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_clk32_clkm[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_c, .value = 1},
- {.input = &tegra_clk_32k, .value = 2},
- {.input = &tegra_clk_m, .value = 3},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_clkm_clk32[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_c, .value = 1},
- {.input = &tegra_clk_m, .value = 2},
- {.input = &tegra_clk_32k, .value = 3},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_pllc_pllm[] = {
- {.input = &tegra_pll_p, .value = 0},
- {.input = &tegra_pll_c, .value = 1},
- {.input = &tegra_pll_m, .value = 2},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_clk_m[] = {
- { .input = &tegra_clk_m, .value = 0},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_pllp_out3[] = {
- { .input = &tegra_pll_p_out3, .value = 0},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_plld_out0[] = {
- { .input = &tegra_pll_d_out0, .value = 0},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_plld_out0_plld2_out0[] = {
- { .input = &tegra_pll_d_out0, .value = 0},
- { .input = &tegra_pll_d2_out0, .value = 1},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_clk_32k[] = {
- { .input = &tegra_clk_32k, .value = 0},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_plla_clk32_pllp_clkm_plle[] = {
- { .input = &tegra_pll_a_out0, .value = 0},
- { .input = &tegra_clk_32k, .value = 1},
- { .input = &tegra_pll_p, .value = 2},
- { .input = &tegra_clk_m, .value = 3},
- { .input = &tegra_pll_e, .value = 4},
- { 0, 0},
-};
-
-static struct clk_mux_sel mux_cclk_g[] = {
- { .input = &tegra_clk_m, .value = 0},
- { .input = &tegra_pll_c, .value = 1},
- { .input = &tegra_clk_32k, .value = 2},
- { .input = &tegra_pll_m, .value = 3},
- { .input = &tegra_pll_p, .value = 4},
- { .input = &tegra_pll_p_out4, .value = 5},
- { .input = &tegra_pll_p_out3, .value = 6},
- { .input = &tegra_pll_x, .value = 8},
- { 0, 0},
-};
-
-static struct clk tegra_clk_cclk_g = {
- .name = "cclk_g",
- .flags = DIV_U71 | DIV_U71_INT,
- .inputs = mux_cclk_g,
- .reg = 0x368,
- .ops = &tegra_super_ops,
- .max_rate = 1700000000,
-};
-
-static struct clk tegra30_clk_twd = {
- .parent = &tegra_clk_cclk_g,
- .name = "twd",
- .ops = &tegra30_twd_ops,
- .max_rate = 1400000000, /* Same as tegra_clk_cpu_cmplx.max_rate */
- .mul = 1,
- .div = 2,
-};
-
-#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \
- { \
- .name = _name, \
- .lookup = { \
- .dev_id = _dev, \
- .con_id = _con, \
- }, \
- .ops = &tegra_periph_clk_ops, \
- .reg = _reg, \
- .inputs = _inputs, \
- .flags = _flags, \
- .max_rate = _max, \
- .u.periph = { \
- .clk_num = _clk_num, \
- }, \
- }
-
-#define PERIPH_CLK_EX(_name, _dev, _con, _clk_num, _reg, _max, _inputs, \
- _flags, _ops) \
- { \
- .name = _name, \
- .lookup = { \
- .dev_id = _dev, \
- .con_id = _con, \
- }, \
- .ops = _ops, \
- .reg = _reg, \
- .inputs = _inputs, \
- .flags = _flags, \
- .max_rate = _max, \
- .u.periph = { \
- .clk_num = _clk_num, \
- }, \
- }
-
-#define SHARED_CLK(_name, _dev, _con, _parent, _id, _div, _mode)\
- { \
- .name = _name, \
- .lookup = { \
- .dev_id = _dev, \
- .con_id = _con, \
- }, \
- .ops = &tegra_clk_shared_bus_ops, \
- .parent = _parent, \
- .u.shared_bus_user = { \
- .client_id = _id, \
- .client_div = _div, \
- .mode = _mode, \
- }, \
- }
-struct clk tegra_list_clks[] = {
- PERIPH_CLK("apbdma", "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0),
- PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
- PERIPH_CLK("kbc", "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB),
- PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0),
- PERIPH_CLK("kfuse", "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0),
- PERIPH_CLK("fuse", "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
- PERIPH_CLK("fuse_burn", "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB),
- PERIPH_CLK("apbif", "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0),
- PERIPH_CLK("i2s0", "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s1", "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s2", "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s3", "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("i2s4", "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("spdif_out", "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("spdif_in", "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("pwm", "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("d_audio", "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("dam0", "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("dam1", "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("dam2", "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71),
- PERIPH_CLK("hda", "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("hda2codec_2x", "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("hda2hdmi", "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0),
- PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc5", "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sbc6", "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sata_oob", "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sata", "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("sata_cold", "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0),
- PERIPH_CLK_EX("ndflash", "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71, &tegra_nand_clk_ops),
- PERIPH_CLK("ndspeed", "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */
- PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("vde", "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */
- PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71),
- PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB), /* scales with voltage */
- PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c4", "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("i2c5", "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB),
- PERIPH_CLK("uarta", "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartb", "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartc", "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
- PERIPH_CLK("uartd", "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
- PERIPH_CLK("uarte", "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB),
- PERIPH_CLK_EX("vi", "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT, &tegra_vi_clk_ops),
- PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
- PERIPH_CLK("3d2", "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET),
- PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE),
- PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET),
- PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT),
- PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK_EX("dtv", "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0, &tegra_dtv_clk_ops),
- PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */
- PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
- PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8),
- PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
- PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
- PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */
- PERIPH_CLK("dsia", "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0),
- PERIPH_CLK_EX("dsib", "tegradc.1", "dsib", 82, 0xd0, 500000000, mux_plld_out0_plld2_out0, MUX | PLLD, &tegra_dsib_clk_ops),
- PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0),
- PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */
- PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET),
-
- PERIPH_CLK("tsensor", "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71),
- PERIPH_CLK("actmon", "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71),
- PERIPH_CLK("extern1", "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("extern2", "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("extern3", "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71),
- PERIPH_CLK("i2cslow", "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB),
- PERIPH_CLK("pcie", "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("afi", "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0),
- PERIPH_CLK("se", "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT),
-};
-
-#define CLK_DUPLICATE(_name, _dev, _con) \
- { \
- .name = _name, \
- .lookup = { \
- .dev_id = _dev, \
- .con_id = _con, \
- }, \
- }
-
-/* Some clocks may be used by different drivers depending on the board
- * configuration. List those here to register them twice in the clock lookup
- * table under two names.
- */
-struct clk_duplicate tegra_clk_duplicates[] = {
- CLK_DUPLICATE("uarta", "serial8250.0", NULL),
- CLK_DUPLICATE("uartb", "serial8250.1", NULL),
- CLK_DUPLICATE("uartc", "serial8250.2", NULL),
- CLK_DUPLICATE("uartd", "serial8250.3", NULL),
- CLK_DUPLICATE("uarte", "serial8250.4", NULL),
- CLK_DUPLICATE("usbd", "utmip-pad", NULL),
- CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
- CLK_DUPLICATE("usbd", "tegra-otg", NULL),
- CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
- CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
- CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
- CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
- CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
- CLK_DUPLICATE("bsev", "nvavp", "bsev"),
- CLK_DUPLICATE("vde", "tegra-aes", "vde"),
- CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
- CLK_DUPLICATE("bsea", "nvavp", "bsea"),
- CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
- CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
- CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
- CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
- CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
- CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
- CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
- CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
- CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
- CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
- CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
- CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
- CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
- CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
- CLK_DUPLICATE("twd", "smp_twd", NULL),
- CLK_DUPLICATE("vcp", "nvavp", "vcp"),
- CLK_DUPLICATE("i2s0", NULL, "i2s0"),
- CLK_DUPLICATE("i2s1", NULL, "i2s1"),
- CLK_DUPLICATE("i2s2", NULL, "i2s2"),
- CLK_DUPLICATE("i2s3", NULL, "i2s3"),
- CLK_DUPLICATE("i2s4", NULL, "i2s4"),
- CLK_DUPLICATE("dam0", NULL, "dam0"),
- CLK_DUPLICATE("dam1", NULL, "dam1"),
- CLK_DUPLICATE("dam2", NULL, "dam2"),
- CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
-};
-
-struct clk *tegra_ptr_clks[] = {
- &tegra_clk_32k,
- &tegra_clk_m,
- &tegra_clk_m_div2,
- &tegra_clk_m_div4,
- &tegra_pll_ref,
- &tegra_pll_m,
- &tegra_pll_m_out1,
- &tegra_pll_c,
- &tegra_pll_c_out1,
- &tegra_pll_p,
- &tegra_pll_p_out1,
- &tegra_pll_p_out2,
- &tegra_pll_p_out3,
- &tegra_pll_p_out4,
- &tegra_pll_a,
- &tegra_pll_a_out0,
- &tegra_pll_d,
- &tegra_pll_d_out0,
- &tegra_pll_d2,
- &tegra_pll_d2_out0,
- &tegra_pll_u,
- &tegra_pll_x,
- &tegra_pll_x_out0,
- &tegra_pll_e,
- &tegra_clk_cclk_g,
- &tegra_cml0_clk,
- &tegra_cml1_clk,
- &tegra_pciex_clk,
- &tegra_clk_sclk,
- &tegra_clk_blink,
- &tegra30_clk_twd,
-};
-
-
-static void tegra30_init_one_clock(struct clk *c)
+static void tegra30_put_cpu_in_reset(u32 cpu)
{
- clk_init(c);
- INIT_LIST_HEAD(&c->shared_bus_list);
- if (!c->lookup.dev_id && !c->lookup.con_id)
- c->lookup.con_id = c->name;
- c->lookup.clk = c;
- clkdev_add(&c->lookup);
+ writel(CPU_RESET(cpu),
+ reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_SET);
+ dmb();
}
-void __init tegra30_init_clocks(void)
+static void tegra30_cpu_out_of_reset(u32 cpu)
{
- int i;
- struct clk *c;
+ writel(CPU_RESET(cpu),
+ reg_clk_base + TEGRA_CLK_RST_CONTROLLER_RST_CPU_CMPLX_CLR);
+ wmb();
+}
- for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
- tegra30_init_one_clock(tegra_ptr_clks[i]);
+static void tegra30_enable_cpu_clock(u32 cpu)
+{
+ unsigned int reg;
- for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
- tegra30_init_one_clock(&tegra_list_clks[i]);
+ writel(CPU_CLOCK(cpu),
+ reg_clk_base + TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+ reg = readl(reg_clk_base +
+ TEGRA30_CLK_RST_CONTROLLER_CLK_CPU_CMPLX_CLR);
+}
- for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
- c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
- if (!c) {
- pr_err("%s: Unknown duplicate clock %s\n", __func__,
- tegra_clk_duplicates[i].name);
- continue;
- }
+static void tegra30_disable_cpu_clock(u32 cpu)
+{
- tegra_clk_duplicates[i].lookup.clk = c;
- clkdev_add(&tegra_clk_duplicates[i].lookup);
- }
+ unsigned int reg;
- for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
- tegra30_init_one_clock(&tegra_sync_source_list[i]);
- for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
- tegra30_init_one_clock(&tegra_clk_audio_list[i]);
- for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
- tegra30_init_one_clock(&tegra_clk_audio_2x_list[i]);
+ reg = readl(reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+ writel(reg | CPU_CLOCK(cpu),
+ reg_clk_base + TEGRA_CLK_RST_CONTROLLER_CLK_CPU_CMPLX);
+}
- init_clk_out_mux();
- for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
- tegra30_init_one_clock(&tegra_clk_out_list[i]);
+static struct tegra_cpu_car_ops tegra30_cpu_car_ops = {
+ .wait_for_reset = tegra30_wait_cpu_in_reset,
+ .put_in_reset = tegra30_put_cpu_in_reset,
+ .out_of_reset = tegra30_cpu_out_of_reset,
+ .enable_clock = tegra30_enable_cpu_clock,
+ .disable_clock = tegra30_disable_cpu_clock,
+};
+void __init tegra30_cpu_car_ops_init(void)
+{
+ tegra_cpu_car_ops = &tegra30_cpu_car_ops;
}
diff --git a/arch/arm/mach-tegra/tegra30_clocks.h b/arch/arm/mach-tegra/tegra30_clocks.h
new file mode 100644
index 0000000..f2f88fe
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks.h
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA30_CLOCK_H
+#define __MACH_TEGRA30_CLOCK_H
+
+extern struct clk_ops tegra30_clk_32k_ops;
+extern struct clk_ops tegra30_clk_m_ops;
+extern struct clk_ops tegra_clk_m_div_ops;
+extern struct clk_ops tegra_pll_ref_ops;
+extern struct clk_ops tegra30_pll_ops;
+extern struct clk_ops tegra30_pll_div_ops;
+extern struct clk_ops tegra_plld_ops;
+extern struct clk_ops tegra30_plle_ops;
+extern struct clk_ops tegra_cml_clk_ops;
+extern struct clk_ops tegra_pciex_clk_ops;
+extern struct clk_ops tegra_sync_source_ops;
+extern struct clk_ops tegra30_audio_sync_clk_ops;
+extern struct clk_ops tegra30_clk_double_ops;
+extern struct clk_ops tegra_clk_out_ops;
+extern struct clk_ops tegra30_super_ops;
+extern struct clk_ops tegra30_blink_clk_ops;
+extern struct clk_ops tegra30_twd_ops;
+extern struct clk_ops tegra30_periph_clk_ops;
+extern struct clk_ops tegra30_dsib_clk_ops;
+extern struct clk_ops tegra_nand_clk_ops;
+extern struct clk_ops tegra_vi_clk_ops;
+extern struct clk_ops tegra_dtv_clk_ops;
+extern struct clk_ops tegra_clk_shared_bus_ops;
+
+int tegra30_plld_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting);
+void tegra30_periph_clk_reset(struct clk_hw *hw, bool assert);
+int tegra30_vi_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting);
+int tegra30_nand_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting);
+int tegra30_dtv_clk_cfg_ex(struct clk_hw *hw,
+ enum tegra_clk_ex_param p, u32 setting);
+#endif
diff --git a/arch/arm/mach-tegra/tegra30_clocks_data.c b/arch/arm/mach-tegra/tegra30_clocks_data.c
new file mode 100644
index 0000000..c104496
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra30_clocks_data.c
@@ -0,0 +1,1372 @@
+/*
+ * arch/arm/mach-tegra/tegra30_clocks.c
+ *
+ * Copyright (c) 2010-2012 NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ *
+ */
+
+#include <linux/clk-private.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/cpufreq.h>
+
+#include "clock.h"
+#include "fuse.h"
+#include "tegra30_clocks.h"
+#include "tegra_cpu_car.h"
+
+#define DEFINE_CLK_TEGRA(_name, _rate, _ops, _flags, \
+ _parent_names, _parents, _parent) \
+ static struct clk tegra_##_name = { \
+ .hw = &tegra_##_name##_hw.hw, \
+ .name = #_name, \
+ .rate = _rate, \
+ .ops = _ops, \
+ .flags = _flags, \
+ .parent_names = _parent_names, \
+ .parents = _parents, \
+ .num_parents = ARRAY_SIZE(_parent_names), \
+ .parent = _parent, \
+ };
+
+static struct clk tegra_clk_32k;
+static struct clk_tegra tegra_clk_32k_hw = {
+ .hw = {
+ .clk = &tegra_clk_32k,
+ },
+ .fixed_rate = 32768,
+};
+static struct clk tegra_clk_32k = {
+ .name = "clk_32k",
+ .hw = &tegra_clk_32k_hw.hw,
+ .ops = &tegra30_clk_32k_ops,
+ .flags = CLK_IS_ROOT,
+};
+
+static struct clk tegra_clk_m;
+static struct clk_tegra tegra_clk_m_hw = {
+ .hw = {
+ .clk = &tegra_clk_m,
+ },
+ .flags = ENABLE_ON_INIT,
+ .reg = 0x1fc,
+ .reg_shift = 28,
+ .max_rate = 48000000,
+};
+static struct clk tegra_clk_m = {
+ .name = "clk_m",
+ .hw = &tegra_clk_m_hw.hw,
+ .ops = &tegra30_clk_m_ops,
+ .flags = CLK_IS_ROOT | CLK_IGNORE_UNUSED,
+};
+
+static const char *clk_m_div_parent_names[] = {
+ "clk_m",
+};
+
+static struct clk *clk_m_div_parents[] = {
+ &tegra_clk_m,
+};
+
+static struct clk tegra_clk_m_div2;
+static struct clk_tegra tegra_clk_m_div2_hw = {
+ .hw = {
+ .clk = &tegra_clk_m_div2,
+ },
+ .mul = 1,
+ .div = 2,
+ .max_rate = 24000000,
+};
+DEFINE_CLK_TEGRA(clk_m_div2, 0, &tegra_clk_m_div_ops, 0,
+ clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+
+static struct clk tegra_clk_m_div4;
+static struct clk_tegra tegra_clk_m_div4_hw = {
+ .hw = {
+ .clk = &tegra_clk_m_div4,
+ },
+ .mul = 1,
+ .div = 4,
+ .max_rate = 12000000,
+};
+DEFINE_CLK_TEGRA(clk_m_div4, 0, &tegra_clk_m_div_ops, 0,
+ clk_m_div_parent_names, clk_m_div_parents, &tegra_clk_m);
+
+static struct clk tegra_pll_ref;
+static struct clk_tegra tegra_pll_ref_hw = {
+ .hw = {
+ .clk = &tegra_pll_ref,
+ },
+ .flags = ENABLE_ON_INIT,
+ .max_rate = 26000000,
+};
+DEFINE_CLK_TEGRA(pll_ref, 0, &tegra_pll_ref_ops, 0, clk_m_div_parent_names,
+ clk_m_div_parents, &tegra_clk_m);
+
+#define DEFINE_PLL(_name, _flags, _reg, _max_rate, _input_min, \
+ _input_max, _cf_min, _cf_max, _vco_min, \
+ _vco_max, _freq_table, _lock_delay, _ops, \
+ _fixed_rate, _clk_cfg_ex, _parent) \
+ static struct clk tegra_##_name; \
+ static const char *_name##_parent_names[] = { \
+ #_parent, \
+ }; \
+ static struct clk *_name##_parents[] = { \
+ &tegra_##_parent, \
+ }; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .flags = _flags, \
+ .reg = _reg, \
+ .max_rate = _max_rate, \
+ .u.pll = { \
+ .input_min = _input_min, \
+ .input_max = _input_max, \
+ .cf_min = _cf_min, \
+ .cf_max = _cf_max, \
+ .vco_min = _vco_min, \
+ .vco_max = _vco_max, \
+ .freq_table = _freq_table, \
+ .lock_delay = _lock_delay, \
+ .fixed_rate = _fixed_rate, \
+ }, \
+ .clk_cfg_ex = _clk_cfg_ex, \
+ }; \
+ DEFINE_CLK_TEGRA(_name, 0, &_ops, CLK_IGNORE_UNUSED, \
+ _name##_parent_names, _name##_parents, \
+ &tegra_##_parent);
+
+#define DEFINE_PLL_OUT(_name, _flags, _reg, _reg_shift, \
+ _max_rate, _ops, _parent, _clk_flags) \
+ static const char *_name##_parent_names[] = { \
+ #_parent, \
+ }; \
+ static struct clk *_name##_parents[] = { \
+ &tegra_##_parent, \
+ }; \
+ static struct clk tegra_##_name; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .flags = _flags, \
+ .reg = _reg, \
+ .max_rate = _max_rate, \
+ .reg_shift = _reg_shift, \
+ }; \
+ DEFINE_CLK_TEGRA(_name, 0, &tegra30_pll_div_ops, \
+ _clk_flags, _name##_parent_names, \
+ _name##_parents, &tegra_##_parent);
+
+static struct clk_pll_freq_table tegra_pll_c_freq_table[] = {
+ { 12000000, 1040000000, 520, 6, 1, 8},
+ { 13000000, 1040000000, 480, 6, 1, 8},
+ { 16800000, 1040000000, 495, 8, 1, 8}, /* actual: 1039.5 MHz */
+ { 19200000, 1040000000, 325, 6, 1, 6},
+ { 26000000, 1040000000, 520, 13, 1, 8},
+
+ { 12000000, 832000000, 416, 6, 1, 8},
+ { 13000000, 832000000, 832, 13, 1, 8},
+ { 16800000, 832000000, 396, 8, 1, 8}, /* actual: 831.6 MHz */
+ { 19200000, 832000000, 260, 6, 1, 8},
+ { 26000000, 832000000, 416, 13, 1, 8},
+
+ { 12000000, 624000000, 624, 12, 1, 8},
+ { 13000000, 624000000, 624, 13, 1, 8},
+ { 16800000, 600000000, 520, 14, 1, 8},
+ { 19200000, 624000000, 520, 16, 1, 8},
+ { 26000000, 624000000, 624, 26, 1, 8},
+
+ { 12000000, 600000000, 600, 12, 1, 8},
+ { 13000000, 600000000, 600, 13, 1, 8},
+ { 16800000, 600000000, 500, 14, 1, 8},
+ { 19200000, 600000000, 375, 12, 1, 6},
+ { 26000000, 600000000, 600, 26, 1, 8},
+
+ { 12000000, 520000000, 520, 12, 1, 8},
+ { 13000000, 520000000, 520, 13, 1, 8},
+ { 16800000, 520000000, 495, 16, 1, 8}, /* actual: 519.75 MHz */
+ { 19200000, 520000000, 325, 12, 1, 6},
+ { 26000000, 520000000, 520, 26, 1, 8},
+
+ { 12000000, 416000000, 416, 12, 1, 8},
+ { 13000000, 416000000, 416, 13, 1, 8},
+ { 16800000, 416000000, 396, 16, 1, 8}, /* actual: 415.8 MHz */
+ { 19200000, 416000000, 260, 12, 1, 6},
+ { 26000000, 416000000, 416, 26, 1, 8},
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_c, PLL_HAS_CPCON, 0x80, 1400000000, 2000000, 31000000, 1000000,
+ 6000000, 20000000, 1400000000, tegra_pll_c_freq_table, 300,
+ tegra30_pll_ops, 0, NULL, pll_ref);
+
+DEFINE_PLL_OUT(pll_c_out1, DIV_U71, 0x84, 0, 700000000,
+ tegra30_pll_div_ops, pll_c, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_m_freq_table[] = {
+ { 12000000, 666000000, 666, 12, 1, 8},
+ { 13000000, 666000000, 666, 13, 1, 8},
+ { 16800000, 666000000, 555, 14, 1, 8},
+ { 19200000, 666000000, 555, 16, 1, 8},
+ { 26000000, 666000000, 666, 26, 1, 8},
+ { 12000000, 600000000, 600, 12, 1, 8},
+ { 13000000, 600000000, 600, 13, 1, 8},
+ { 16800000, 600000000, 500, 14, 1, 8},
+ { 19200000, 600000000, 375, 12, 1, 6},
+ { 26000000, 600000000, 600, 26, 1, 8},
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_m, PLL_HAS_CPCON | PLLM, 0x90, 800000000, 2000000, 31000000,
+ 1000000, 6000000, 20000000, 1200000000, tegra_pll_m_freq_table,
+ 300, tegra30_pll_ops, 0, NULL, pll_ref);
+
+DEFINE_PLL_OUT(pll_m_out1, DIV_U71, 0x94, 0, 600000000,
+ tegra30_pll_div_ops, pll_m, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_p_freq_table[] = {
+ { 12000000, 216000000, 432, 12, 2, 8},
+ { 13000000, 216000000, 432, 13, 2, 8},
+ { 16800000, 216000000, 360, 14, 2, 8},
+ { 19200000, 216000000, 360, 16, 2, 8},
+ { 26000000, 216000000, 432, 26, 2, 8},
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_p, ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, 0xa0, 432000000,
+ 2000000, 31000000, 1000000, 6000000, 20000000, 1400000000,
+ tegra_pll_p_freq_table, 300, tegra30_pll_ops, 408000000, NULL,
+ pll_ref);
+
+DEFINE_PLL_OUT(pll_p_out1, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+ 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out2, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa4,
+ 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out3, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+ 0, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+DEFINE_PLL_OUT(pll_p_out4, ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, 0xa8,
+ 16, 432000000, tegra30_pll_div_ops, pll_p, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_a_freq_table[] = {
+ { 9600000, 564480000, 294, 5, 1, 4},
+ { 9600000, 552960000, 288, 5, 1, 4},
+ { 9600000, 24000000, 5, 2, 1, 1},
+
+ { 28800000, 56448000, 49, 25, 1, 1},
+ { 28800000, 73728000, 64, 25, 1, 1},
+ { 28800000, 24000000, 5, 6, 1, 1},
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_a, PLL_HAS_CPCON, 0xb0, 700000000, 2000000, 31000000, 1000000,
+ 6000000, 20000000, 1400000000, tegra_pll_a_freq_table,
+ 300, tegra30_pll_ops, 0, NULL, pll_p_out1);
+
+DEFINE_PLL_OUT(pll_a_out0, DIV_U71, 0xb4, 0, 100000000, tegra30_pll_div_ops,
+ pll_a, CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_d_freq_table[] = {
+ { 12000000, 216000000, 216, 12, 1, 4},
+ { 13000000, 216000000, 216, 13, 1, 4},
+ { 16800000, 216000000, 180, 14, 1, 4},
+ { 19200000, 216000000, 180, 16, 1, 4},
+ { 26000000, 216000000, 216, 26, 1, 4},
+
+ { 12000000, 594000000, 594, 12, 1, 8},
+ { 13000000, 594000000, 594, 13, 1, 8},
+ { 16800000, 594000000, 495, 14, 1, 8},
+ { 19200000, 594000000, 495, 16, 1, 8},
+ { 26000000, 594000000, 594, 26, 1, 8},
+
+ { 12000000, 1000000000, 1000, 12, 1, 12},
+ { 13000000, 1000000000, 1000, 13, 1, 12},
+ { 19200000, 1000000000, 625, 12, 1, 8},
+ { 26000000, 1000000000, 1000, 26, 1, 12},
+
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_d, PLL_HAS_CPCON | PLLD, 0xd0, 1000000000, 2000000, 40000000,
+ 1000000, 6000000, 40000000, 1000000000, tegra_pll_d_freq_table,
+ 1000, tegra30_pll_ops, 0, tegra30_plld_clk_cfg_ex, pll_ref);
+
+DEFINE_PLL_OUT(pll_d_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+ pll_d, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+
+DEFINE_PLL(pll_d2, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLD, 0x4b8, 1000000000,
+ 2000000, 40000000, 1000000, 6000000, 40000000, 1000000000,
+ tegra_pll_d_freq_table, 1000, tegra30_pll_ops, 0, NULL,
+ pll_ref);
+
+DEFINE_PLL_OUT(pll_d2_out0, DIV_2 | PLLD, 0, 0, 500000000, tegra30_pll_div_ops,
+ pll_d2, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_u_freq_table[] = {
+ { 12000000, 480000000, 960, 12, 2, 12},
+ { 13000000, 480000000, 960, 13, 2, 12},
+ { 16800000, 480000000, 400, 7, 2, 5},
+ { 19200000, 480000000, 200, 4, 2, 3},
+ { 26000000, 480000000, 960, 26, 2, 12},
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_u, PLL_HAS_CPCON | PLLU, 0xc0, 480000000, 2000000, 40000000,
+ 1000000, 6000000, 48000000, 960000000, tegra_pll_u_freq_table,
+ 1000, tegra30_pll_ops, 0, NULL, pll_ref);
+
+static struct clk_pll_freq_table tegra_pll_x_freq_table[] = {
+ /* 1.7 GHz */
+ { 12000000, 1700000000, 850, 6, 1, 8},
+ { 13000000, 1700000000, 915, 7, 1, 8}, /* actual: 1699.2 MHz */
+ { 16800000, 1700000000, 708, 7, 1, 8}, /* actual: 1699.2 MHz */
+ { 19200000, 1700000000, 885, 10, 1, 8}, /* actual: 1699.2 MHz */
+ { 26000000, 1700000000, 850, 13, 1, 8},
+
+ /* 1.6 GHz */
+ { 12000000, 1600000000, 800, 6, 1, 8},
+ { 13000000, 1600000000, 738, 6, 1, 8}, /* actual: 1599.0 MHz */
+ { 16800000, 1600000000, 857, 9, 1, 8}, /* actual: 1599.7 MHz */
+ { 19200000, 1600000000, 500, 6, 1, 8},
+ { 26000000, 1600000000, 800, 13, 1, 8},
+
+ /* 1.5 GHz */
+ { 12000000, 1500000000, 750, 6, 1, 8},
+ { 13000000, 1500000000, 923, 8, 1, 8}, /* actual: 1499.8 MHz */
+ { 16800000, 1500000000, 625, 7, 1, 8},
+ { 19200000, 1500000000, 625, 8, 1, 8},
+ { 26000000, 1500000000, 750, 13, 1, 8},
+
+ /* 1.4 GHz */
+ { 12000000, 1400000000, 700, 6, 1, 8},
+ { 13000000, 1400000000, 969, 9, 1, 8}, /* actual: 1399.7 MHz */
+ { 16800000, 1400000000, 1000, 12, 1, 8},
+ { 19200000, 1400000000, 875, 12, 1, 8},
+ { 26000000, 1400000000, 700, 13, 1, 8},
+
+ /* 1.3 GHz */
+ { 12000000, 1300000000, 975, 9, 1, 8},
+ { 13000000, 1300000000, 1000, 10, 1, 8},
+ { 16800000, 1300000000, 928, 12, 1, 8}, /* actual: 1299.2 MHz */
+ { 19200000, 1300000000, 812, 12, 1, 8}, /* actual: 1299.2 MHz */
+ { 26000000, 1300000000, 650, 13, 1, 8},
+
+ /* 1.2 GHz */
+ { 12000000, 1200000000, 1000, 10, 1, 8},
+ { 13000000, 1200000000, 923, 10, 1, 8}, /* actual: 1199.9 MHz */
+ { 16800000, 1200000000, 1000, 14, 1, 8},
+ { 19200000, 1200000000, 1000, 16, 1, 8},
+ { 26000000, 1200000000, 600, 13, 1, 8},
+
+ /* 1.1 GHz */
+ { 12000000, 1100000000, 825, 9, 1, 8},
+ { 13000000, 1100000000, 846, 10, 1, 8}, /* actual: 1099.8 MHz */
+ { 16800000, 1100000000, 982, 15, 1, 8}, /* actual: 1099.8 MHz */
+ { 19200000, 1100000000, 859, 15, 1, 8}, /* actual: 1099.5 MHz */
+ { 26000000, 1100000000, 550, 13, 1, 8},
+
+ /* 1 GHz */
+ { 12000000, 1000000000, 1000, 12, 1, 8},
+ { 13000000, 1000000000, 1000, 13, 1, 8},
+ { 16800000, 1000000000, 833, 14, 1, 8}, /* actual: 999.6 MHz */
+ { 19200000, 1000000000, 625, 12, 1, 8},
+ { 26000000, 1000000000, 1000, 26, 1, 8},
+
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_x, PLL_HAS_CPCON | PLL_ALT_MISC_REG | PLLX, 0xe0, 1700000000,
+ 2000000, 31000000, 1000000, 6000000, 20000000, 1700000000,
+ tegra_pll_x_freq_table, 300, tegra30_pll_ops, 0, NULL, pll_ref);
+
+DEFINE_PLL_OUT(pll_x_out0, DIV_2 | PLLX, 0, 0, 850000000, tegra30_pll_div_ops,
+ pll_x, CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED);
+
+static struct clk_pll_freq_table tegra_pll_e_freq_table[] = {
+ /* PLLE special case: use cpcon field to store cml divider value */
+ { 12000000, 100000000, 150, 1, 18, 11},
+ { 216000000, 100000000, 200, 18, 24, 13},
+ { 0, 0, 0, 0, 0, 0 },
+};
+
+DEFINE_PLL(pll_e, PLL_ALT_MISC_REG, 0xe8, 100000000, 2000000, 216000000,
+ 12000000, 12000000, 1200000000, 2400000000U,
+ tegra_pll_e_freq_table, 300, tegra30_plle_ops, 100000000, NULL,
+ pll_ref);
+
+static const char *mux_plle[] = {
+ "pll_e",
+};
+
+static struct clk *mux_plle_p[] = {
+ &tegra_pll_e,
+};
+
+static struct clk tegra_cml0;
+static struct clk_tegra tegra_cml0_hw = {
+ .hw = {
+ .clk = &tegra_cml0,
+ },
+ .reg = 0x48c,
+ .fixed_rate = 100000000,
+ .u.periph = {
+ .clk_num = 0,
+ },
+};
+DEFINE_CLK_TEGRA(cml0, 0, &tegra_cml_clk_ops, 0, mux_plle,
+ mux_plle_p, &tegra_pll_e);
+
+static struct clk tegra_cml1;
+static struct clk_tegra tegra_cml1_hw = {
+ .hw = {
+ .clk = &tegra_cml1,
+ },
+ .reg = 0x48c,
+ .fixed_rate = 100000000,
+ .u.periph = {
+ .clk_num = 1,
+ },
+};
+DEFINE_CLK_TEGRA(cml1, 0, &tegra_cml_clk_ops, 0, mux_plle,
+ mux_plle_p, &tegra_pll_e);
+
+static struct clk tegra_pciex;
+static struct clk_tegra tegra_pciex_hw = {
+ .hw = {
+ .clk = &tegra_pciex,
+ },
+ .reg = 0x48c,
+ .fixed_rate = 100000000,
+ .reset = tegra30_periph_clk_reset,
+ .u.periph = {
+ .clk_num = 74,
+ },
+};
+DEFINE_CLK_TEGRA(pciex, 0, &tegra_pciex_clk_ops, 0, mux_plle,
+ mux_plle_p, &tegra_pll_e);
+
+#define SYNC_SOURCE(_name) \
+ static struct clk tegra_##_name##_sync; \
+ static struct clk_tegra tegra_##_name##_sync_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name##_sync, \
+ }, \
+ .max_rate = 24000000, \
+ .fixed_rate = 24000000, \
+ }; \
+ static struct clk tegra_##_name##_sync = { \
+ .name = #_name "_sync", \
+ .hw = &tegra_##_name##_sync_hw.hw, \
+ .ops = &tegra_sync_source_ops, \
+ .flags = CLK_IS_ROOT, \
+ };
+
+SYNC_SOURCE(spdif_in);
+SYNC_SOURCE(i2s0);
+SYNC_SOURCE(i2s1);
+SYNC_SOURCE(i2s2);
+SYNC_SOURCE(i2s3);
+SYNC_SOURCE(i2s4);
+SYNC_SOURCE(vimclk);
+
+static struct clk *tegra_sync_source_list[] = {
+ &tegra_spdif_in_sync,
+ &tegra_i2s0_sync,
+ &tegra_i2s1_sync,
+ &tegra_i2s2_sync,
+ &tegra_i2s3_sync,
+ &tegra_i2s4_sync,
+ &tegra_vimclk_sync,
+};
+
+static const char *mux_audio_sync_clk[] = {
+ "spdif_in_sync",
+ "i2s0_sync",
+ "i2s1_sync",
+ "i2s2_sync",
+ "i2s3_sync",
+ "i2s4_sync",
+ "vimclk_sync",
+};
+
+#define AUDIO_SYNC_CLK(_name, _index) \
+ static struct clk tegra_##_name; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .max_rate = 24000000, \
+ .reg = 0x4A0 + (_index) * 4, \
+ }; \
+ static struct clk tegra_##_name = { \
+ .name = #_name, \
+ .ops = &tegra30_audio_sync_clk_ops, \
+ .hw = &tegra_##_name##_hw.hw, \
+ .parent_names = mux_audio_sync_clk, \
+ .parents = tegra_sync_source_list, \
+ .num_parents = ARRAY_SIZE(mux_audio_sync_clk), \
+ };
+
+AUDIO_SYNC_CLK(audio0, 0);
+AUDIO_SYNC_CLK(audio1, 1);
+AUDIO_SYNC_CLK(audio2, 2);
+AUDIO_SYNC_CLK(audio3, 3);
+AUDIO_SYNC_CLK(audio4, 4);
+AUDIO_SYNC_CLK(audio5, 5);
+
+static struct clk *tegra_clk_audio_list[] = {
+ &tegra_audio0,
+ &tegra_audio1,
+ &tegra_audio2,
+ &tegra_audio3,
+ &tegra_audio4,
+ &tegra_audio5, /* SPDIF */
+};
+
+#define AUDIO_SYNC_2X_CLK(_name, _index) \
+ static const char *_name##_parent_names[] = { \
+ "tegra_" #_name, \
+ }; \
+ static struct clk *_name##_parents[] = { \
+ &tegra_##_name, \
+ }; \
+ static struct clk tegra_##_name##_2x; \
+ static struct clk_tegra tegra_##_name##_2x_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name##_2x, \
+ }, \
+ .flags = PERIPH_NO_RESET, \
+ .max_rate = 48000000, \
+ .reg = 0x49C, \
+ .reg_shift = 24 + (_index), \
+ .u.periph = { \
+ .clk_num = 113 + (_index), \
+ }, \
+ }; \
+ static struct clk tegra_##_name##_2x = { \
+ .name = #_name "_2x", \
+ .ops = &tegra30_clk_double_ops, \
+ .hw = &tegra_##_name##_2x_hw.hw, \
+ .parent_names = _name##_parent_names, \
+ .parents = _name##_parents, \
+ .parent = &tegra_##_name, \
+ .num_parents = 1, \
+ };
+
+AUDIO_SYNC_2X_CLK(audio0, 0);
+AUDIO_SYNC_2X_CLK(audio1, 1);
+AUDIO_SYNC_2X_CLK(audio2, 2);
+AUDIO_SYNC_2X_CLK(audio3, 3);
+AUDIO_SYNC_2X_CLK(audio4, 4);
+AUDIO_SYNC_2X_CLK(audio5, 5); /* SPDIF */
+
+static struct clk *tegra_clk_audio_2x_list[] = {
+ &tegra_audio0_2x,
+ &tegra_audio1_2x,
+ &tegra_audio2_2x,
+ &tegra_audio3_2x,
+ &tegra_audio4_2x,
+ &tegra_audio5_2x, /* SPDIF */
+};
+
+#define MUX_I2S_SPDIF(_id) \
+static const char *mux_pllaout0_##_id##_2x_pllp_clkm[] = { \
+ "pll_a_out0", \
+ #_id "_2x", \
+ "pll_p", \
+ "clk_m", \
+}; \
+static struct clk *mux_pllaout0_##_id##_2x_pllp_clkm_p[] = { \
+ &tegra_pll_a_out0, \
+ &tegra_##_id##_2x, \
+ &tegra_pll_p, \
+ &tegra_clk_m, \
+};
+
+MUX_I2S_SPDIF(audio0);
+MUX_I2S_SPDIF(audio1);
+MUX_I2S_SPDIF(audio2);
+MUX_I2S_SPDIF(audio3);
+MUX_I2S_SPDIF(audio4);
+MUX_I2S_SPDIF(audio5); /* SPDIF */
+
+static struct clk tegra_extern1;
+static struct clk tegra_extern2;
+static struct clk tegra_extern3;
+
+/* External clock outputs (through PMC) */
+#define MUX_EXTERN_OUT(_id) \
+static const char *mux_clkm_clkm2_clkm4_extern##_id[] = { \
+ "clk_m", \
+ "clk_m_div2", \
+ "clk_m_div4", \
+ "extern" #_id, \
+}; \
+static struct clk *mux_clkm_clkm2_clkm4_extern##_id##_p[] = { \
+ &tegra_clk_m, \
+ &tegra_clk_m_div2, \
+ &tegra_clk_m_div4, \
+ &tegra_extern##_id, \
+};
+
+MUX_EXTERN_OUT(1);
+MUX_EXTERN_OUT(2);
+MUX_EXTERN_OUT(3);
+
+#define CLK_OUT_CLK(_name, _index) \
+ static struct clk tegra_##_name; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .lookup = { \
+ .dev_id = #_name, \
+ .con_id = "extern" #_index, \
+ }, \
+ .flags = MUX_CLK_OUT, \
+ .fixed_rate = 216000000, \
+ .reg = 0x1a8, \
+ .u.periph = { \
+ .clk_num = (_index - 1) * 8 + 2, \
+ }, \
+ }; \
+ static struct clk tegra_##_name = { \
+ .name = #_name, \
+ .ops = &tegra_clk_out_ops, \
+ .hw = &tegra_##_name##_hw.hw, \
+ .parent_names = mux_clkm_clkm2_clkm4_extern##_index, \
+ .parents = mux_clkm_clkm2_clkm4_extern##_index##_p, \
+ .num_parents = ARRAY_SIZE(mux_clkm_clkm2_clkm4_extern##_index),\
+ };
+
+CLK_OUT_CLK(clk_out_1, 1);
+CLK_OUT_CLK(clk_out_2, 2);
+CLK_OUT_CLK(clk_out_3, 3);
+
+static struct clk *tegra_clk_out_list[] = {
+ &tegra_clk_out_1,
+ &tegra_clk_out_2,
+ &tegra_clk_out_3,
+};
+
+static const char *mux_sclk[] = {
+ "clk_m",
+ "pll_c_out1",
+ "pll_p_out4",
+ "pll_p_out3",
+ "pll_p_out2",
+ "dummy",
+ "clk_32k",
+ "pll_m_out1",
+};
+
+static struct clk *mux_sclk_p[] = {
+ &tegra_clk_m,
+ &tegra_pll_c_out1,
+ &tegra_pll_p_out4,
+ &tegra_pll_p_out3,
+ &tegra_pll_p_out2,
+ NULL,
+ &tegra_clk_32k,
+ &tegra_pll_m_out1,
+};
+
+static struct clk tegra_clk_sclk;
+static struct clk_tegra tegra_clk_sclk_hw = {
+ .hw = {
+ .clk = &tegra_clk_sclk,
+ },
+ .reg = 0x28,
+ .max_rate = 334000000,
+ .min_rate = 40000000,
+};
+
+static struct clk tegra_clk_sclk = {
+ .name = "sclk",
+ .ops = &tegra30_super_ops,
+ .hw = &tegra_clk_sclk_hw.hw,
+ .parent_names = mux_sclk,
+ .parents = mux_sclk_p,
+ .num_parents = ARRAY_SIZE(mux_sclk),
+};
+
+static const char *mux_blink[] = {
+ "clk_32k",
+};
+
+static struct clk *mux_blink_p[] = {
+ &tegra_clk_32k,
+};
+
+static struct clk tegra_clk_blink;
+static struct clk_tegra tegra_clk_blink_hw = {
+ .hw = {
+ .clk = &tegra_clk_blink,
+ },
+ .reg = 0x40,
+ .max_rate = 32768,
+};
+static struct clk tegra_clk_blink = {
+ .name = "blink",
+ .ops = &tegra30_blink_clk_ops,
+ .hw = &tegra_clk_blink_hw.hw,
+ .parent = &tegra_clk_32k,
+ .parent_names = mux_blink,
+ .parents = mux_blink_p,
+ .num_parents = ARRAY_SIZE(mux_blink),
+};
+
+static const char *mux_pllm_pllc_pllp_plla[] = {
+ "pll_m",
+ "pll_c",
+ "pll_p",
+ "pll_a_out0",
+};
+
+static const char *mux_pllp_pllc_pllm_clkm[] = {
+ "pll_p",
+ "pll_c",
+ "pll_m",
+ "clk_m",
+};
+
+static const char *mux_pllp_clkm[] = {
+ "pll_p",
+ "dummy",
+ "dummy",
+ "clk_m",
+};
+
+static const char *mux_pllp_plld_pllc_clkm[] = {
+ "pll_p",
+ "pll_d_out0",
+ "pll_c",
+ "clk_m",
+};
+
+static const char *mux_pllp_pllm_plld_plla_pllc_plld2_clkm[] = {
+ "pll_p",
+ "pll_m",
+ "pll_d_out0",
+ "pll_a_out0",
+ "pll_c",
+ "pll_d2_out0",
+ "clk_m",
+};
+
+static const char *mux_plla_pllc_pllp_clkm[] = {
+ "pll_a_out0",
+ "dummy",
+ "pll_p",
+ "clk_m"
+};
+
+static const char *mux_pllp_pllc_clk32_clkm[] = {
+ "pll_p",
+ "pll_c",
+ "clk_32k",
+ "clk_m",
+};
+
+static const char *mux_pllp_pllc_clkm_clk32[] = {
+ "pll_p",
+ "pll_c",
+ "clk_m",
+ "clk_32k",
+};
+
+static const char *mux_pllp_pllc_pllm[] = {
+ "pll_p",
+ "pll_c",
+ "pll_m",
+};
+
+static const char *mux_clk_m[] = {
+ "clk_m",
+};
+
+static const char *mux_pllp_out3[] = {
+ "pll_p_out3",
+};
+
+static const char *mux_plld_out0[] = {
+ "pll_d_out0",
+};
+
+static const char *mux_plld_out0_plld2_out0[] = {
+ "pll_d_out0",
+ "pll_d2_out0",
+};
+
+static const char *mux_clk_32k[] = {
+ "clk_32k",
+};
+
+static const char *mux_plla_clk32_pllp_clkm_plle[] = {
+ "pll_a_out0",
+ "clk_32k",
+ "pll_p",
+ "clk_m",
+ "pll_e",
+};
+
+static const char *mux_cclk_g[] = {
+ "clk_m",
+ "pll_c",
+ "clk_32k",
+ "pll_m",
+ "pll_p",
+ "pll_p_out4",
+ "pll_p_out3",
+ "dummy",
+ "pll_x",
+};
+
+static struct clk *mux_pllm_pllc_pllp_plla_p[] = {
+ &tegra_pll_m,
+ &tegra_pll_c,
+ &tegra_pll_p,
+ &tegra_pll_a_out0,
+};
+
+static struct clk *mux_pllp_pllc_pllm_clkm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_c,
+ &tegra_pll_m,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_clkm_p[] = {
+ &tegra_pll_p,
+ NULL,
+ NULL,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_plld_pllc_clkm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_d_out0,
+ &tegra_pll_c,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllm_plld_plla_pllc_plld2_clkm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_m,
+ &tegra_pll_d_out0,
+ &tegra_pll_a_out0,
+ &tegra_pll_c,
+ &tegra_pll_d2_out0,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_plla_pllc_pllp_clkm_p[] = {
+ &tegra_pll_a_out0,
+ NULL,
+ &tegra_pll_p,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllc_clk32_clkm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_c,
+ &tegra_clk_32k,
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_pllc_clkm_clk32_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_c,
+ &tegra_clk_m,
+ &tegra_clk_32k,
+};
+
+static struct clk *mux_pllp_pllc_pllm_p[] = {
+ &tegra_pll_p,
+ &tegra_pll_c,
+ &tegra_pll_m,
+};
+
+static struct clk *mux_clk_m_p[] = {
+ &tegra_clk_m,
+};
+
+static struct clk *mux_pllp_out3_p[] = {
+ &tegra_pll_p_out3,
+};
+
+static struct clk *mux_plld_out0_p[] = {
+ &tegra_pll_d_out0,
+};
+
+static struct clk *mux_plld_out0_plld2_out0_p[] = {
+ &tegra_pll_d_out0,
+ &tegra_pll_d2_out0,
+};
+
+static struct clk *mux_clk_32k_p[] = {
+ &tegra_clk_32k,
+};
+
+static struct clk *mux_plla_clk32_pllp_clkm_plle_p[] = {
+ &tegra_pll_a_out0,
+ &tegra_clk_32k,
+ &tegra_pll_p,
+ &tegra_clk_m,
+ &tegra_pll_e,
+};
+
+static struct clk *mux_cclk_g_p[] = {
+ &tegra_clk_m,
+ &tegra_pll_c,
+ &tegra_clk_32k,
+ &tegra_pll_m,
+ &tegra_pll_p,
+ &tegra_pll_p_out4,
+ &tegra_pll_p_out3,
+ NULL,
+ &tegra_pll_x,
+};
+
+static struct clk tegra_clk_cclk_g;
+static struct clk_tegra tegra_clk_cclk_g_hw = {
+ .hw = {
+ .clk = &tegra_clk_cclk_g,
+ },
+ .flags = DIV_U71 | DIV_U71_INT,
+ .reg = 0x368,
+ .max_rate = 1700000000,
+};
+static struct clk tegra_clk_cclk_g = {
+ .name = "cclk_g",
+ .ops = &tegra30_super_ops,
+ .hw = &tegra_clk_cclk_g_hw.hw,
+ .parent_names = mux_cclk_g,
+ .parents = mux_cclk_g_p,
+ .num_parents = ARRAY_SIZE(mux_cclk_g),
+};
+
+static const char *mux_twd[] = {
+ "cclk_g",
+};
+
+static struct clk *mux_twd_p[] = {
+ &tegra_clk_cclk_g,
+};
+
+static struct clk tegra30_clk_twd;
+static struct clk_tegra tegra30_clk_twd_hw = {
+ .hw = {
+ .clk = &tegra30_clk_twd,
+ },
+ .max_rate = 1400000000,
+ .mul = 1,
+ .div = 2,
+};
+
+static struct clk tegra30_clk_twd = {
+ .name = "twd",
+ .ops = &tegra30_twd_ops,
+ .hw = &tegra30_clk_twd_hw.hw,
+ .parent = &tegra_clk_cclk_g,
+ .parent_names = mux_twd,
+ .parents = mux_twd_p,
+ .num_parents = ARRAY_SIZE(mux_twd),
+};
+
+#define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, \
+ _max, _inputs, _flags) \
+ static struct clk tegra_##_name; \
+ static struct clk_tegra tegra_##_name##_hw = { \
+ .hw = { \
+ .clk = &tegra_##_name, \
+ }, \
+ .lookup = { \
+ .dev_id = _dev, \
+ .con_id = _con, \
+ }, \
+ .reg = _reg, \
+ .flags = _flags, \
+ .max_rate = _max, \
+ .u.periph = { \
+ .clk_num = _clk_num, \
+ }, \
+ .reset = &tegra30_periph_clk_reset, \
+ }; \
+ static struct clk tegra_##_name = { \
+ .name = #_name, \
+ .ops = &tegra30_periph_clk_ops, \
+ .hw = &tegra_##_name##_hw.hw, \
+ .parent_names = _inputs, \
+ .parents = _inputs##_p, \
+ .num_parents = ARRAY_SIZE(_inputs), \
+ };
+
+PERIPH_CLK(apbdma, "tegra-apbdma", NULL, 34, 0, 26000000, mux_clk_m, 0);
+PERIPH_CLK(rtc, "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(kbc, "tegra-kbc", NULL, 36, 0, 32768, mux_clk_32k, PERIPH_NO_RESET | PERIPH_ON_APB);
+PERIPH_CLK(timer, "timer", NULL, 5, 0, 26000000, mux_clk_m, 0);
+PERIPH_CLK(kfuse, "kfuse-tegra", NULL, 40, 0, 26000000, mux_clk_m, 0);
+PERIPH_CLK(fuse, "fuse-tegra", "fuse", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
+PERIPH_CLK(fuse_burn, "fuse-tegra", "fuse_burn", 39, 0, 26000000, mux_clk_m, PERIPH_ON_APB);
+PERIPH_CLK(apbif, "tegra30-ahub", "apbif", 107, 0, 26000000, mux_clk_m, 0);
+PERIPH_CLK(i2s0, "tegra30-i2s.0", NULL, 30, 0x1d8, 26000000, mux_pllaout0_audio0_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s1, "tegra30-i2s.1", NULL, 11, 0x100, 26000000, mux_pllaout0_audio1_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s2, "tegra30-i2s.2", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s3, "tegra30-i2s.3", NULL, 101, 0x3bc, 26000000, mux_pllaout0_audio3_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(i2s4, "tegra30-i2s.4", NULL, 102, 0x3c0, 26000000, mux_pllaout0_audio4_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_out, "tegra30-spdif", "spdif_out", 10, 0x108, 100000000, mux_pllaout0_audio5_2x_pllp_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(spdif_in, "tegra30-spdif", "spdif_in", 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pwm, "tegra-pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_clk32_clkm, MUX | MUX_PWM | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(d_audio, "tegra30-ahub", "d_audio", 106, 0x3d0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
+PERIPH_CLK(dam0, "tegra30-dam.0", NULL, 108, 0x3d8, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
+PERIPH_CLK(dam1, "tegra30-dam.1", NULL, 109, 0x3dc, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
+PERIPH_CLK(dam2, "tegra30-dam.2", NULL, 110, 0x3e0, 48000000, mux_plla_pllc_pllp_clkm, MUX | DIV_U71);
+PERIPH_CLK(hda, "tegra30-hda", "hda", 125, 0x428, 108000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(hda2codec_2x, "tegra30-hda", "hda2codec", 111, 0x3e4, 48000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(hda2hdmi, "tegra30-hda", "hda2hdmi", 128, 0, 48000000, mux_clk_m, 0);
+PERIPH_CLK(sbc1, "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc2, "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc3, "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc4, "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc5, "spi_tegra.4", NULL, 104, 0x3c8, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sbc6, "spi_tegra.5", NULL, 105, 0x3cc, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sata_oob, "tegra_sata_oob", NULL, 123, 0x420, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(sata, "tegra_sata", NULL, 124, 0x424, 216000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(sata_cold, "tegra_sata_cold", NULL, 129, 0, 48000000, mux_clk_m, 0);
+PERIPH_CLK(ndflash, "tegra_nand", NULL, 13, 0x160, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(ndspeed, "tegra_nand_speed", NULL, 80, 0x3f8, 240000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(vfir, "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(sdmmc1, "sdhci-tegra.0", NULL, 14, 0x150, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc2, "sdhci-tegra.1", NULL, 9, 0x154, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc3, "sdhci-tegra.2", NULL, 69, 0x1bc, 208000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(sdmmc4, "sdhci-tegra.3", NULL, 15, 0x164, 104000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* scales with voltage */
+PERIPH_CLK(vcp, "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(bsea, "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(bsev, "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(vde, "vde", NULL, 61, 0x1c8, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(csite, "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* max rate ??? */
+PERIPH_CLK(la, "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71);
+PERIPH_CLK(owr, "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(nor, "nor", NULL, 42, 0x1d0, 127000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(mipi, "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | PERIPH_ON_APB); /* scales with voltage */
+PERIPH_CLK(i2c1, "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c2, "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c3, "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c4, "tegra-i2c.3", NULL, 103, 0x3c4, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(i2c5, "tegra-i2c.4", NULL, 47, 0x128, 26000000, mux_pllp_clkm, MUX | DIV_U16 | PERIPH_ON_APB);
+PERIPH_CLK(uarta, "tegra-uart.0", NULL, 6, 0x178, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartb, "tegra-uart.1", NULL, 7, 0x17c, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartc, "tegra-uart.2", NULL, 55, 0x1a0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uartd, "tegra-uart.3", NULL, 65, 0x1c0, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(uarte, "tegra-uart.4", NULL, 66, 0x1c4, 800000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB);
+PERIPH_CLK(vi, "tegra_camera", "vi", 20, 0x148, 425000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(3d, "3d", NULL, 24, 0x158, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(3d2, "3d2", NULL, 98, 0x3b0, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET);
+PERIPH_CLK(2d, "2d", NULL, 21, 0x15c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE);
+PERIPH_CLK(vi_sensor, "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET);
+PERIPH_CLK(epp, "epp", NULL, 19, 0x16c, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(mpe, "mpe", NULL, 60, 0x170, 520000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(host1x, "host1x", NULL, 28, 0x180, 260000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | DIV_U71_INT);
+PERIPH_CLK(cve, "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(tvo, "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(dtv, "dtv", NULL, 79, 0x1dc, 250000000, mux_clk_m, 0);
+PERIPH_CLK(hdmi, "hdmi", NULL, 51, 0x18c, 148500000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8 | DIV_U71);
+PERIPH_CLK(tvdac, "tvdac", NULL, 53, 0x194, 220000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71); /* requires min voltage */
+PERIPH_CLK(disp1, "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
+PERIPH_CLK(disp2, "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_pllm_plld_plla_pllc_plld2_clkm, MUX | MUX8);
+PERIPH_CLK(usbd, "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
+PERIPH_CLK(usb2, "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
+PERIPH_CLK(usb3, "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0); /* requires min voltage */
+PERIPH_CLK(dsia, "tegradc.0", "dsia", 48, 0, 500000000, mux_plld_out0, 0);
+PERIPH_CLK(csi, "tegra_camera", "csi", 52, 0, 102000000, mux_pllp_out3, 0);
+PERIPH_CLK(isp, "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0); /* same frequency as VI */
+PERIPH_CLK(csus, "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET);
+PERIPH_CLK(tsensor, "tegra-tsensor", NULL, 100, 0x3b8, 216000000, mux_pllp_pllc_clkm_clk32, MUX | DIV_U71);
+PERIPH_CLK(actmon, "actmon", NULL, 119, 0x3e8, 216000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71);
+PERIPH_CLK(extern1, "extern1", NULL, 120, 0x3ec, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern2, "extern2", NULL, 121, 0x3f0, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
+PERIPH_CLK(extern3, "extern3", NULL, 122, 0x3f4, 216000000, mux_plla_clk32_pllp_clkm_plle, MUX | MUX8 | DIV_U71);
+PERIPH_CLK(i2cslow, "i2cslow", NULL, 81, 0x3fc, 26000000, mux_pllp_pllc_clk32_clkm, MUX | DIV_U71 | PERIPH_ON_APB);
+PERIPH_CLK(pcie, "tegra-pcie", "pcie", 70, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(afi, "tegra-pcie", "afi", 72, 0, 250000000, mux_clk_m, 0);
+PERIPH_CLK(se, "se", NULL, 127, 0x42c, 520000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71 | DIV_U71_INT);
+
+static struct clk tegra_dsib;
+static struct clk_tegra tegra_dsib_hw = {
+ .hw = {
+ .clk = &tegra_dsib,
+ },
+ .lookup = {
+ .dev_id = "tegradc.1",
+ .con_id = "dsib",
+ },
+ .reg = 0xd0,
+ .flags = MUX | PLLD,
+ .max_rate = 500000000,
+ .u.periph = {
+ .clk_num = 82,
+ },
+ .reset = &tegra30_periph_clk_reset,
+};
+static struct clk tegra_dsib = {
+ .name = "dsib",
+ .ops = &tegra30_dsib_clk_ops,
+ .hw = &tegra_dsib_hw.hw,
+ .parent_names = mux_plld_out0_plld2_out0,
+ .parents = mux_plld_out0_plld2_out0_p,
+ .num_parents = ARRAY_SIZE(mux_plld_out0_plld2_out0),
+};
+
+struct clk *tegra_list_clks[] = {
+ &tegra_apbdma,
+ &tegra_rtc,
+ &tegra_kbc,
+ &tegra_kfuse,
+ &tegra_fuse,
+ &tegra_fuse_burn,
+ &tegra_apbif,
+ &tegra_i2s0,
+ &tegra_i2s1,
+ &tegra_i2s2,
+ &tegra_i2s3,
+ &tegra_i2s4,
+ &tegra_spdif_out,
+ &tegra_spdif_in,
+ &tegra_pwm,
+ &tegra_d_audio,
+ &tegra_dam0,
+ &tegra_dam1,
+ &tegra_dam2,
+ &tegra_hda,
+ &tegra_hda2codec_2x,
+ &tegra_hda2hdmi,
+ &tegra_sbc1,
+ &tegra_sbc2,
+ &tegra_sbc3,
+ &tegra_sbc4,
+ &tegra_sbc5,
+ &tegra_sbc6,
+ &tegra_sata_oob,
+ &tegra_sata,
+ &tegra_sata_cold,
+ &tegra_ndflash,
+ &tegra_ndspeed,
+ &tegra_vfir,
+ &tegra_sdmmc1,
+ &tegra_sdmmc2,
+ &tegra_sdmmc3,
+ &tegra_sdmmc4,
+ &tegra_vcp,
+ &tegra_bsea,
+ &tegra_bsev,
+ &tegra_vde,
+ &tegra_csite,
+ &tegra_la,
+ &tegra_owr,
+ &tegra_nor,
+ &tegra_mipi,
+ &tegra_i2c1,
+ &tegra_i2c2,
+ &tegra_i2c3,
+ &tegra_i2c4,
+ &tegra_i2c5,
+ &tegra_uarta,
+ &tegra_uartb,
+ &tegra_uartc,
+ &tegra_uartd,
+ &tegra_uarte,
+ &tegra_vi,
+ &tegra_3d,
+ &tegra_3d2,
+ &tegra_2d,
+ &tegra_vi_sensor,
+ &tegra_epp,
+ &tegra_mpe,
+ &tegra_host1x,
+ &tegra_cve,
+ &tegra_tvo,
+ &tegra_dtv,
+ &tegra_hdmi,
+ &tegra_tvdac,
+ &tegra_disp1,
+ &tegra_disp2,
+ &tegra_usbd,
+ &tegra_usb2,
+ &tegra_usb3,
+ &tegra_dsia,
+ &tegra_dsib,
+ &tegra_csi,
+ &tegra_isp,
+ &tegra_csus,
+ &tegra_tsensor,
+ &tegra_actmon,
+ &tegra_extern1,
+ &tegra_extern2,
+ &tegra_extern3,
+ &tegra_i2cslow,
+ &tegra_pcie,
+ &tegra_afi,
+ &tegra_se,
+};
+
+#define CLK_DUPLICATE(_name, _dev, _con) \
+ { \
+ .name = _name, \
+ .lookup = { \
+ .dev_id = _dev, \
+ .con_id = _con, \
+ }, \
+ }
+
+/* Some clocks may be used by different drivers depending on the board
+ * configuration. List those here to register them twice in the clock lookup
+ * table under two names.
+ */
+struct clk_duplicate tegra_clk_duplicates[] = {
+ CLK_DUPLICATE("uarta", "serial8250.0", NULL),
+ CLK_DUPLICATE("uartb", "serial8250.1", NULL),
+ CLK_DUPLICATE("uartc", "serial8250.2", NULL),
+ CLK_DUPLICATE("uartd", "serial8250.3", NULL),
+ CLK_DUPLICATE("uarte", "serial8250.4", NULL),
+ CLK_DUPLICATE("usbd", "utmip-pad", NULL),
+ CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL),
+ CLK_DUPLICATE("usbd", "tegra-otg", NULL),
+ CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"),
+ CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"),
+ CLK_DUPLICATE("dsib", "tegradc.0", "dsib"),
+ CLK_DUPLICATE("dsia", "tegradc.1", "dsia"),
+ CLK_DUPLICATE("bsev", "tegra-avp", "bsev"),
+ CLK_DUPLICATE("bsev", "nvavp", "bsev"),
+ CLK_DUPLICATE("vde", "tegra-aes", "vde"),
+ CLK_DUPLICATE("bsea", "tegra-aes", "bsea"),
+ CLK_DUPLICATE("bsea", "nvavp", "bsea"),
+ CLK_DUPLICATE("cml1", "tegra_sata_cml", NULL),
+ CLK_DUPLICATE("cml0", "tegra_pcie", "cml"),
+ CLK_DUPLICATE("pciex", "tegra_pcie", "pciex"),
+ CLK_DUPLICATE("i2c1", "tegra-i2c-slave.0", NULL),
+ CLK_DUPLICATE("i2c2", "tegra-i2c-slave.1", NULL),
+ CLK_DUPLICATE("i2c3", "tegra-i2c-slave.2", NULL),
+ CLK_DUPLICATE("i2c4", "tegra-i2c-slave.3", NULL),
+ CLK_DUPLICATE("i2c5", "tegra-i2c-slave.4", NULL),
+ CLK_DUPLICATE("sbc1", "spi_slave_tegra.0", NULL),
+ CLK_DUPLICATE("sbc2", "spi_slave_tegra.1", NULL),
+ CLK_DUPLICATE("sbc3", "spi_slave_tegra.2", NULL),
+ CLK_DUPLICATE("sbc4", "spi_slave_tegra.3", NULL),
+ CLK_DUPLICATE("sbc5", "spi_slave_tegra.4", NULL),
+ CLK_DUPLICATE("sbc6", "spi_slave_tegra.5", NULL),
+ CLK_DUPLICATE("twd", "smp_twd", NULL),
+ CLK_DUPLICATE("vcp", "nvavp", "vcp"),
+ CLK_DUPLICATE("i2s0", NULL, "i2s0"),
+ CLK_DUPLICATE("i2s1", NULL, "i2s1"),
+ CLK_DUPLICATE("i2s2", NULL, "i2s2"),
+ CLK_DUPLICATE("i2s3", NULL, "i2s3"),
+ CLK_DUPLICATE("i2s4", NULL, "i2s4"),
+ CLK_DUPLICATE("dam0", NULL, "dam0"),
+ CLK_DUPLICATE("dam1", NULL, "dam1"),
+ CLK_DUPLICATE("dam2", NULL, "dam2"),
+ CLK_DUPLICATE("spdif_in", NULL, "spdif_in"),
+};
+
+struct clk *tegra_ptr_clks[] = {
+ &tegra_clk_32k,
+ &tegra_clk_m,
+ &tegra_clk_m_div2,
+ &tegra_clk_m_div4,
+ &tegra_pll_ref,
+ &tegra_pll_m,
+ &tegra_pll_m_out1,
+ &tegra_pll_c,
+ &tegra_pll_c_out1,
+ &tegra_pll_p,
+ &tegra_pll_p_out1,
+ &tegra_pll_p_out2,
+ &tegra_pll_p_out3,
+ &tegra_pll_p_out4,
+ &tegra_pll_a,
+ &tegra_pll_a_out0,
+ &tegra_pll_d,
+ &tegra_pll_d_out0,
+ &tegra_pll_d2,
+ &tegra_pll_d2_out0,
+ &tegra_pll_u,
+ &tegra_pll_x,
+ &tegra_pll_x_out0,
+ &tegra_pll_e,
+ &tegra_clk_cclk_g,
+ &tegra_cml0,
+ &tegra_cml1,
+ &tegra_pciex,
+ &tegra_clk_sclk,
+ &tegra_clk_blink,
+ &tegra30_clk_twd,
+};
+
+static void tegra30_init_one_clock(struct clk *c)
+{
+ struct clk_tegra *clk = to_clk_tegra(c->hw);
+ __clk_init(NULL, c);
+ INIT_LIST_HEAD(&clk->shared_bus_list);
+ if (!clk->lookup.dev_id && !clk->lookup.con_id)
+ clk->lookup.con_id = c->name;
+ clk->lookup.clk = c;
+ clkdev_add(&clk->lookup);
+ tegra_clk_add(c);
+}
+
+void __init tegra30_init_clocks(void)
+{
+ int i;
+ struct clk *c;
+
+ for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++)
+ tegra30_init_one_clock(tegra_ptr_clks[i]);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++)
+ tegra30_init_one_clock(tegra_list_clks[i]);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) {
+ c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name);
+ if (!c) {
+ pr_err("%s: Unknown duplicate clock %s\n", __func__,
+ tegra_clk_duplicates[i].name);
+ continue;
+ }
+
+ tegra_clk_duplicates[i].lookup.clk = c;
+ clkdev_add(&tegra_clk_duplicates[i].lookup);
+ }
+
+ for (i = 0; i < ARRAY_SIZE(tegra_sync_source_list); i++)
+ tegra30_init_one_clock(tegra_sync_source_list[i]);
+ for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_list); i++)
+ tegra30_init_one_clock(tegra_clk_audio_list[i]);
+ for (i = 0; i < ARRAY_SIZE(tegra_clk_audio_2x_list); i++)
+ tegra30_init_one_clock(tegra_clk_audio_2x_list[i]);
+
+ for (i = 0; i < ARRAY_SIZE(tegra_clk_out_list); i++)
+ tegra30_init_one_clock(tegra_clk_out_list[i]);
+
+ tegra30_cpu_car_ops_init();
+}
diff --git a/arch/arm/mach-tegra/tegra_cpu_car.h b/arch/arm/mach-tegra/tegra_cpu_car.h
new file mode 100644
index 0000000..30d063a
--- /dev/null
+++ b/arch/arm/mach-tegra/tegra_cpu_car.h
@@ -0,0 +1,87 @@
+/*
+ * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __MACH_TEGRA_CPU_CAR_H
+#define __MACH_TEGRA_CPU_CAR_H
+
+/*
+ * Tegra CPU clock and reset control ops
+ *
+ * wait_for_reset:
+ * keep waiting until the CPU in reset state
+ * put_in_reset:
+ * put the CPU in reset state
+ * out_of_reset:
+ * release the CPU from reset state
+ * enable_clock:
+ * CPU clock un-gate
+ * disable_clock:
+ * CPU clock gate
+ */
+struct tegra_cpu_car_ops {
+ void (*wait_for_reset)(u32 cpu);
+ void (*put_in_reset)(u32 cpu);
+ void (*out_of_reset)(u32 cpu);
+ void (*enable_clock)(u32 cpu);
+ void (*disable_clock)(u32 cpu);
+};
+
+extern struct tegra_cpu_car_ops *tegra_cpu_car_ops;
+
+static inline void tegra_wait_cpu_in_reset(u32 cpu)
+{
+ if (WARN_ON(!tegra_cpu_car_ops->wait_for_reset))
+ return;
+
+ tegra_cpu_car_ops->wait_for_reset(cpu);
+}
+
+static inline void tegra_put_cpu_in_reset(u32 cpu)
+{
+ if (WARN_ON(!tegra_cpu_car_ops->put_in_reset))
+ return;
+
+ tegra_cpu_car_ops->put_in_reset(cpu);
+}
+
+static inline void tegra_cpu_out_of_reset(u32 cpu)
+{
+ if (WARN_ON(!tegra_cpu_car_ops->out_of_reset))
+ return;
+
+ tegra_cpu_car_ops->out_of_reset(cpu);
+}
+
+static inline void tegra_enable_cpu_clock(u32 cpu)
+{
+ if (WARN_ON(!tegra_cpu_car_ops->enable_clock))
+ return;
+
+ tegra_cpu_car_ops->enable_clock(cpu);
+}
+
+static inline void tegra_disable_cpu_clock(u32 cpu)
+{
+ if (WARN_ON(!tegra_cpu_car_ops->disable_clock))
+ return;
+
+ tegra_cpu_car_ops->disable_clock(cpu);
+}
+
+void tegra20_cpu_car_ops_init(void);
+void tegra30_cpu_car_ops_init(void);
+
+#endif /* __MACH_TEGRA_CPU_CAR_H */
diff --git a/arch/arm/mach-ux500/cache-l2x0.c b/arch/arm/mach-ux500/cache-l2x0.c
index dc12394..75d5b51 100644
--- a/arch/arm/mach-ux500/cache-l2x0.c
+++ b/arch/arm/mach-ux500/cache-l2x0.c
@@ -38,7 +38,7 @@
{
u32 aux_val = 0x3e000000;
- if (cpu_is_u8500_family())
+ if (cpu_is_u8500_family() || cpu_is_ux540_family())
l2x0_base = __io_address(U8500_L2CC_BASE);
else
ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/clock.c b/arch/arm/mach-ux500/clock.c
index 8d73b06..bc5a516 100644
--- a/arch/arm/mach-ux500/clock.c
+++ b/arch/arm/mach-ux500/clock.c
@@ -149,7 +149,7 @@
unsigned long mturate;
unsigned long retclk;
- if (cpu_is_u8500_family())
+ if (cpu_is_u8500_family() || cpu_is_ux540_family())
addr = __io_address(U8500_PRCMU_BASE);
else
ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index db3c52d..8169f2c 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -19,7 +19,6 @@
#include <linux/mfd/abx500/ab8500.h>
#include <asm/mach/map.h>
-#include <asm/pmu.h>
#include <plat/gpio-nomadik.h>
#include <mach/hardware.h>
#include <mach/setup.h>
@@ -80,7 +79,7 @@
iotable_init(u8500_common_io_desc, ARRAY_SIZE(u8500_common_io_desc));
- if (cpu_is_u9540())
+ if (cpu_is_ux540_family())
iotable_init(u9540_io_desc, ARRAY_SIZE(u9540_io_desc));
else
iotable_init(u8500_io_desc, ARRAY_SIZE(u8500_io_desc));
@@ -122,7 +121,7 @@
static struct platform_device db8500_pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(db8500_pmu_resources),
.resource = db8500_pmu_resources,
.dev.platform_data = &db8500_pmu_platdata,
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index e2360e7..4b0a9b3 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -51,7 +51,7 @@
void __iomem *dist_base;
void __iomem *cpu_base;
- if (cpu_is_u8500_family()) {
+ if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
dist_base = __io_address(U8500_GIC_DIST_BASE);
cpu_base = __io_address(U8500_GIC_CPU_BASE);
} else
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index c6e2db9..9c42642 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -41,43 +41,29 @@
return dbx500_partnumber() == 0x8500;
}
+static inline bool __attribute_const__ cpu_is_u8520(void)
+{
+ return dbx500_partnumber() == 0x8520;
+}
+
+static inline bool cpu_is_u8500_family(void)
+{
+ return cpu_is_u8500() || cpu_is_u8520();
+}
+
static inline bool __attribute_const__ cpu_is_u9540(void)
{
return dbx500_partnumber() == 0x9540;
}
-static inline bool cpu_is_u8500_family(void)
+static inline bool __attribute_const__ cpu_is_u8540(void)
{
- return cpu_is_u8500() || cpu_is_u9540();
+ return dbx500_partnumber() == 0x8540;
}
-static inline bool __attribute_const__ cpu_is_u5500(void)
+static inline bool cpu_is_ux540_family(void)
{
- return dbx500_partnumber() == 0x5500;
-}
-
-/*
- * 5500 revisions
- */
-
-static inline bool __attribute_const__ cpu_is_u5500v1(void)
-{
- return cpu_is_u5500() && (dbx500_revision() & 0xf0) == 0xA0;
-}
-
-static inline bool __attribute_const__ cpu_is_u5500v2(void)
-{
- return (dbx500_id.revision & 0xf0) == 0xB0;
-}
-
-static inline bool __attribute_const__ cpu_is_u5500v20(void)
-{
- return cpu_is_u5500() && ((dbx500_revision() & 0xf0) == 0xB0);
-}
-
-static inline bool __attribute_const__ cpu_is_u5500v21(void)
-{
- return cpu_is_u5500() && (dbx500_revision() == 0xB1);
+ return cpu_is_u9540() || cpu_is_u8540();
}
/*
@@ -119,14 +105,14 @@
return cpu_is_u8500() && (dbx500_revision() == 0xB1);
}
+static inline bool cpu_is_u8500v22(void)
+{
+ return cpu_is_u8500() && (dbx500_revision() == 0xB2);
+}
+
static inline bool cpu_is_u8500v20_or_later(void)
{
- /*
- * U9540 has so much in common with U8500 that is is considered a
- * U8500 variant.
- */
- return cpu_is_u9540() ||
- (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
+ return (cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11());
}
static inline bool ux500_is_svp(void)
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index da1d5ad..a5dda68444 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -48,7 +48,7 @@
static void __iomem *scu_base_addr(void)
{
- if (cpu_is_u8500_family())
+ if (cpu_is_u8500_family() || cpu_is_ux540_family())
return __io_address(U8500_SCU_BASE);
else
ux500_unknown_soc();
@@ -118,7 +118,7 @@
{
void __iomem *backupram;
- if (cpu_is_u8500_family())
+ if (cpu_is_u8500_family() || cpu_is_ux540_family())
backupram = __io_address(U8500_BACKUPRAM0_BASE);
else
ux500_unknown_soc();
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index 66e7f00..6f39731 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -54,7 +54,7 @@
void __iomem *tmp_base;
struct device_node *np;
- if (cpu_is_u8500_family()) {
+ if (cpu_is_u8500_family() || cpu_is_ux540_family()) {
mtu_timer_base = __io_address(U8500_MTU0_BASE);
prcmu_timer_base = __io_address(U8500_PRCMU_TIMER_4_BASE);
} else {
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index 61c4924..e4073a6 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -13,7 +13,6 @@
#include <asm/hardware/arm_timer.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/hardware/gic.h>
-#include <asm/pmu.h>
#include <asm/smp_scu.h>
#include <asm/smp_twd.h>
@@ -144,7 +143,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(pmu_resources),
.resource = pmu_resources,
};
diff --git a/arch/arm/plat-iop/pmu.c b/arch/arm/plat-iop/pmu.c
index a2024b8..ad9f974 100644
--- a/arch/arm/plat-iop/pmu.c
+++ b/arch/arm/plat-iop/pmu.c
@@ -9,7 +9,6 @@
*/
#include <linux/platform_device.h>
-#include <asm/pmu.h>
#include <mach/irqs.h>
static struct resource pmu_resource = {
@@ -26,7 +25,7 @@
static struct platform_device pmu_device = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.resource = &pmu_resource,
.num_resources = 1,
};
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx3.h b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
index d8b65b5..f79f78a 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx3.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx3.h
@@ -512,12 +512,16 @@
#define MX31_PIN_CSPI3_SPI_RDY__CTS3 IOMUX_MODE(MX31_PIN_CSPI3_SPI_RDY, IOMUX_CONFIG_ALT1)
#define MX31_PIN_CTS1__CTS1 IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_RTS1__RTS1 IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RTS1__SFS IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_TXD1__TXD1 IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_TXD1__SCK IOMUX_MODE(MX31_PIN_TXD1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_RXD1__RXD1 IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_RXD1__STXDA IOMUX_MODE(MX31_PIN_RXD1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_DCD_DCE1__DCD_DCE1 IOMUX_MODE(MX31_PIN_DCD_DCE1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_RI_DCE1__RI_DCE1 IOMUX_MODE(MX31_PIN_RI_DCE1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_DSR_DCE1__DSR_DCE1 IOMUX_MODE(MX31_PIN_DSR_DCE1, IOMUX_CONFIG_FUNC)
#define MX31_PIN_DTR_DCE1__DTR_DCE1 IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_DTR_DCE1__SRXDA IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_ALT2)
#define MX31_PIN_CTS2__CTS2 IOMUX_MODE(MX31_PIN_CTS2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_RTS2__RTS2 IOMUX_MODE(MX31_PIN_RTS2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_TXD2__TXD2 IOMUX_MODE(MX31_PIN_TXD2, IOMUX_CONFIG_FUNC)
@@ -721,6 +725,7 @@
#define MX31_PIN_KEY_ROW2_KEY_ROW2 IOMUX_MODE(MX31_PIN_KEY_ROW2, IOMUX_CONFIG_FUNC)
#define MX31_PIN_KEY_ROW3_KEY_ROW3 IOMUX_MODE(MX31_PIN_KEY_ROW3, IOMUX_CONFIG_FUNC)
#define MX31_PIN_KEY_ROW4_KEY_ROW4 IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_FUNC)
+#define MX31_PIN_KEY_ROW4_GPIO IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO)
#define MX31_PIN_KEY_ROW5_KEY_ROW5 IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_FUNC)
#define MX31_PIN_KEY_ROW6_KEY_ROW6 IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_FUNC)
#define MX31_PIN_KEY_ROW7_KEY_ROW7 IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_FUNC)
diff --git a/arch/arm/plat-mxc/ssi-fiq.S b/arch/arm/plat-mxc/ssi-fiq.S
index 8397a2d..a8b93c5 100644
--- a/arch/arm/plat-mxc/ssi-fiq.S
+++ b/arch/arm/plat-mxc/ssi-fiq.S
@@ -34,91 +34,98 @@
.global imx_ssi_fiq_rx_buffer
.global imx_ssi_fiq_tx_buffer
+/*
+ * imx_ssi_fiq_start is _intentionally_ not marked as a function symbol
+ * using ENDPROC(). imx_ssi_fiq_start and imx_ssi_fiq_end are used to
+ * mark the function body so that it can be copied to the FIQ vector in
+ * the vectors page. imx_ssi_fiq_start should only be called as the result
+ * of an FIQ: calling it directly will not work.
+ */
imx_ssi_fiq_start:
- ldr r12, imx_ssi_fiq_base
+ ldr r12, .L_imx_ssi_fiq_base
/* TX */
- ldr r11, imx_ssi_fiq_tx_buffer
+ ldr r13, .L_imx_ssi_fiq_tx_buffer
/* shall we send? */
- ldr r13, [r12, #SSI_SIER]
- tst r13, #SSI_SIER_TFE0_EN
+ ldr r11, [r12, #SSI_SIER]
+ tst r11, #SSI_SIER_TFE0_EN
beq 1f
/* TX FIFO empty? */
- ldr r13, [r12, #SSI_SISR]
- tst r13, #SSI_SISR_TFE0
+ ldr r11, [r12, #SSI_SISR]
+ tst r11, #SSI_SISR_TFE0
beq 1f
mov r10, #0x10000
sub r10, #1
and r10, r10, r8 /* r10: current buffer offset */
- add r11, r11, r10
+ add r13, r13, r10
- ldrh r13, [r11]
- strh r13, [r12, #SSI_STX0]
+ ldrh r11, [r13]
+ strh r11, [r12, #SSI_STX0]
- ldrh r13, [r11, #2]
- strh r13, [r12, #SSI_STX0]
+ ldrh r11, [r13, #2]
+ strh r11, [r12, #SSI_STX0]
- ldrh r13, [r11, #4]
- strh r13, [r12, #SSI_STX0]
+ ldrh r11, [r13, #4]
+ strh r11, [r12, #SSI_STX0]
- ldrh r13, [r11, #6]
- strh r13, [r12, #SSI_STX0]
+ ldrh r11, [r13, #6]
+ strh r11, [r12, #SSI_STX0]
add r10, #8
- lsr r13, r8, #16 /* r13: buffer size */
- cmp r10, r13
- lslgt r8, r13, #16
+ lsr r11, r8, #16 /* r11: buffer size */
+ cmp r10, r11
+ lslgt r8, r11, #16
addle r8, #8
1:
/* RX */
/* shall we receive? */
- ldr r13, [r12, #SSI_SIER]
- tst r13, #SSI_SIER_RFF0_EN
+ ldr r11, [r12, #SSI_SIER]
+ tst r11, #SSI_SIER_RFF0_EN
beq 1f
/* RX FIFO full? */
- ldr r13, [r12, #SSI_SISR]
- tst r13, #SSI_SISR_RFF0
+ ldr r11, [r12, #SSI_SISR]
+ tst r11, #SSI_SISR_RFF0
beq 1f
- ldr r11, imx_ssi_fiq_rx_buffer
+ ldr r13, .L_imx_ssi_fiq_rx_buffer
mov r10, #0x10000
sub r10, #1
and r10, r10, r9 /* r10: current buffer offset */
- add r11, r11, r10
+ add r13, r13, r10
- ldr r13, [r12, #SSI_SACNT]
- tst r13, #SSI_SACNT_AC97EN
+ ldr r11, [r12, #SSI_SACNT]
+ tst r11, #SSI_SACNT_AC97EN
- ldr r13, [r12, #SSI_SRX0]
- strh r13, [r11]
+ ldr r11, [r12, #SSI_SRX0]
+ strh r11, [r13]
- ldr r13, [r12, #SSI_SRX0]
- strh r13, [r11, #2]
+ ldr r11, [r12, #SSI_SRX0]
+ strh r11, [r13, #2]
/* dummy read to skip slot 12 */
- ldrne r13, [r12, #SSI_SRX0]
+ ldrne r11, [r12, #SSI_SRX0]
- ldr r13, [r12, #SSI_SRX0]
- strh r13, [r11, #4]
+ ldr r11, [r12, #SSI_SRX0]
+ strh r11, [r13, #4]
- ldr r13, [r12, #SSI_SRX0]
- strh r13, [r11, #6]
+ ldr r11, [r12, #SSI_SRX0]
+ strh r11, [r13, #6]
/* dummy read to skip slot 12 */
- ldrne r13, [r12, #SSI_SRX0]
+ ldrne r11, [r12, #SSI_SRX0]
add r10, #8
- lsr r13, r9, #16 /* r13: buffer size */
- cmp r10, r13
- lslgt r9, r13, #16
+ lsr r11, r9, #16 /* r11: buffer size */
+ cmp r10, r11
+ lslgt r9, r11, #16
addle r9, #8
1:
@@ -126,11 +133,15 @@
subs pc, lr, #4
.align
+.L_imx_ssi_fiq_base:
imx_ssi_fiq_base:
.word 0x0
+.L_imx_ssi_fiq_rx_buffer:
imx_ssi_fiq_rx_buffer:
.word 0x0
+.L_imx_ssi_fiq_tx_buffer:
imx_ssi_fiq_tx_buffer:
.word 0x0
+.L_imx_ssi_fiq_end:
imx_ssi_fiq_end:
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index 4327b2c..e7259c0 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -60,6 +60,7 @@
* @_dev_wakeup_lat_limit: dev wakeup latency limit in nsec - set by OMAP PM
* @_state: one of OMAP_DEVICE_STATE_* (see above)
* @flags: device flags
+ * @_driver_status: one of BUS_NOTIFY_*_DRIVER from <linux/device.h>
*
* Integrates omap_hwmod data into Linux platform_device.
*
@@ -73,6 +74,7 @@
struct omap_device_pm_latency *pm_lats;
u32 dev_wakeup_lat;
u32 _dev_wakeup_lat_limit;
+ unsigned long _driver_status;
u8 pm_lats_cnt;
s8 pm_lat_level;
u8 hwmods_cnt;
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index c490240..0f51982 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -385,17 +385,21 @@
unsigned long event, void *dev)
{
struct platform_device *pdev = to_platform_device(dev);
+ struct omap_device *od;
switch (event) {
- case BUS_NOTIFY_ADD_DEVICE:
- if (pdev->dev.of_node)
- omap_device_build_from_dt(pdev);
- break;
-
case BUS_NOTIFY_DEL_DEVICE:
if (pdev->archdata.od)
omap_device_delete(pdev->archdata.od);
break;
+ case BUS_NOTIFY_ADD_DEVICE:
+ if (pdev->dev.of_node)
+ omap_device_build_from_dt(pdev);
+ /* fall through */
+ default:
+ od = to_omap_device(pdev);
+ if (od)
+ od->_driver_status = event;
}
return NOTIFY_DONE;
@@ -752,6 +756,10 @@
struct omap_device *od = to_omap_device(pdev);
int ret;
+ /* Don't attempt late suspend on a driver that is not bound */
+ if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER)
+ return 0;
+
ret = pm_generic_suspend_noirq(dev);
if (!ret && !pm_runtime_status_suspended(dev)) {
@@ -1125,3 +1133,41 @@
return 0;
}
core_initcall(omap_device_init);
+
+/**
+ * omap_device_late_idle - idle devices without drivers
+ * @dev: struct device * associated with omap_device
+ * @data: unused
+ *
+ * Check the driver bound status of this device, and idle it
+ * if there is no driver attached.
+ */
+static int __init omap_device_late_idle(struct device *dev, void *data)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct omap_device *od = to_omap_device(pdev);
+
+ if (!od)
+ return 0;
+
+ /*
+ * If omap_device state is enabled, but has no driver bound,
+ * idle it.
+ */
+ if (od->_driver_status != BUS_NOTIFY_BOUND_DRIVER) {
+ if (od->_state == OMAP_DEVICE_STATE_ENABLED) {
+ dev_warn(dev, "%s: enabled but no driver. Idling\n",
+ __func__);
+ omap_device_idle(pdev);
+ }
+ }
+
+ return 0;
+}
+
+static int __init omap_device_late_init(void)
+{
+ bus_for_each_dev(&platform_bus_type, NULL, NULL, omap_device_late_idle);
+ return 0;
+}
+late_initcall(omap_device_late_init);
diff --git a/arch/arm/plat-samsung/devs.c b/arch/arm/plat-samsung/devs.c
index fc49f3d..6ff45d5 100644
--- a/arch/arm/plat-samsung/devs.c
+++ b/arch/arm/plat-samsung/devs.c
@@ -35,7 +35,6 @@
#include <media/s5p_hdmi.h>
#include <asm/irq.h>
-#include <asm/pmu.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
#include <asm/mach/irq.h>
@@ -1132,7 +1131,7 @@
static struct platform_device s5p_device_pmu = {
.name = "arm-pmu",
- .id = ARM_PMU_DEVICE_CPU,
+ .id = -1,
.num_resources = ARRAY_SIZE(s5p_pmu_resource),
.resource = s5p_pmu_resource,
};