MIPS: Cavium: Add EDAC support.
Drivers for EDAC on Cavium. Supported subsystems are:
o CPU primary caches. These are parity protected only, so only error
reporting.
o Second level cache - ECC protected, provides SECDED.
o Memory: ECC / SECDEC if used with suitable DRAM modules. The driver will
will only initialize if ECC is enabled on a system so is safe to run on
non-ECC memory.
o PCI: Parity error reporting
Since it is very hard to test this sort of code the implementation is very
conservative and uses polling where possible for now.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Reviewed-by: Borislav Petkov <borislav.petkov@amd.com>
diff --git a/arch/mips/pci/pci-octeon.c b/arch/mips/pci/pci-octeon.c
index 4b0c347..8eb2ee3 100644
--- a/arch/mips/pci/pci-octeon.c
+++ b/arch/mips/pci/pci-octeon.c
@@ -11,6 +11,7 @@
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/delay.h>
+#include <linux/platform_device.h>
#include <linux/swiotlb.h>
#include <asm/time.h>
@@ -704,6 +705,9 @@
*/
cvmx_write_csr(CVMX_NPI_PCI_INT_SUM2, -1);
+ if (IS_ERR(platform_device_register_simple("co_pci_edac", 0, NULL, 0)))
+ pr_err("Registation of co_pci_edac failed!\n");
+
octeon_pci_dma_init();
return 0;