| commit | f892f24b37345181b9bc7748ed4a8e927cdb6e06 | [log] [tgz] |
|---|---|---|
| author | Sean Paul <seanpaul@chromium.org> | Wed Oct 01 12:40:41 2014 -0400 |
| committer | Peter De Schrijver <pdeschrijver@nvidia.com> | Mon Feb 02 15:46:34 2015 +0200 |
| tree | 75c2f3ba5b9dde77bc4487dad5ad24f8bc2e941b | |
| parent | 18abd16376ad88ed3995c63ddae47be78bd56abe [diff] |
clk: tegra124: Add init data for dsi lp clocks Set the parent of the dsi lp clocks to pll_p and the rate to 68MHz. The default parent is clk_m and rate is 12MHz, this is too slow to receive data from the peripheral. Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz will suffice. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>