tree b1a20998343a7dc9c17f2dad91bffdf30849ab96
parent be75de25251f7cf3e399ca1f584716a95510d24a
author Max Filippov <jcmvbkbc@gmail.com> 1533964882 -0700
committer Max Filippov <jcmvbkbc@gmail.com> 1534216081 -0700

xtensa: increase ranges in ___invalidate_{i,d}cache_all

Cache invalidation macros use cache line size to iterate over
invalidated cache lines, assuming that all cache ways are invalidated by
single instruction, but xtensa ISA recommends to not assume that for
future compatibility:
  In some implementations all ways at index Addry-1..z are invalidated
  regardless of the specified way, but for future compatibility this
  behavior should not be assumed.

Iterate over all cache ways in ___invalidate_icache_all and
___invalidate_dcache_all.

Cc: stable@vger.kernel.org
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>