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gerrit-public.fairphone.software / kernel / msm-5.4 / 0d35bc78ecb74e4a9bf20609d6983aeef2102a56 / . / drivers / gpu / drm / amd / amdgpu / soc15_common.h
blob: def865067edd2b2cadc820824442b0006b057b2c [file] [log] [blame]
Ken Wang8e3153b2017-03-06 12:41:22 -0500[diff] [blame]1/*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef __SOC15_COMMON_H__
25#define __SOC15_COMMON_H__
26
Tom St Denisb1bb8c02017-04-07 07:53:31 -0400[diff] [blame]27/* Register Access Macros */
Shaoyun Liucd292532017-11-29 13:51:32 -0500[diff] [blame]28#define SOC15_REG_OFFSET(ip, inst, reg) (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
Ken Wang8e3153b2017-03-06 12:41:22 -0500[diff] [blame]29
Tom St Denisb1bb8c02017-04-07 07:53:31 -0400[diff] [blame]30#define WREG32_FIELD15(ip, idx, reg, field, val) \
Shaoyun Liub4661072017-11-27 13:20:38 -0500[diff] [blame]31 WREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg, \
32 (RREG32(adev->reg_offset[ip##_HWIP][idx][mm##reg##_BASE_IDX] + mm##reg) \
33 & ~REG_FIELD_MASK(reg, field)) | (val) << REG_FIELD_SHIFT(reg, field))
Tom St Denisb1bb8c02017-04-07 07:53:31 -0400[diff] [blame]34
35#define RREG32_SOC15(ip, inst, reg) \
Shaoyun Liub4661072017-11-27 13:20:38 -0500[diff] [blame]36 RREG32(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
Tom St Denisb1bb8c02017-04-07 07:53:31 -0400[diff] [blame]37
Tom St Denis496828e2017-06-12 12:05:42 -0400[diff] [blame]38#define RREG32_SOC15_OFFSET(ip, inst, reg, offset) \
Shaoyun Liub4661072017-11-27 13:20:38 -0500[diff] [blame]39 RREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset)
Tom St Denis496828e2017-06-12 12:05:42 -0400[diff] [blame]40
Tom St Denisb1bb8c02017-04-07 07:53:31 -0400[diff] [blame]41#define WREG32_SOC15(ip, inst, reg, value) \
Shaoyun Liub4661072017-11-27 13:20:38 -0500[diff] [blame]42 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
Tom St Denisb1bb8c02017-04-07 07:53:31 -0400[diff] [blame]43
Shaoyun Liuc7085352017-07-05 10:53:55 -0400[diff] [blame]44#define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
Shaoyun Liub4661072017-11-27 13:20:38 -0500[diff] [blame]45 WREG32_NO_KIQ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg), value)
Shaoyun Liuc7085352017-07-05 10:53:55 -0400[diff] [blame]46
Tom St Denis496828e2017-06-12 12:05:42 -0400[diff] [blame]47#define WREG32_SOC15_OFFSET(ip, inst, reg, offset, value) \
Shaoyun Liub4661072017-11-27 13:20:38 -0500[diff] [blame]48 WREG32((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) + offset, value)
Tom St Denis496828e2017-06-12 12:05:42 -0400[diff] [blame]49
Ken Wang8e3153b2017-03-06 12:41:22 -0500[diff] [blame]50#endif
51
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