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gerrit-public.fairphone.software / kernel / msm-5.4 / 37dab4112d7b53c3574426ef7bdd92a78d32ac3e / . / drivers / infiniband / hw / nes / nes_hw.h
blob: 6a0f94cc9f0cd5854f3b7addc491907dbbfccf39 [file] [log] [blame]
Glenn Streiff3c2d7742008-02-04 20:20:45 -0800[diff] [blame]1/*
2* Copyright (c) 2006 - 2008 NetEffect, Inc. All rights reserved.
3*
4* This software is available to you under a choice of one of two
5* licenses. You may choose to be licensed under the terms of the GNU
6* General Public License (GPL) Version 2, available from the file
7* COPYING in the main directory of this source tree, or the
8* OpenIB.org BSD license below:
9*
10* Redistribution and use in source and binary forms, with or
11* without modification, are permitted provided that the following
12* conditions are met:
13*
14* - Redistributions of source code must retain the above
15* copyright notice, this list of conditions and the following
16* disclaimer.
17*
18* - Redistributions in binary form must reproduce the above
19* copyright notice, this list of conditions and the following
20* disclaimer in the documentation and/or other materials
21* provided with the distribution.
22*
23* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30* SOFTWARE.
31*/
32
33#ifndef __NES_HW_H
34#define __NES_HW_H
35
Faisal Latif37dab412008-04-29 13:46:54 -0700[diff] [blame^]36#include <linux/inet_lro.h>
37
Glenn Streiff3c2d7742008-02-04 20:20:45 -0800[diff] [blame]38#define NES_PHY_TYPE_1G 2
39#define NES_PHY_TYPE_IRIS 3
40#define NES_PHY_TYPE_PUMA_10G 6
41
42#define NES_MULTICAST_PF_MAX 8
43
44enum pci_regs {
45 NES_INT_STAT = 0x0000,
46 NES_INT_MASK = 0x0004,
47 NES_INT_PENDING = 0x0008,
48 NES_INTF_INT_STAT = 0x000C,
49 NES_INTF_INT_MASK = 0x0010,
50 NES_TIMER_STAT = 0x0014,
51 NES_PERIODIC_CONTROL = 0x0018,
52 NES_ONE_SHOT_CONTROL = 0x001C,
53 NES_EEPROM_COMMAND = 0x0020,
54 NES_EEPROM_DATA = 0x0024,
55 NES_FLASH_COMMAND = 0x0028,
56 NES_FLASH_DATA = 0x002C,
57 NES_SOFTWARE_RESET = 0x0030,
58 NES_CQ_ACK = 0x0034,
59 NES_WQE_ALLOC = 0x0040,
60 NES_CQE_ALLOC = 0x0044,
61};
62
63enum indexed_regs {
64 NES_IDX_CREATE_CQP_LOW = 0x0000,
65 NES_IDX_CREATE_CQP_HIGH = 0x0004,
66 NES_IDX_QP_CONTROL = 0x0040,
67 NES_IDX_FLM_CONTROL = 0x0080,
68 NES_IDX_INT_CPU_STATUS = 0x00a0,
69 NES_IDX_GPIO_CONTROL = 0x00f0,
70 NES_IDX_GPIO_DATA = 0x00f4,
71 NES_IDX_TCP_CONFIG0 = 0x01e4,
72 NES_IDX_TCP_TIMER_CONFIG = 0x01ec,
73 NES_IDX_TCP_NOW = 0x01f0,
74 NES_IDX_QP_MAX_CFG_SIZES = 0x0200,
75 NES_IDX_QP_CTX_SIZE = 0x0218,
76 NES_IDX_TCP_TIMER_SIZE0 = 0x0238,
77 NES_IDX_TCP_TIMER_SIZE1 = 0x0240,
78 NES_IDX_ARP_CACHE_SIZE = 0x0258,
79 NES_IDX_CQ_CTX_SIZE = 0x0260,
80 NES_IDX_MRT_SIZE = 0x0278,
81 NES_IDX_PBL_REGION_SIZE = 0x0280,
82 NES_IDX_IRRQ_COUNT = 0x02b0,
83 NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x02f0,
84 NES_IDX_RX_WINDOW_BUFFER_SIZE = 0x0300,
85 NES_IDX_DST_IP_ADDR = 0x0400,
86 NES_IDX_PCIX_DIAG = 0x08e8,
87 NES_IDX_MPP_DEBUG = 0x0a00,
88 NES_IDX_PORT_RX_DISCARDS = 0x0a30,
89 NES_IDX_PORT_TX_DISCARDS = 0x0a34,
90 NES_IDX_MPP_LB_DEBUG = 0x0b00,
91 NES_IDX_DENALI_CTL_22 = 0x1058,
92 NES_IDX_MAC_TX_CONTROL = 0x2000,
93 NES_IDX_MAC_TX_CONFIG = 0x2004,
94 NES_IDX_MAC_TX_PAUSE_QUANTA = 0x2008,
95 NES_IDX_MAC_RX_CONTROL = 0x200c,
96 NES_IDX_MAC_RX_CONFIG = 0x2010,
97 NES_IDX_MAC_EXACT_MATCH_BOTTOM = 0x201c,
98 NES_IDX_MAC_MDIO_CONTROL = 0x2084,
99 NES_IDX_MAC_TX_OCTETS_LOW = 0x2100,
100 NES_IDX_MAC_TX_OCTETS_HIGH = 0x2104,
101 NES_IDX_MAC_TX_FRAMES_LOW = 0x2108,
102 NES_IDX_MAC_TX_FRAMES_HIGH = 0x210c,
103 NES_IDX_MAC_TX_PAUSE_FRAMES = 0x2118,
104 NES_IDX_MAC_TX_ERRORS = 0x2138,
105 NES_IDX_MAC_RX_OCTETS_LOW = 0x213c,
106 NES_IDX_MAC_RX_OCTETS_HIGH = 0x2140,
107 NES_IDX_MAC_RX_FRAMES_LOW = 0x2144,
108 NES_IDX_MAC_RX_FRAMES_HIGH = 0x2148,
109 NES_IDX_MAC_RX_BC_FRAMES_LOW = 0x214c,
110 NES_IDX_MAC_RX_MC_FRAMES_HIGH = 0x2150,
111 NES_IDX_MAC_RX_PAUSE_FRAMES = 0x2154,
112 NES_IDX_MAC_RX_SHORT_FRAMES = 0x2174,
113 NES_IDX_MAC_RX_OVERSIZED_FRAMES = 0x2178,
114 NES_IDX_MAC_RX_JABBER_FRAMES = 0x217c,
115 NES_IDX_MAC_RX_CRC_ERR_FRAMES = 0x2180,
116 NES_IDX_MAC_RX_LENGTH_ERR_FRAMES = 0x2184,
117 NES_IDX_MAC_RX_SYMBOL_ERR_FRAMES = 0x2188,
118 NES_IDX_MAC_INT_STATUS = 0x21f0,
119 NES_IDX_MAC_INT_MASK = 0x21f4,
120 NES_IDX_PHY_PCS_CONTROL_STATUS0 = 0x2800,
121 NES_IDX_PHY_PCS_CONTROL_STATUS1 = 0x2a00,
122 NES_IDX_ETH_SERDES_COMMON_CONTROL0 = 0x2808,
123 NES_IDX_ETH_SERDES_COMMON_CONTROL1 = 0x2a08,
124 NES_IDX_ETH_SERDES_COMMON_STATUS0 = 0x280c,
125 NES_IDX_ETH_SERDES_COMMON_STATUS1 = 0x2a0c,
126 NES_IDX_ETH_SERDES_TX_EMP0 = 0x2810,
127 NES_IDX_ETH_SERDES_TX_EMP1 = 0x2a10,
128 NES_IDX_ETH_SERDES_TX_DRIVE0 = 0x2814,
129 NES_IDX_ETH_SERDES_TX_DRIVE1 = 0x2a14,
130 NES_IDX_ETH_SERDES_RX_MODE0 = 0x2818,
131 NES_IDX_ETH_SERDES_RX_MODE1 = 0x2a18,
132 NES_IDX_ETH_SERDES_RX_SIGDET0 = 0x281c,
133 NES_IDX_ETH_SERDES_RX_SIGDET1 = 0x2a1c,
134 NES_IDX_ETH_SERDES_BYPASS0 = 0x2820,
135 NES_IDX_ETH_SERDES_BYPASS1 = 0x2a20,
136 NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0 = 0x2824,
137 NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1 = 0x2a24,
138 NES_IDX_ETH_SERDES_RX_EQ_CONTROL0 = 0x2828,
139 NES_IDX_ETH_SERDES_RX_EQ_CONTROL1 = 0x2a28,
140 NES_IDX_ETH_SERDES_RX_EQ_STATUS0 = 0x282c,
141 NES_IDX_ETH_SERDES_RX_EQ_STATUS1 = 0x2a2c,
142 NES_IDX_ETH_SERDES_CDR_RESET0 = 0x2830,
143 NES_IDX_ETH_SERDES_CDR_RESET1 = 0x2a30,
144 NES_IDX_ETH_SERDES_CDR_CONTROL0 = 0x2834,
145 NES_IDX_ETH_SERDES_CDR_CONTROL1 = 0x2a34,
146 NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0 = 0x2838,
147 NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1 = 0x2a38,
148 NES_IDX_ENDNODE0_NSTAT_RX_DISCARD = 0x3080,
149 NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_LO = 0x3000,
150 NES_IDX_ENDNODE0_NSTAT_RX_OCTETS_HI = 0x3004,
151 NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_LO = 0x3008,
152 NES_IDX_ENDNODE0_NSTAT_RX_FRAMES_HI = 0x300c,
153 NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_LO = 0x7000,
154 NES_IDX_ENDNODE0_NSTAT_TX_OCTETS_HI = 0x7004,
155 NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_LO = 0x7008,
156 NES_IDX_ENDNODE0_NSTAT_TX_FRAMES_HI = 0x700c,
157 NES_IDX_CM_CONFIG = 0x5100,
158 NES_IDX_NIC_LOGPORT_TO_PHYPORT = 0x6000,
159 NES_IDX_NIC_PHYPORT_TO_USW = 0x6008,
160 NES_IDX_NIC_ACTIVE = 0x6010,
161 NES_IDX_NIC_UNICAST_ALL = 0x6018,
162 NES_IDX_NIC_MULTICAST_ALL = 0x6020,
163 NES_IDX_NIC_MULTICAST_ENABLE = 0x6028,
164 NES_IDX_NIC_BROADCAST_ON = 0x6030,
165 NES_IDX_USED_CHUNKS_TX = 0x60b0,
166 NES_IDX_TX_POOL_SIZE = 0x60b8,
167 NES_IDX_QUAD_HASH_TABLE_SIZE = 0x6148,
168 NES_IDX_PERFECT_FILTER_LOW = 0x6200,
169 NES_IDX_PERFECT_FILTER_HIGH = 0x6204,
170 NES_IDX_IPV4_TCP_REXMITS = 0x7080,
171 NES_IDX_DEBUG_ERROR_CONTROL_STATUS = 0x913c,
172 NES_IDX_DEBUG_ERROR_MASKS0 = 0x9140,
173 NES_IDX_DEBUG_ERROR_MASKS1 = 0x9144,
174 NES_IDX_DEBUG_ERROR_MASKS2 = 0x9148,
175 NES_IDX_DEBUG_ERROR_MASKS3 = 0x914c,
176 NES_IDX_DEBUG_ERROR_MASKS4 = 0x9150,
177 NES_IDX_DEBUG_ERROR_MASKS5 = 0x9154,
178};
179
180#define NES_IDX_MAC_TX_CONFIG_ENABLE_PAUSE 1
181#define NES_IDX_MPP_DEBUG_PORT_DISABLE_PAUSE (1 << 17)
182
183enum nes_cqp_opcodes {
184 NES_CQP_CREATE_QP = 0x00,
185 NES_CQP_MODIFY_QP = 0x01,
186 NES_CQP_DESTROY_QP = 0x02,
187 NES_CQP_CREATE_CQ = 0x03,
188 NES_CQP_MODIFY_CQ = 0x04,
189 NES_CQP_DESTROY_CQ = 0x05,
190 NES_CQP_ALLOCATE_STAG = 0x09,
191 NES_CQP_REGISTER_STAG = 0x0a,
192 NES_CQP_QUERY_STAG = 0x0b,
193 NES_CQP_REGISTER_SHARED_STAG = 0x0c,
194 NES_CQP_DEALLOCATE_STAG = 0x0d,
195 NES_CQP_MANAGE_ARP_CACHE = 0x0f,
196 NES_CQP_SUSPEND_QPS = 0x11,
197 NES_CQP_UPLOAD_CONTEXT = 0x13,
198 NES_CQP_CREATE_CEQ = 0x16,
199 NES_CQP_DESTROY_CEQ = 0x18,
200 NES_CQP_CREATE_AEQ = 0x19,
201 NES_CQP_DESTROY_AEQ = 0x1b,
202 NES_CQP_LMI_ACCESS = 0x20,
203 NES_CQP_FLUSH_WQES = 0x22,
204 NES_CQP_MANAGE_APBVT = 0x23
205};
206
207enum nes_cqp_wqe_word_idx {
208 NES_CQP_WQE_OPCODE_IDX = 0,
209 NES_CQP_WQE_ID_IDX = 1,
210 NES_CQP_WQE_COMP_CTX_LOW_IDX = 2,
211 NES_CQP_WQE_COMP_CTX_HIGH_IDX = 3,
212 NES_CQP_WQE_COMP_SCRATCH_LOW_IDX = 4,
213 NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX = 5,
214};
215
216enum nes_cqp_cq_wqeword_idx {
217 NES_CQP_CQ_WQE_PBL_LOW_IDX = 6,
218 NES_CQP_CQ_WQE_PBL_HIGH_IDX = 7,
219 NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX = 8,
220 NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX = 9,
221 NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX = 10,
222};
223
224enum nes_cqp_stag_wqeword_idx {
225 NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX = 1,
226 NES_CQP_STAG_WQE_LEN_HIGH_PD_IDX = 6,
227 NES_CQP_STAG_WQE_LEN_LOW_IDX = 7,
228 NES_CQP_STAG_WQE_STAG_IDX = 8,
229 NES_CQP_STAG_WQE_VA_LOW_IDX = 10,
230 NES_CQP_STAG_WQE_VA_HIGH_IDX = 11,
231 NES_CQP_STAG_WQE_PA_LOW_IDX = 12,
232 NES_CQP_STAG_WQE_PA_HIGH_IDX = 13,
233 NES_CQP_STAG_WQE_PBL_LEN_IDX = 14
234};
235
236#define NES_CQP_OP_IWARP_STATE_SHIFT 28
237
238enum nes_cqp_qp_bits {
239 NES_CQP_QP_ARP_VALID = (1<<8),
240 NES_CQP_QP_WINBUF_VALID = (1<<9),
241 NES_CQP_QP_CONTEXT_VALID = (1<<10),
242 NES_CQP_QP_ORD_VALID = (1<<11),
243 NES_CQP_QP_WINBUF_DATAIND_EN = (1<<12),
244 NES_CQP_QP_VIRT_WQS = (1<<13),
245 NES_CQP_QP_DEL_HTE = (1<<14),
246 NES_CQP_QP_CQS_VALID = (1<<15),
247 NES_CQP_QP_TYPE_TSA = 0,
248 NES_CQP_QP_TYPE_IWARP = (1<<16),
249 NES_CQP_QP_TYPE_CQP = (4<<16),
250 NES_CQP_QP_TYPE_NIC = (5<<16),
251 NES_CQP_QP_MSS_CHG = (1<<20),
252 NES_CQP_QP_STATIC_RESOURCES = (1<<21),
253 NES_CQP_QP_IGNORE_MW_BOUND = (1<<22),
254 NES_CQP_QP_VWQ_USE_LMI = (1<<23),
255 NES_CQP_QP_IWARP_STATE_IDLE = (1<<NES_CQP_OP_IWARP_STATE_SHIFT),
256 NES_CQP_QP_IWARP_STATE_RTS = (2<<NES_CQP_OP_IWARP_STATE_SHIFT),
257 NES_CQP_QP_IWARP_STATE_CLOSING = (3<<NES_CQP_OP_IWARP_STATE_SHIFT),
258 NES_CQP_QP_IWARP_STATE_TERMINATE = (5<<NES_CQP_OP_IWARP_STATE_SHIFT),
259 NES_CQP_QP_IWARP_STATE_ERROR = (6<<NES_CQP_OP_IWARP_STATE_SHIFT),
260 NES_CQP_QP_IWARP_STATE_MASK = (7<<NES_CQP_OP_IWARP_STATE_SHIFT),
261 NES_CQP_QP_RESET = (1<<31),
262};
263
264enum nes_cqp_qp_wqe_word_idx {
265 NES_CQP_QP_WQE_CONTEXT_LOW_IDX = 6,
266 NES_CQP_QP_WQE_CONTEXT_HIGH_IDX = 7,
267 NES_CQP_QP_WQE_NEW_MSS_IDX = 15,
268};
269
270enum nes_nic_ctx_bits {
271 NES_NIC_CTX_RQ_SIZE_32 = (3<<8),
272 NES_NIC_CTX_RQ_SIZE_512 = (3<<8),
273 NES_NIC_CTX_SQ_SIZE_32 = (1<<10),
274 NES_NIC_CTX_SQ_SIZE_512 = (3<<10),
275};
276
277enum nes_nic_qp_ctx_word_idx {
278 NES_NIC_CTX_MISC_IDX = 0,
279 NES_NIC_CTX_SQ_LOW_IDX = 2,
280 NES_NIC_CTX_SQ_HIGH_IDX = 3,
281 NES_NIC_CTX_RQ_LOW_IDX = 4,
282 NES_NIC_CTX_RQ_HIGH_IDX = 5,
283};
284
285enum nes_cqp_cq_bits {
286 NES_CQP_CQ_CEQE_MASK = (1<<9),
287 NES_CQP_CQ_CEQ_VALID = (1<<10),
288 NES_CQP_CQ_RESIZE = (1<<11),
289 NES_CQP_CQ_CHK_OVERFLOW = (1<<12),
290 NES_CQP_CQ_4KB_CHUNK = (1<<14),
291 NES_CQP_CQ_VIRT = (1<<15),
292};
293
294enum nes_cqp_stag_bits {
295 NES_CQP_STAG_VA_TO = (1<<9),
296 NES_CQP_STAG_DEALLOC_PBLS = (1<<10),
297 NES_CQP_STAG_PBL_BLK_SIZE = (1<<11),
298 NES_CQP_STAG_MR = (1<<13),
299 NES_CQP_STAG_RIGHTS_LOCAL_READ = (1<<16),
300 NES_CQP_STAG_RIGHTS_LOCAL_WRITE = (1<<17),
301 NES_CQP_STAG_RIGHTS_REMOTE_READ = (1<<18),
302 NES_CQP_STAG_RIGHTS_REMOTE_WRITE = (1<<19),
303 NES_CQP_STAG_RIGHTS_WINDOW_BIND = (1<<20),
304 NES_CQP_STAG_REM_ACC_EN = (1<<21),
305 NES_CQP_STAG_LEAVE_PENDING = (1<<31),
306};
307
308enum nes_cqp_ceq_wqeword_idx {
309 NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX = 1,
310 NES_CQP_CEQ_WQE_PBL_LOW_IDX = 6,
311 NES_CQP_CEQ_WQE_PBL_HIGH_IDX = 7,
312};
313
314enum nes_cqp_ceq_bits {
315 NES_CQP_CEQ_4KB_CHUNK = (1<<14),
316 NES_CQP_CEQ_VIRT = (1<<15),
317};
318
319enum nes_cqp_aeq_wqeword_idx {
320 NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX = 1,
321 NES_CQP_AEQ_WQE_PBL_LOW_IDX = 6,
322 NES_CQP_AEQ_WQE_PBL_HIGH_IDX = 7,
323};
324
325enum nes_cqp_aeq_bits {
326 NES_CQP_AEQ_4KB_CHUNK = (1<<14),
327 NES_CQP_AEQ_VIRT = (1<<15),
328};
329
330enum nes_cqp_lmi_wqeword_idx {
331 NES_CQP_LMI_WQE_LMI_OFFSET_IDX = 1,
332 NES_CQP_LMI_WQE_FRAG_LOW_IDX = 8,
333 NES_CQP_LMI_WQE_FRAG_HIGH_IDX = 9,
334 NES_CQP_LMI_WQE_FRAG_LEN_IDX = 10,
335};
336
337enum nes_cqp_arp_wqeword_idx {
338 NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX = 6,
339 NES_CQP_ARP_WQE_MAC_HIGH_IDX = 7,
340 NES_CQP_ARP_WQE_REACHABILITY_MAX_IDX = 1,
341};
342
343enum nes_cqp_upload_wqeword_idx {
344 NES_CQP_UPLOAD_WQE_CTXT_LOW_IDX = 6,
345 NES_CQP_UPLOAD_WQE_CTXT_HIGH_IDX = 7,
346 NES_CQP_UPLOAD_WQE_HTE_IDX = 8,
347};
348
349enum nes_cqp_arp_bits {
350 NES_CQP_ARP_VALID = (1<<8),
351 NES_CQP_ARP_PERM = (1<<9),
352};
353
354enum nes_cqp_flush_bits {
355 NES_CQP_FLUSH_SQ = (1<<30),
356 NES_CQP_FLUSH_RQ = (1<<31),
357};
358
359enum nes_cqe_opcode_bits {
360 NES_CQE_STAG_VALID = (1<<6),
361 NES_CQE_ERROR = (1<<7),
362 NES_CQE_SQ = (1<<8),
363 NES_CQE_SE = (1<<9),
364 NES_CQE_PSH = (1<<29),
365 NES_CQE_FIN = (1<<30),
366 NES_CQE_VALID = (1<<31),
367};
368
369
370enum nes_cqe_word_idx {
371 NES_CQE_PAYLOAD_LENGTH_IDX = 0,
372 NES_CQE_COMP_COMP_CTX_LOW_IDX = 2,
373 NES_CQE_COMP_COMP_CTX_HIGH_IDX = 3,
374 NES_CQE_INV_STAG_IDX = 4,
375 NES_CQE_QP_ID_IDX = 5,
376 NES_CQE_ERROR_CODE_IDX = 6,
377 NES_CQE_OPCODE_IDX = 7,
378};
379
380enum nes_ceqe_word_idx {
381 NES_CEQE_CQ_CTX_LOW_IDX = 0,
382 NES_CEQE_CQ_CTX_HIGH_IDX = 1,
383};
384
385enum nes_ceqe_status_bit {
386 NES_CEQE_VALID = (1<<31),
387};
388
389enum nes_int_bits {
390 NES_INT_CEQ0 = (1<<0),
391 NES_INT_CEQ1 = (1<<1),
392 NES_INT_CEQ2 = (1<<2),
393 NES_INT_CEQ3 = (1<<3),
394 NES_INT_CEQ4 = (1<<4),
395 NES_INT_CEQ5 = (1<<5),
396 NES_INT_CEQ6 = (1<<6),
397 NES_INT_CEQ7 = (1<<7),
398 NES_INT_CEQ8 = (1<<8),
399 NES_INT_CEQ9 = (1<<9),
400 NES_INT_CEQ10 = (1<<10),
401 NES_INT_CEQ11 = (1<<11),
402 NES_INT_CEQ12 = (1<<12),
403 NES_INT_CEQ13 = (1<<13),
404 NES_INT_CEQ14 = (1<<14),
405 NES_INT_CEQ15 = (1<<15),
406 NES_INT_AEQ0 = (1<<16),
407 NES_INT_AEQ1 = (1<<17),
408 NES_INT_AEQ2 = (1<<18),
409 NES_INT_AEQ3 = (1<<19),
410 NES_INT_AEQ4 = (1<<20),
411 NES_INT_AEQ5 = (1<<21),
412 NES_INT_AEQ6 = (1<<22),
413 NES_INT_AEQ7 = (1<<23),
414 NES_INT_MAC0 = (1<<24),
415 NES_INT_MAC1 = (1<<25),
416 NES_INT_MAC2 = (1<<26),
417 NES_INT_MAC3 = (1<<27),
418 NES_INT_TSW = (1<<28),
419 NES_INT_TIMER = (1<<29),
420 NES_INT_INTF = (1<<30),
421};
422
423enum nes_intf_int_bits {
424 NES_INTF_INT_PCIERR = (1<<0),
425 NES_INTF_PERIODIC_TIMER = (1<<2),
426 NES_INTF_ONE_SHOT_TIMER = (1<<3),
427 NES_INTF_INT_CRITERR = (1<<14),
428 NES_INTF_INT_AEQ0_OFLOW = (1<<16),
429 NES_INTF_INT_AEQ1_OFLOW = (1<<17),
430 NES_INTF_INT_AEQ2_OFLOW = (1<<18),
431 NES_INTF_INT_AEQ3_OFLOW = (1<<19),
432 NES_INTF_INT_AEQ4_OFLOW = (1<<20),
433 NES_INTF_INT_AEQ5_OFLOW = (1<<21),
434 NES_INTF_INT_AEQ6_OFLOW = (1<<22),
435 NES_INTF_INT_AEQ7_OFLOW = (1<<23),
436 NES_INTF_INT_AEQ_OFLOW = (0xff<<16),
437};
438
439enum nes_mac_int_bits {
440 NES_MAC_INT_LINK_STAT_CHG = (1<<1),
441 NES_MAC_INT_XGMII_EXT = (1<<2),
442 NES_MAC_INT_TX_UNDERFLOW = (1<<6),
443 NES_MAC_INT_TX_ERROR = (1<<7),
444};
445
446enum nes_cqe_allocate_bits {
447 NES_CQE_ALLOC_INC_SELECT = (1<<28),
448 NES_CQE_ALLOC_NOTIFY_NEXT = (1<<29),
449 NES_CQE_ALLOC_NOTIFY_SE = (1<<30),
450 NES_CQE_ALLOC_RESET = (1<<31),
451};
452
453enum nes_nic_rq_wqe_word_idx {
454 NES_NIC_RQ_WQE_LENGTH_1_0_IDX = 0,
455 NES_NIC_RQ_WQE_LENGTH_3_2_IDX = 1,
456 NES_NIC_RQ_WQE_FRAG0_LOW_IDX = 2,
457 NES_NIC_RQ_WQE_FRAG0_HIGH_IDX = 3,
458 NES_NIC_RQ_WQE_FRAG1_LOW_IDX = 4,
459 NES_NIC_RQ_WQE_FRAG1_HIGH_IDX = 5,
460 NES_NIC_RQ_WQE_FRAG2_LOW_IDX = 6,
461 NES_NIC_RQ_WQE_FRAG2_HIGH_IDX = 7,
462 NES_NIC_RQ_WQE_FRAG3_LOW_IDX = 8,
463 NES_NIC_RQ_WQE_FRAG3_HIGH_IDX = 9,
464};
465
466enum nes_nic_sq_wqe_word_idx {
467 NES_NIC_SQ_WQE_MISC_IDX = 0,
468 NES_NIC_SQ_WQE_TOTAL_LENGTH_IDX = 1,
469 NES_NIC_SQ_WQE_LSO_INFO_IDX = 2,
470 NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX = 3,
471 NES_NIC_SQ_WQE_LENGTH_2_1_IDX = 4,
472 NES_NIC_SQ_WQE_LENGTH_4_3_IDX = 5,
473 NES_NIC_SQ_WQE_FRAG0_LOW_IDX = 6,
474 NES_NIC_SQ_WQE_FRAG0_HIGH_IDX = 7,
475 NES_NIC_SQ_WQE_FRAG1_LOW_IDX = 8,
476 NES_NIC_SQ_WQE_FRAG1_HIGH_IDX = 9,
477 NES_NIC_SQ_WQE_FRAG2_LOW_IDX = 10,
478 NES_NIC_SQ_WQE_FRAG2_HIGH_IDX = 11,
479 NES_NIC_SQ_WQE_FRAG3_LOW_IDX = 12,
480 NES_NIC_SQ_WQE_FRAG3_HIGH_IDX = 13,
481 NES_NIC_SQ_WQE_FRAG4_LOW_IDX = 14,
482 NES_NIC_SQ_WQE_FRAG4_HIGH_IDX = 15,
483};
484
485enum nes_iwarp_sq_wqe_word_idx {
486 NES_IWARP_SQ_WQE_MISC_IDX = 0,
487 NES_IWARP_SQ_WQE_TOTAL_PAYLOAD_IDX = 1,
488 NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX = 2,
489 NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX = 3,
490 NES_IWARP_SQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
491 NES_IWARP_SQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
492 NES_IWARP_SQ_WQE_INV_STAG_LOW_IDX = 7,
493 NES_IWARP_SQ_WQE_RDMA_TO_LOW_IDX = 8,
494 NES_IWARP_SQ_WQE_RDMA_TO_HIGH_IDX = 9,
495 NES_IWARP_SQ_WQE_RDMA_LENGTH_IDX = 10,
496 NES_IWARP_SQ_WQE_RDMA_STAG_IDX = 11,
497 NES_IWARP_SQ_WQE_IMM_DATA_START_IDX = 12,
498 NES_IWARP_SQ_WQE_FRAG0_LOW_IDX = 16,
499 NES_IWARP_SQ_WQE_FRAG0_HIGH_IDX = 17,
500 NES_IWARP_SQ_WQE_LENGTH0_IDX = 18,
501 NES_IWARP_SQ_WQE_STAG0_IDX = 19,
502 NES_IWARP_SQ_WQE_FRAG1_LOW_IDX = 20,
503 NES_IWARP_SQ_WQE_FRAG1_HIGH_IDX = 21,
504 NES_IWARP_SQ_WQE_LENGTH1_IDX = 22,
505 NES_IWARP_SQ_WQE_STAG1_IDX = 23,
506 NES_IWARP_SQ_WQE_FRAG2_LOW_IDX = 24,
507 NES_IWARP_SQ_WQE_FRAG2_HIGH_IDX = 25,
508 NES_IWARP_SQ_WQE_LENGTH2_IDX = 26,
509 NES_IWARP_SQ_WQE_STAG2_IDX = 27,
510 NES_IWARP_SQ_WQE_FRAG3_LOW_IDX = 28,
511 NES_IWARP_SQ_WQE_FRAG3_HIGH_IDX = 29,
512 NES_IWARP_SQ_WQE_LENGTH3_IDX = 30,
513 NES_IWARP_SQ_WQE_STAG3_IDX = 31,
514};
515
516enum nes_iwarp_sq_bind_wqe_word_idx {
517 NES_IWARP_SQ_BIND_WQE_MR_IDX = 6,
518 NES_IWARP_SQ_BIND_WQE_MW_IDX = 7,
519 NES_IWARP_SQ_BIND_WQE_LENGTH_LOW_IDX = 8,
520 NES_IWARP_SQ_BIND_WQE_LENGTH_HIGH_IDX = 9,
521 NES_IWARP_SQ_BIND_WQE_VA_FBO_LOW_IDX = 10,
522 NES_IWARP_SQ_BIND_WQE_VA_FBO_HIGH_IDX = 11,
523};
524
525enum nes_iwarp_sq_fmr_wqe_word_idx {
526 NES_IWARP_SQ_FMR_WQE_MR_STAG_IDX = 7,
527 NES_IWARP_SQ_FMR_WQE_LENGTH_LOW_IDX = 8,
528 NES_IWARP_SQ_FMR_WQE_LENGTH_HIGH_IDX = 9,
529 NES_IWARP_SQ_FMR_WQE_VA_FBO_LOW_IDX = 10,
530 NES_IWARP_SQ_FMR_WQE_VA_FBO_HIGH_IDX = 11,
531 NES_IWARP_SQ_FMR_WQE_PBL_ADDR_LOW_IDX = 12,
532 NES_IWARP_SQ_FMR_WQE_PBL_ADDR_HIGH_IDX = 13,
533 NES_IWARP_SQ_FMR_WQE_PBL_LENGTH_IDX = 14,
534};
535
536enum nes_iwarp_sq_locinv_wqe_word_idx {
537 NES_IWARP_SQ_LOCINV_WQE_INV_STAG_IDX = 6,
538};
539
540
541enum nes_iwarp_rq_wqe_word_idx {
542 NES_IWARP_RQ_WQE_TOTAL_PAYLOAD_IDX = 1,
543 NES_IWARP_RQ_WQE_COMP_CTX_LOW_IDX = 2,
544 NES_IWARP_RQ_WQE_COMP_CTX_HIGH_IDX = 3,
545 NES_IWARP_RQ_WQE_COMP_SCRATCH_LOW_IDX = 4,
546 NES_IWARP_RQ_WQE_COMP_SCRATCH_HIGH_IDX = 5,
547 NES_IWARP_RQ_WQE_FRAG0_LOW_IDX = 8,
548 NES_IWARP_RQ_WQE_FRAG0_HIGH_IDX = 9,
549 NES_IWARP_RQ_WQE_LENGTH0_IDX = 10,
550 NES_IWARP_RQ_WQE_STAG0_IDX = 11,
551 NES_IWARP_RQ_WQE_FRAG1_LOW_IDX = 12,
552 NES_IWARP_RQ_WQE_FRAG1_HIGH_IDX = 13,
553 NES_IWARP_RQ_WQE_LENGTH1_IDX = 14,
554 NES_IWARP_RQ_WQE_STAG1_IDX = 15,
555 NES_IWARP_RQ_WQE_FRAG2_LOW_IDX = 16,
556 NES_IWARP_RQ_WQE_FRAG2_HIGH_IDX = 17,
557 NES_IWARP_RQ_WQE_LENGTH2_IDX = 18,
558 NES_IWARP_RQ_WQE_STAG2_IDX = 19,
559 NES_IWARP_RQ_WQE_FRAG3_LOW_IDX = 20,
560 NES_IWARP_RQ_WQE_FRAG3_HIGH_IDX = 21,
561 NES_IWARP_RQ_WQE_LENGTH3_IDX = 22,
562 NES_IWARP_RQ_WQE_STAG3_IDX = 23,
563};
564
565enum nes_nic_sq_wqe_bits {
566 NES_NIC_SQ_WQE_PHDR_CS_READY = (1<<21),
567 NES_NIC_SQ_WQE_LSO_ENABLE = (1<<22),
568 NES_NIC_SQ_WQE_TAGVALUE_ENABLE = (1<<23),
569 NES_NIC_SQ_WQE_DISABLE_CHKSUM = (1<<30),
570 NES_NIC_SQ_WQE_COMPLETION = (1<<31),
571};
572
573enum nes_nic_cqe_word_idx {
574 NES_NIC_CQE_ACCQP_ID_IDX = 0,
575 NES_NIC_CQE_TAG_PKT_TYPE_IDX = 2,
576 NES_NIC_CQE_MISC_IDX = 3,
577};
578
579#define NES_PKT_TYPE_APBVT_BITS 0xC112
580#define NES_PKT_TYPE_APBVT_MASK 0xff3e
581
582#define NES_PKT_TYPE_PVALID_BITS 0x10000000
583#define NES_PKT_TYPE_PVALID_MASK 0x30000000
584
585#define NES_PKT_TYPE_TCPV4_BITS 0x0110
586#define NES_PKT_TYPE_TCPV4_MASK 0x3f30
587
588#define NES_PKT_TYPE_UDPV4_BITS 0x0210
589#define NES_PKT_TYPE_UDPV4_MASK 0x3f30
590
591#define NES_PKT_TYPE_IPV4_BITS 0x0010
592#define NES_PKT_TYPE_IPV4_MASK 0x3f30
593
594#define NES_PKT_TYPE_OTHER_BITS 0x0000
595#define NES_PKT_TYPE_OTHER_MASK 0x0030
596
597#define NES_NIC_CQE_ERRV_SHIFT 16
598enum nes_nic_ev_bits {
599 NES_NIC_ERRV_BITS_MODE = (1<<0),
600 NES_NIC_ERRV_BITS_IPV4_CSUM_ERR = (1<<1),
601 NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR = (1<<2),
602 NES_NIC_ERRV_BITS_WQE_OVERRUN = (1<<3),
603 NES_NIC_ERRV_BITS_IPH_ERR = (1<<4),
604};
605
606enum nes_nic_cqe_bits {
607 NES_NIC_CQE_ERRV_MASK = (0xff<<NES_NIC_CQE_ERRV_SHIFT),
608 NES_NIC_CQE_SQ = (1<<24),
609 NES_NIC_CQE_ACCQP_PORT = (1<<28),
610 NES_NIC_CQE_ACCQP_VALID = (1<<29),
611 NES_NIC_CQE_TAG_VALID = (1<<30),
612 NES_NIC_CQE_VALID = (1<<31),
613};
614
615enum nes_aeqe_word_idx {
616 NES_AEQE_COMP_CTXT_LOW_IDX = 0,
617 NES_AEQE_COMP_CTXT_HIGH_IDX = 1,
618 NES_AEQE_COMP_QP_CQ_ID_IDX = 2,
619 NES_AEQE_MISC_IDX = 3,
620};
621
622enum nes_aeqe_bits {
623 NES_AEQE_QP = (1<<16),
624 NES_AEQE_CQ = (1<<17),
625 NES_AEQE_SQ = (1<<18),
626 NES_AEQE_INBOUND_RDMA = (1<<19),
627 NES_AEQE_IWARP_STATE_MASK = (7<<20),
628 NES_AEQE_TCP_STATE_MASK = (0xf<<24),
629 NES_AEQE_VALID = (1<<31),
630};
631
632#define NES_AEQE_IWARP_STATE_SHIFT 20
633#define NES_AEQE_TCP_STATE_SHIFT 24
634
635enum nes_aeqe_iwarp_state {
636 NES_AEQE_IWARP_STATE_NON_EXISTANT = 0,
637 NES_AEQE_IWARP_STATE_IDLE = 1,
638 NES_AEQE_IWARP_STATE_RTS = 2,
639 NES_AEQE_IWARP_STATE_CLOSING = 3,
640 NES_AEQE_IWARP_STATE_TERMINATE = 5,
641 NES_AEQE_IWARP_STATE_ERROR = 6
642};
643
644enum nes_aeqe_tcp_state {
645 NES_AEQE_TCP_STATE_NON_EXISTANT = 0,
646 NES_AEQE_TCP_STATE_CLOSED = 1,
647 NES_AEQE_TCP_STATE_LISTEN = 2,
648 NES_AEQE_TCP_STATE_SYN_SENT = 3,
649 NES_AEQE_TCP_STATE_SYN_RCVD = 4,
650 NES_AEQE_TCP_STATE_ESTABLISHED = 5,
651 NES_AEQE_TCP_STATE_CLOSE_WAIT = 6,
652 NES_AEQE_TCP_STATE_FIN_WAIT_1 = 7,
653 NES_AEQE_TCP_STATE_CLOSING = 8,
654 NES_AEQE_TCP_STATE_LAST_ACK = 9,
655 NES_AEQE_TCP_STATE_FIN_WAIT_2 = 10,
656 NES_AEQE_TCP_STATE_TIME_WAIT = 11
657};
658
659enum nes_aeqe_aeid {
660 NES_AEQE_AEID_AMP_UNALLOCATED_STAG = 0x0102,
661 NES_AEQE_AEID_AMP_INVALID_STAG = 0x0103,
662 NES_AEQE_AEID_AMP_BAD_QP = 0x0104,
663 NES_AEQE_AEID_AMP_BAD_PD = 0x0105,
664 NES_AEQE_AEID_AMP_BAD_STAG_KEY = 0x0106,
665 NES_AEQE_AEID_AMP_BAD_STAG_INDEX = 0x0107,
666 NES_AEQE_AEID_AMP_BOUNDS_VIOLATION = 0x0108,
667 NES_AEQE_AEID_AMP_RIGHTS_VIOLATION = 0x0109,
668 NES_AEQE_AEID_AMP_TO_WRAP = 0x010a,
669 NES_AEQE_AEID_AMP_FASTREG_SHARED = 0x010b,
670 NES_AEQE_AEID_AMP_FASTREG_VALID_STAG = 0x010c,
671 NES_AEQE_AEID_AMP_FASTREG_MW_STAG = 0x010d,
672 NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS = 0x010e,
673 NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW = 0x010f,
674 NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH = 0x0110,
675 NES_AEQE_AEID_AMP_INVALIDATE_SHARED = 0x0111,
676 NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS = 0x0112,
677 NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS = 0x0113,
678 NES_AEQE_AEID_AMP_MWBIND_VALID_STAG = 0x0114,
679 NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG = 0x0115,
680 NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG = 0x0116,
681 NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG = 0x0117,
682 NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS = 0x0118,
683 NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS = 0x0119,
684 NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT = 0x011a,
685 NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED = 0x011b,
686 NES_AEQE_AEID_BAD_CLOSE = 0x0201,
687 NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE = 0x0202,
688 NES_AEQE_AEID_CQ_OPERATION_ERROR = 0x0203,
689 NES_AEQE_AEID_PRIV_OPERATION_DENIED = 0x0204,
690 NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO = 0x0205,
691 NES_AEQE_AEID_STAG_ZERO_INVALID = 0x0206,
692 NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN = 0x0301,
693 NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID = 0x0302,
694 NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER = 0x0303,
695 NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION = 0x0304,
696 NES_AEQE_AEID_DDP_UBE_INVALID_MO = 0x0305,
697 NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE = 0x0306,
698 NES_AEQE_AEID_DDP_UBE_INVALID_QN = 0x0307,
699 NES_AEQE_AEID_DDP_NO_L_BIT = 0x0308,
700 NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION = 0x0311,
701 NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE = 0x0312,
702 NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST = 0x0313,
703 NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP = 0x0314,
704 NES_AEQE_AEID_INVALID_ARP_ENTRY = 0x0401,
705 NES_AEQE_AEID_INVALID_TCP_OPTION_RCVD = 0x0402,
706 NES_AEQE_AEID_STALE_ARP_ENTRY = 0x0403,
707 NES_AEQE_AEID_LLP_CLOSE_COMPLETE = 0x0501,
708 NES_AEQE_AEID_LLP_CONNECTION_RESET = 0x0502,
709 NES_AEQE_AEID_LLP_FIN_RECEIVED = 0x0503,
710 NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH = 0x0504,
711 NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR = 0x0505,
712 NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE = 0x0506,
713 NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL = 0x0507,
714 NES_AEQE_AEID_LLP_SYN_RECEIVED = 0x0508,
715 NES_AEQE_AEID_LLP_TERMINATE_RECEIVED = 0x0509,
716 NES_AEQE_AEID_LLP_TOO_MANY_RETRIES = 0x050a,
717 NES_AEQE_AEID_LLP_TOO_MANY_KEEPALIVE_RETRIES = 0x050b,
718 NES_AEQE_AEID_RESET_SENT = 0x0601,
719 NES_AEQE_AEID_TERMINATE_SENT = 0x0602,
720 NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC = 0x0700
721};
722
723enum nes_iwarp_sq_opcodes {
724 NES_IWARP_SQ_WQE_WRPDU = (1<<15),
725 NES_IWARP_SQ_WQE_PSH = (1<<21),
726 NES_IWARP_SQ_WQE_STREAMING = (1<<23),
727 NES_IWARP_SQ_WQE_IMM_DATA = (1<<28),
728 NES_IWARP_SQ_WQE_READ_FENCE = (1<<29),
729 NES_IWARP_SQ_WQE_LOCAL_FENCE = (1<<30),
730 NES_IWARP_SQ_WQE_SIGNALED_COMPL = (1<<31),
731};
732
733enum nes_iwarp_sq_wqe_bits {
734 NES_IWARP_SQ_OP_RDMAW = 0,
735 NES_IWARP_SQ_OP_RDMAR = 1,
736 NES_IWARP_SQ_OP_SEND = 3,
737 NES_IWARP_SQ_OP_SENDINV = 4,
738 NES_IWARP_SQ_OP_SENDSE = 5,
739 NES_IWARP_SQ_OP_SENDSEINV = 6,
740 NES_IWARP_SQ_OP_BIND = 8,
741 NES_IWARP_SQ_OP_FAST_REG = 9,
742 NES_IWARP_SQ_OP_LOCINV = 10,
743 NES_IWARP_SQ_OP_RDMAR_LOCINV = 11,
744 NES_IWARP_SQ_OP_NOP = 12,
745};
746
747#define NES_EEPROM_READ_REQUEST (1<<16)
748#define NES_MAC_ADDR_VALID (1<<20)
749
750/*
751 * NES index registers init values.
752 */
753struct nes_init_values {
754 u32 index;
755 u32 data;
756 u8 wrt;
757};
758
759/*
760 * NES registers in BAR0.
761 */
762struct nes_pci_regs {
763 u32 int_status;
764 u32 int_mask;
765 u32 int_pending;
766 u32 intf_int_status;
767 u32 intf_int_mask;
768 u32 other_regs[59]; /* pad out to 256 bytes for now */
769};
770
771#define NES_CQP_SQ_SIZE 128
772#define NES_CCQ_SIZE 128
773#define NES_NIC_WQ_SIZE 512
774#define NES_NIC_CTX_SIZE ((NES_NIC_CTX_RQ_SIZE_512) | (NES_NIC_CTX_SQ_SIZE_512))
775#define NES_NIC_BACK_STORE 0x00038000
776
777struct nes_device;
778
779struct nes_hw_nic_qp_context {
780 __le32 context_words[6];
781};
782
783struct nes_hw_nic_sq_wqe {
784 __le32 wqe_words[16];
785};
786
787struct nes_hw_nic_rq_wqe {
788 __le32 wqe_words[16];
789};
790
791struct nes_hw_nic_cqe {
792 __le32 cqe_words[4];
793};
794
795struct nes_hw_cqp_qp_context {
796 __le32 context_words[4];
797};
798
799struct nes_hw_cqp_wqe {
800 __le32 wqe_words[16];
801};
802
803struct nes_hw_qp_wqe {
804 __le32 wqe_words[32];
805};
806
807struct nes_hw_cqe {
808 __le32 cqe_words[8];
809};
810
811struct nes_hw_ceqe {
812 __le32 ceqe_words[2];
813};
814
815struct nes_hw_aeqe {
816 __le32 aeqe_words[4];
817};
818
819struct nes_cqp_request {
820 union {
821 u64 cqp_callback_context;
822 void *cqp_callback_pointer;
823 };
824 wait_queue_head_t waitq;
825 struct nes_hw_cqp_wqe cqp_wqe;
826 struct list_head list;
827 atomic_t refcount;
828 void (*cqp_callback)(struct nes_device *nesdev, struct nes_cqp_request *cqp_request);
829 u16 major_code;
830 u16 minor_code;
831 u8 waiting;
832 u8 request_done;
833 u8 dynamic;
834 u8 callback;
835};
836
837struct nes_hw_cqp {
838 struct nes_hw_cqp_wqe *sq_vbase;
839 dma_addr_t sq_pbase;
840 spinlock_t lock;
841 wait_queue_head_t waitq;
842 u16 qp_id;
843 u16 sq_head;
844 u16 sq_tail;
845 u16 sq_size;
846};
847
848#define NES_FIRST_FRAG_SIZE 128
849struct nes_first_frag {
850 u8 buffer[NES_FIRST_FRAG_SIZE];
851};
852
853struct nes_hw_nic {
854 struct nes_first_frag *first_frag_vbase; /* virtual address of first frags */
855 struct nes_hw_nic_sq_wqe *sq_vbase; /* virtual address of sq */
856 struct nes_hw_nic_rq_wqe *rq_vbase; /* virtual address of rq */
857 struct sk_buff *tx_skb[NES_NIC_WQ_SIZE];
858 struct sk_buff *rx_skb[NES_NIC_WQ_SIZE];
859 dma_addr_t frag_paddr[NES_NIC_WQ_SIZE];
860 unsigned long first_frag_overflow[BITS_TO_LONGS(NES_NIC_WQ_SIZE)];
861 dma_addr_t sq_pbase; /* PCI memory for host rings */
862 dma_addr_t rq_pbase; /* PCI memory for host rings */
863
864 u16 qp_id;
865 u16 sq_head;
866 u16 sq_tail;
867 u16 sq_size;
868 u16 rq_head;
869 u16 rq_tail;
870 u16 rq_size;
871 u8 replenishing_rq;
872 u8 reserved;
873
874 spinlock_t sq_lock;
875 spinlock_t rq_lock;
876};
877
878struct nes_hw_nic_cq {
879 struct nes_hw_nic_cqe volatile *cq_vbase; /* PCI memory for host rings */
880 void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_nic_cq *cq);
881 dma_addr_t cq_pbase; /* PCI memory for host rings */
882 int rx_cqes_completed;
883 int cqe_allocs_pending;
884 int rx_pkts_indicated;
885 u16 cq_head;
886 u16 cq_size;
887 u16 cq_number;
888 u8 cqes_pending;
889};
890
891struct nes_hw_qp {
892 struct nes_hw_qp_wqe *sq_vbase; /* PCI memory for host rings */
893 struct nes_hw_qp_wqe *rq_vbase; /* PCI memory for host rings */
894 void *q2_vbase; /* PCI memory for host rings */
895 dma_addr_t sq_pbase; /* PCI memory for host rings */
896 dma_addr_t rq_pbase; /* PCI memory for host rings */
897 dma_addr_t q2_pbase; /* PCI memory for host rings */
898 u32 qp_id;
899 u16 sq_head;
900 u16 sq_tail;
901 u16 sq_size;
902 u16 rq_head;
903 u16 rq_tail;
904 u16 rq_size;
905 u8 rq_encoded_size;
906 u8 sq_encoded_size;
907};
908
909struct nes_hw_cq {
Roland Dreier31d1e342008-04-23 11:55:45 -0700[diff] [blame]910 struct nes_hw_cqe *cq_vbase; /* PCI memory for host rings */
Glenn Streiff3c2d7742008-02-04 20:20:45 -0800[diff] [blame]911 void (*ce_handler)(struct nes_device *nesdev, struct nes_hw_cq *cq);
912 dma_addr_t cq_pbase; /* PCI memory for host rings */
913 u16 cq_head;
914 u16 cq_size;
915 u16 cq_number;
916};
917
918struct nes_hw_ceq {
919 struct nes_hw_ceqe volatile *ceq_vbase; /* PCI memory for host rings */
920 dma_addr_t ceq_pbase; /* PCI memory for host rings */
921 u16 ceq_head;
922 u16 ceq_size;
923};
924
925struct nes_hw_aeq {
926 struct nes_hw_aeqe volatile *aeq_vbase; /* PCI memory for host rings */
927 dma_addr_t aeq_pbase; /* PCI memory for host rings */
928 u16 aeq_head;
929 u16 aeq_size;
930};
931
932struct nic_qp_map {
933 u8 qpid;
934 u8 nic_index;
935 u8 logical_port;
936 u8 is_hnic;
937};
938
939#define NES_CQP_ARP_AEQ_INDEX_MASK 0x000f0000
940#define NES_CQP_ARP_AEQ_INDEX_SHIFT 16
941
942#define NES_CQP_APBVT_ADD 0x00008000
943#define NES_CQP_APBVT_NIC_SHIFT 16
944
945#define NES_ARP_ADD 1
946#define NES_ARP_DELETE 2
947#define NES_ARP_RESOLVE 3
948
949#define NES_MAC_SW_IDLE 0
950#define NES_MAC_SW_INTERRUPT 1
951#define NES_MAC_SW_MH 2
952
953struct nes_arp_entry {
954 u32 ip_addr;
955 u8 mac_addr[ETH_ALEN];
956};
957
958#define NES_NIC_FAST_TIMER 96
959#define NES_NIC_FAST_TIMER_LOW 40
960#define NES_NIC_FAST_TIMER_HIGH 1000
961#define DEFAULT_NES_QL_HIGH 256
962#define DEFAULT_NES_QL_LOW 16
963#define DEFAULT_NES_QL_TARGET 64
964#define DEFAULT_JUMBO_NES_QL_LOW 12
965#define DEFAULT_JUMBO_NES_QL_TARGET 40
966#define DEFAULT_JUMBO_NES_QL_HIGH 128
John Lacombe4b1cc7e2008-02-21 08:34:58 -0600[diff] [blame]967#define NES_NIC_CQ_DOWNWARD_TREND 16
Glenn Streiff3c2d7742008-02-04 20:20:45 -0800[diff] [blame]968
969struct nes_hw_tune_timer {
970 //u16 cq_count;
971 u16 threshold_low;
972 u16 threshold_target;
973 u16 threshold_high;
974 u16 timer_in_use;
975 u16 timer_in_use_old;
976 u16 timer_in_use_min;
977 u16 timer_in_use_max;
978 u8 timer_direction_upward;
979 u8 timer_direction_downward;
980 u16 cq_count_old;
981 u8 cq_direction_downward;
982};
983
984#define NES_TIMER_INT_LIMIT 2
985#define NES_TIMER_INT_LIMIT_DYNAMIC 10
986#define NES_TIMER_ENABLE_LIMIT 4
Faisal Latif37dab412008-04-29 13:46:54 -0700[diff] [blame^]987#define NES_MAX_LINK_INTERRUPTS 128
988#define NES_MAX_LINK_CHECK 200
989#define NES_MAX_LRO_DESCRIPTORS 32
990#define NES_LRO_MAX_AGGR 64
Glenn Streiff3c2d7742008-02-04 20:20:45 -0800[diff] [blame]991
992struct nes_adapter {
993 u64 fw_ver;
994 unsigned long *allocated_qps;
995 unsigned long *allocated_cqs;
996 unsigned long *allocated_mrs;
997 unsigned long *allocated_pds;
998 unsigned long *allocated_arps;
999 struct nes_qp **qp_table;
1000 struct workqueue_struct *work_q;
1001
1002 struct list_head list;
1003 struct list_head active_listeners;
1004 /* list of the netdev's associated with each logical port */
1005 struct list_head nesvnic_list[4];
1006
1007 struct timer_list mh_timer;
1008 struct timer_list lc_timer;
1009 struct work_struct work;
1010 spinlock_t resource_lock;
1011 spinlock_t phy_lock;
1012 spinlock_t pbl_lock;
1013 spinlock_t periodic_timer_lock;
1014
1015 struct nes_arp_entry arp_table[NES_MAX_ARP_TABLE_SIZE];
1016
1017 /* Adapter CEQ and AEQs */
1018 struct nes_hw_ceq ceq[16];
1019 struct nes_hw_aeq aeq[8];
1020
1021 struct nes_hw_tune_timer tune_timer;
1022
1023 unsigned long doorbell_start;
1024
1025 u32 hw_rev;
1026 u32 vendor_id;
1027 u32 vendor_part_id;
1028 u32 device_cap_flags;
1029 u32 tick_delta;
1030 u32 timer_int_req;
1031 u32 arp_table_size;
1032 u32 next_arp_index;
1033
1034 u32 max_mr;
1035 u32 max_256pbl;
1036 u32 max_4kpbl;
1037 u32 free_256pbl;
1038 u32 free_4kpbl;
1039 u32 max_mr_size;
1040 u32 max_qp;
1041 u32 next_qp;
1042 u32 max_irrq;
1043 u32 max_qp_wr;
1044 u32 max_sge;
1045 u32 max_cq;
1046 u32 next_cq;
1047 u32 max_cqe;
1048 u32 max_pd;
1049 u32 base_pd;
1050 u32 next_pd;
1051 u32 hte_index_mask;
1052
1053 /* EEPROM information */
1054 u32 rx_pool_size;
1055 u32 tx_pool_size;
1056 u32 rx_threshold;
1057 u32 tcp_timer_core_clk_divisor;
1058 u32 iwarp_config;
1059 u32 cm_config;
1060 u32 sws_timer_config;
1061 u32 tcp_config1;
1062 u32 wqm_wat;
1063 u32 core_clock;
1064 u32 firmware_version;
1065
1066 u32 nic_rx_eth_route_err;
1067
1068 u32 et_rx_coalesce_usecs;
1069 u32 et_rx_max_coalesced_frames;
1070 u32 et_rx_coalesce_usecs_irq;
1071 u32 et_rx_max_coalesced_frames_irq;
1072 u32 et_pkt_rate_low;
1073 u32 et_rx_coalesce_usecs_low;
1074 u32 et_rx_max_coalesced_frames_low;
1075 u32 et_pkt_rate_high;
1076 u32 et_rx_coalesce_usecs_high;
1077 u32 et_rx_max_coalesced_frames_high;
1078 u32 et_rate_sample_interval;
1079 u32 timer_int_limit;
1080
1081 /* Adapter base MAC address */
1082 u32 mac_addr_low;
1083 u16 mac_addr_high;
1084
1085 u16 firmware_eeprom_offset;
1086 u16 software_eeprom_offset;
1087
1088 u16 max_irrq_wr;
1089
1090 /* pd config for each port */
1091 u16 pd_config_size[4];
1092 u16 pd_config_base[4];
1093
1094 u16 link_interrupt_count[4];
1095
1096 /* the phy index for each port */
1097 u8 phy_index[4];
1098 u8 mac_sw_state[4];
1099 u8 mac_link_down[4];
1100 u8 phy_type[4];
1101
1102 /* PCI information */
1103 unsigned int devfn;
1104 unsigned char bus_number;
1105 unsigned char OneG_Mode;
1106
1107 unsigned char ref_count;
1108 u8 netdev_count;
1109 u8 netdev_max; /* from host nic address count in EEPROM */
1110 u8 port_count;
1111 u8 virtwq;
1112 u8 et_use_adaptive_rx_coalesce;
1113 u8 adapter_fcn_count;
1114};
1115
1116struct nes_pbl {
1117 u64 *pbl_vbase;
1118 dma_addr_t pbl_pbase;
1119 struct page *page;
1120 unsigned long user_base;
1121 u32 pbl_size;
1122 struct list_head list;
1123 /* TODO: need to add list for two level tables */
1124};
1125
1126struct nes_listener {
1127 struct work_struct work;
1128 struct workqueue_struct *wq;
1129 struct nes_vnic *nesvnic;
1130 struct iw_cm_id *cm_id;
1131 struct list_head list;
1132 unsigned long socket;
1133 u8 accept_failed;
1134};
1135
1136struct nes_ib_device;
1137
1138struct nes_vnic {
1139 struct nes_ib_device *nesibdev;
1140 u64 sq_full;
1141 u64 sq_locked;
1142 u64 tso_requests;
1143 u64 segmented_tso_requests;
1144 u64 linearized_skbs;
1145 u64 tx_sw_dropped;
1146 u64 endnode_nstat_rx_discard;
1147 u64 endnode_nstat_rx_octets;
1148 u64 endnode_nstat_rx_frames;
1149 u64 endnode_nstat_tx_octets;
1150 u64 endnode_nstat_tx_frames;
1151 u64 endnode_ipv4_tcp_retransmits;
1152 /* void *mem; */
1153 struct nes_device *nesdev;
1154 struct net_device *netdev;
1155 struct vlan_group *vlan_grp;
1156 atomic_t rx_skbs_needed;
1157 atomic_t rx_skb_timer_running;
1158 int budget;
1159 u32 msg_enable;
1160 /* u32 tx_avail; */
1161 __be32 local_ipaddr;
1162 struct napi_struct napi;
1163 spinlock_t tx_lock; /* could use netdev tx lock? */
1164 struct timer_list rq_wqes_timer;
1165 u32 nic_mem_size;
1166 void *nic_vbase;
1167 dma_addr_t nic_pbase;
1168 struct nes_hw_nic nic;
1169 struct nes_hw_nic_cq nic_cq;
1170 u32 mcrq_qp_id;
1171 struct nes_ucontext *mcrq_ucontext;
1172 struct nes_cqp_request* (*get_cqp_request)(struct nes_device *nesdev);
1173 void (*post_cqp_request)(struct nes_device*, struct nes_cqp_request *, int);
1174 int (*mcrq_mcast_filter)( struct nes_vnic* nesvnic, __u8* dmi_addr );
1175 struct net_device_stats netstats;
1176 /* used to put the netdev on the adapters logical port list */
1177 struct list_head list;
1178 u16 max_frame_size;
1179 u8 netdev_open;
1180 u8 linkup;
1181 u8 logical_port;
1182 u8 netdev_index; /* might not be needed, indexes nesdev->netdev */
1183 u8 perfect_filter_index;
1184 u8 nic_index;
1185 u8 qp_nic_index[4];
1186 u8 next_qp_nic_index;
1187 u8 of_device_registered;
1188 u8 rdma_enabled;
1189 u8 rx_checksum_disabled;
Faisal Latif37dab412008-04-29 13:46:54 -0700[diff] [blame^]1190 u32 lro_max_aggr;
1191 struct net_lro_mgr lro_mgr;
1192 struct net_lro_desc lro_desc[NES_MAX_LRO_DESCRIPTORS];
Glenn Streiff3c2d7742008-02-04 20:20:45 -0800[diff] [blame]1193};
1194
1195struct nes_ib_device {
1196 struct ib_device ibdev;
1197 struct nes_vnic *nesvnic;
1198
1199 /* Virtual RNIC Limits */
1200 u32 max_mr;
1201 u32 max_qp;
1202 u32 max_cq;
1203 u32 max_pd;
1204 u32 num_mr;
1205 u32 num_qp;
1206 u32 num_cq;
1207 u32 num_pd;
1208};
1209
1210#define nes_vlan_rx vlan_hwaccel_receive_skb
1211#define nes_netif_rx netif_receive_skb
1212
1213#endif /* __NES_HW_H */