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Sujithf1dc5602008-10-29 10:16:30 +05301/*
Sujith Manoharan5b681382011-05-17 13:36:18 +05302 * Copyright (c) 2008-2011 Atheros Communications Inc.
Sujithf1dc5602008-10-29 10:16:30 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
Luis R. Rodriguez990b70a2009-09-13 23:55:05 -070017#include "hw.h"
Luis R. Rodriguezac0bb762010-06-12 00:33:42 -040018#include "hw-ops.h"
Paul Gortmakeree40fa02011-05-27 16:14:23 -040019#include <linux/export.h>
Sujithf1dc5602008-10-29 10:16:30 +053020
Sujithcbe61d82009-02-09 13:27:12 +053021static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
Sujithf1dc5602008-10-29 10:16:30 +053022 struct ath9k_tx_queue_info *qi)
23{
Joe Perchesd2182b62011-12-15 14:55:53 -080024 ath_dbg(ath9k_hw_common(ah), INTERRUPT,
Joe Perches226afe62010-12-02 19:12:37 -080025 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
26 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
27 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
28 ah->txurn_interrupt_mask);
Sujithf1dc5602008-10-29 10:16:30 +053029
Sujith7d0d0df2010-04-16 11:53:57 +053030 ENABLE_REGWRITE_BUFFER(ah);
31
Sujithf1dc5602008-10-29 10:16:30 +053032 REG_WRITE(ah, AR_IMR_S0,
Sujith2660b812009-02-09 13:27:26 +053033 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK)
34 | SM(ah->txdesc_interrupt_mask, AR_IMR_S0_QCU_TXDESC));
Sujithf1dc5602008-10-29 10:16:30 +053035 REG_WRITE(ah, AR_IMR_S1,
Sujith2660b812009-02-09 13:27:26 +053036 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR)
37 | SM(ah->txeol_interrupt_mask, AR_IMR_S1_QCU_TXEOL));
Pavel Roskin74bad5c2010-02-23 18:15:27 -050038
39 ah->imrs2_reg &= ~AR_IMR_S2_QCU_TXURN;
40 ah->imrs2_reg |= (ah->txurn_interrupt_mask & AR_IMR_S2_QCU_TXURN);
41 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
Sujith7d0d0df2010-04-16 11:53:57 +053042
43 REGWRITE_BUFFER_FLUSH(ah);
Sujithf1dc5602008-10-29 10:16:30 +053044}
45
Sujithcbe61d82009-02-09 13:27:12 +053046u32 ath9k_hw_gettxbuf(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +053047{
48 return REG_READ(ah, AR_QTXDP(q));
49}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040050EXPORT_SYMBOL(ath9k_hw_gettxbuf);
Sujithf1dc5602008-10-29 10:16:30 +053051
Sujith54e4cec2009-08-07 09:45:09 +053052void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
Sujithf1dc5602008-10-29 10:16:30 +053053{
54 REG_WRITE(ah, AR_QTXDP(q), txdp);
Sujithf1dc5602008-10-29 10:16:30 +053055}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040056EXPORT_SYMBOL(ath9k_hw_puttxbuf);
Sujithf1dc5602008-10-29 10:16:30 +053057
Sujith54e4cec2009-08-07 09:45:09 +053058void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +053059{
Joe Perchesd2182b62011-12-15 14:55:53 -080060 ath_dbg(ath9k_hw_common(ah), QUEUE, "Enable TXE on queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +053061 REG_WRITE(ah, AR_Q_TXE, 1 << q);
Sujithf1dc5602008-10-29 10:16:30 +053062}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040063EXPORT_SYMBOL(ath9k_hw_txstart);
Sujithf1dc5602008-10-29 10:16:30 +053064
Sujithcbe61d82009-02-09 13:27:12 +053065u32 ath9k_hw_numtxpending(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +053066{
67 u32 npend;
68
69 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
70 if (npend == 0) {
71
72 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
73 npend = 1;
74 }
75
76 return npend;
77}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -040078EXPORT_SYMBOL(ath9k_hw_numtxpending);
Sujithf1dc5602008-10-29 10:16:30 +053079
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -050080/**
81 * ath9k_hw_updatetxtriglevel - adjusts the frame trigger level
82 *
83 * @ah: atheros hardware struct
84 * @bIncTrigLevel: whether or not the frame trigger level should be updated
85 *
86 * The frame trigger level specifies the minimum number of bytes,
87 * in units of 64 bytes, that must be DMA'ed into the PCU TX FIFO
88 * before the PCU will initiate sending the frame on the air. This can
89 * mean we initiate transmit before a full frame is on the PCU TX FIFO.
90 * Resets to 0x1 (meaning 64 bytes or a full frame, whichever occurs
91 * first)
92 *
93 * Caution must be taken to ensure to set the frame trigger level based
94 * on the DMA request size. For example if the DMA request size is set to
95 * 128 bytes the trigger level cannot exceed 6 * 64 = 384. This is because
96 * there need to be enough space in the tx FIFO for the requested transfer
97 * size. Hence the tx FIFO will stop with 512 - 128 = 384 bytes. If we set
98 * the threshold to a value beyond 6, then the transmit will hang.
99 *
100 * Current dual stream devices have a PCU TX FIFO size of 8 KB.
101 * Current single stream devices have a PCU TX FIFO size of 4 KB, however,
102 * there is a hardware issue which forces us to use 2 KB instead so the
103 * frame trigger level must not exceed 2 KB for these chipsets.
104 */
Sujithcbe61d82009-02-09 13:27:12 +0530105bool ath9k_hw_updatetxtriglevel(struct ath_hw *ah, bool bIncTrigLevel)
Sujithf1dc5602008-10-29 10:16:30 +0530106{
Sujithf1dc5602008-10-29 10:16:30 +0530107 u32 txcfg, curLevel, newLevel;
Sujithf1dc5602008-10-29 10:16:30 +0530108
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -0500109 if (ah->tx_trig_level >= ah->config.max_txtrig_level)
Sujithf1dc5602008-10-29 10:16:30 +0530110 return false;
111
Felix Fietkau4df30712010-11-08 20:54:47 +0100112 ath9k_hw_disable_interrupts(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530113
114 txcfg = REG_READ(ah, AR_TXCFG);
115 curLevel = MS(txcfg, AR_FTRIG);
116 newLevel = curLevel;
117 if (bIncTrigLevel) {
Luis R. Rodriguezf4709fd2009-11-24 21:37:57 -0500118 if (curLevel < ah->config.max_txtrig_level)
Sujithf1dc5602008-10-29 10:16:30 +0530119 newLevel++;
120 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
121 newLevel--;
122 if (newLevel != curLevel)
123 REG_WRITE(ah, AR_TXCFG,
124 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
125
Felix Fietkau4df30712010-11-08 20:54:47 +0100126 ath9k_hw_enable_interrupts(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530127
Sujith2660b812009-02-09 13:27:26 +0530128 ah->tx_trig_level = newLevel;
Sujithf1dc5602008-10-29 10:16:30 +0530129
130 return newLevel != curLevel;
131}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400132EXPORT_SYMBOL(ath9k_hw_updatetxtriglevel);
Sujithf1dc5602008-10-29 10:16:30 +0530133
Felix Fietkau0d51ccc2011-03-11 21:38:18 +0100134void ath9k_hw_abort_tx_dma(struct ath_hw *ah)
Sujithf1dc5602008-10-29 10:16:30 +0530135{
Felix Fietkau8d1bd2a2012-04-19 21:18:29 +0200136 int maxdelay = 1000;
Felix Fietkau0d51ccc2011-03-11 21:38:18 +0100137 int i, q;
138
Felix Fietkau8d1bd2a2012-04-19 21:18:29 +0200139 if (ah->curchan) {
140 if (IS_CHAN_HALF_RATE(ah->curchan))
141 maxdelay *= 2;
142 else if (IS_CHAN_QUARTER_RATE(ah->curchan))
143 maxdelay *= 4;
144 }
145
Felix Fietkau0d51ccc2011-03-11 21:38:18 +0100146 REG_WRITE(ah, AR_Q_TXD, AR_Q_TXD_M);
147
148 REG_SET_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
149 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
150 REG_SET_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
151
152 for (q = 0; q < AR_NUM_QCU; q++) {
Felix Fietkau8d1bd2a2012-04-19 21:18:29 +0200153 for (i = 0; i < maxdelay; i++) {
Felix Fietkau0d51ccc2011-03-11 21:38:18 +0100154 if (i)
155 udelay(5);
156
157 if (!ath9k_hw_numtxpending(ah, q))
158 break;
159 }
160 }
161
162 REG_CLR_BIT(ah, AR_PCU_MISC, AR_PCU_FORCE_QUIET_COLL | AR_PCU_CLEAR_VMF);
163 REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
164 REG_CLR_BIT(ah, AR_D_GBL_IFS_MISC, AR_D_GBL_IFS_MISC_IGNORE_BACKOFF);
165
166 REG_WRITE(ah, AR_Q_TXD, 0);
167}
168EXPORT_SYMBOL(ath9k_hw_abort_tx_dma);
169
Felix Fietkauefff3952011-03-11 21:38:20 +0100170bool ath9k_hw_stop_dma_queue(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +0530171{
Felix Fietkauefff3952011-03-11 21:38:20 +0100172#define ATH9K_TX_STOP_DMA_TIMEOUT 1000 /* usec */
Sujith94ff91d2009-01-27 15:06:38 +0530173#define ATH9K_TIME_QUANTUM 100 /* usec */
Felix Fietkauefff3952011-03-11 21:38:20 +0100174 int wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
175 int wait;
Sujithf1dc5602008-10-29 10:16:30 +0530176
177 REG_WRITE(ah, AR_Q_TXD, 1 << q);
178
Sujith94ff91d2009-01-27 15:06:38 +0530179 for (wait = wait_time; wait != 0; wait--) {
Felix Fietkauefff3952011-03-11 21:38:20 +0100180 if (wait != wait_time)
181 udelay(ATH9K_TIME_QUANTUM);
182
Sujithf1dc5602008-10-29 10:16:30 +0530183 if (ath9k_hw_numtxpending(ah, q) == 0)
184 break;
Sujithf1dc5602008-10-29 10:16:30 +0530185 }
186
187 REG_WRITE(ah, AR_Q_TXD, 0);
Felix Fietkauefff3952011-03-11 21:38:20 +0100188
Sujithf1dc5602008-10-29 10:16:30 +0530189 return wait != 0;
Sujith94ff91d2009-01-27 15:06:38 +0530190
191#undef ATH9K_TX_STOP_DMA_TIMEOUT
192#undef ATH9K_TIME_QUANTUM
Sujithf1dc5602008-10-29 10:16:30 +0530193}
Felix Fietkauefff3952011-03-11 21:38:20 +0100194EXPORT_SYMBOL(ath9k_hw_stop_dma_queue);
Sujithf1dc5602008-10-29 10:16:30 +0530195
Sujithcbe61d82009-02-09 13:27:12 +0530196bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
Sujithf1dc5602008-10-29 10:16:30 +0530197 const struct ath9k_tx_queue_info *qinfo)
198{
199 u32 cw;
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700200 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530201 struct ath9k_tx_queue_info *qi;
202
Sujith2660b812009-02-09 13:27:26 +0530203 qi = &ah->txq[q];
Sujithf1dc5602008-10-29 10:16:30 +0530204 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800205 ath_dbg(common, QUEUE,
Joe Perches226afe62010-12-02 19:12:37 -0800206 "Set TXQ properties, inactive queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530207 return false;
208 }
209
Joe Perchesd2182b62011-12-15 14:55:53 -0800210 ath_dbg(common, QUEUE, "Set queue properties for: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530211
212 qi->tqi_ver = qinfo->tqi_ver;
213 qi->tqi_subtype = qinfo->tqi_subtype;
214 qi->tqi_qflags = qinfo->tqi_qflags;
215 qi->tqi_priority = qinfo->tqi_priority;
216 if (qinfo->tqi_aifs != ATH9K_TXQ_USEDEFAULT)
217 qi->tqi_aifs = min(qinfo->tqi_aifs, 255U);
218 else
219 qi->tqi_aifs = INIT_AIFS;
220 if (qinfo->tqi_cwmin != ATH9K_TXQ_USEDEFAULT) {
221 cw = min(qinfo->tqi_cwmin, 1024U);
222 qi->tqi_cwmin = 1;
223 while (qi->tqi_cwmin < cw)
224 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
225 } else
226 qi->tqi_cwmin = qinfo->tqi_cwmin;
227 if (qinfo->tqi_cwmax != ATH9K_TXQ_USEDEFAULT) {
228 cw = min(qinfo->tqi_cwmax, 1024U);
229 qi->tqi_cwmax = 1;
230 while (qi->tqi_cwmax < cw)
231 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
232 } else
233 qi->tqi_cwmax = INIT_CWMAX;
234
235 if (qinfo->tqi_shretry != 0)
236 qi->tqi_shretry = min((u32) qinfo->tqi_shretry, 15U);
237 else
238 qi->tqi_shretry = INIT_SH_RETRY;
239 if (qinfo->tqi_lgretry != 0)
240 qi->tqi_lgretry = min((u32) qinfo->tqi_lgretry, 15U);
241 else
242 qi->tqi_lgretry = INIT_LG_RETRY;
243 qi->tqi_cbrPeriod = qinfo->tqi_cbrPeriod;
244 qi->tqi_cbrOverflowLimit = qinfo->tqi_cbrOverflowLimit;
245 qi->tqi_burstTime = qinfo->tqi_burstTime;
246 qi->tqi_readyTime = qinfo->tqi_readyTime;
247
248 switch (qinfo->tqi_subtype) {
249 case ATH9K_WME_UPSD:
250 if (qi->tqi_type == ATH9K_TX_QUEUE_DATA)
251 qi->tqi_intFlags = ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS;
252 break;
253 default:
254 break;
255 }
256
257 return true;
258}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400259EXPORT_SYMBOL(ath9k_hw_set_txq_props);
Sujithf1dc5602008-10-29 10:16:30 +0530260
Sujithcbe61d82009-02-09 13:27:12 +0530261bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
Sujithf1dc5602008-10-29 10:16:30 +0530262 struct ath9k_tx_queue_info *qinfo)
263{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700264 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530265 struct ath9k_tx_queue_info *qi;
266
Sujith2660b812009-02-09 13:27:26 +0530267 qi = &ah->txq[q];
Sujithf1dc5602008-10-29 10:16:30 +0530268 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800269 ath_dbg(common, QUEUE,
Joe Perches226afe62010-12-02 19:12:37 -0800270 "Get TXQ properties, inactive queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530271 return false;
272 }
273
274 qinfo->tqi_qflags = qi->tqi_qflags;
275 qinfo->tqi_ver = qi->tqi_ver;
276 qinfo->tqi_subtype = qi->tqi_subtype;
277 qinfo->tqi_qflags = qi->tqi_qflags;
278 qinfo->tqi_priority = qi->tqi_priority;
279 qinfo->tqi_aifs = qi->tqi_aifs;
280 qinfo->tqi_cwmin = qi->tqi_cwmin;
281 qinfo->tqi_cwmax = qi->tqi_cwmax;
282 qinfo->tqi_shretry = qi->tqi_shretry;
283 qinfo->tqi_lgretry = qi->tqi_lgretry;
284 qinfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
285 qinfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
286 qinfo->tqi_burstTime = qi->tqi_burstTime;
287 qinfo->tqi_readyTime = qi->tqi_readyTime;
288
289 return true;
290}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400291EXPORT_SYMBOL(ath9k_hw_get_txq_props);
Sujithf1dc5602008-10-29 10:16:30 +0530292
Sujithcbe61d82009-02-09 13:27:12 +0530293int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
Sujithf1dc5602008-10-29 10:16:30 +0530294 const struct ath9k_tx_queue_info *qinfo)
295{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700296 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530297 struct ath9k_tx_queue_info *qi;
Sujithf1dc5602008-10-29 10:16:30 +0530298 int q;
299
300 switch (type) {
301 case ATH9K_TX_QUEUE_BEACON:
Felix Fietkauf4c607d2011-03-23 20:57:28 +0100302 q = ATH9K_NUM_TX_QUEUES - 1;
Sujithf1dc5602008-10-29 10:16:30 +0530303 break;
304 case ATH9K_TX_QUEUE_CAB:
Felix Fietkauf4c607d2011-03-23 20:57:28 +0100305 q = ATH9K_NUM_TX_QUEUES - 2;
Sujithf1dc5602008-10-29 10:16:30 +0530306 break;
307 case ATH9K_TX_QUEUE_PSPOLL:
308 q = 1;
309 break;
310 case ATH9K_TX_QUEUE_UAPSD:
Felix Fietkauf4c607d2011-03-23 20:57:28 +0100311 q = ATH9K_NUM_TX_QUEUES - 3;
Sujithf1dc5602008-10-29 10:16:30 +0530312 break;
313 case ATH9K_TX_QUEUE_DATA:
Felix Fietkauf4c607d2011-03-23 20:57:28 +0100314 for (q = 0; q < ATH9K_NUM_TX_QUEUES; q++)
Sujith2660b812009-02-09 13:27:26 +0530315 if (ah->txq[q].tqi_type ==
Sujithf1dc5602008-10-29 10:16:30 +0530316 ATH9K_TX_QUEUE_INACTIVE)
317 break;
Felix Fietkauf4c607d2011-03-23 20:57:28 +0100318 if (q == ATH9K_NUM_TX_QUEUES) {
Joe Perches38002762010-12-02 19:12:36 -0800319 ath_err(common, "No available TX queue\n");
Sujithf1dc5602008-10-29 10:16:30 +0530320 return -1;
321 }
322 break;
323 default:
Joe Perches38002762010-12-02 19:12:36 -0800324 ath_err(common, "Invalid TX queue type: %u\n", type);
Sujithf1dc5602008-10-29 10:16:30 +0530325 return -1;
326 }
327
Joe Perchesd2182b62011-12-15 14:55:53 -0800328 ath_dbg(common, QUEUE, "Setup TX queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530329
Sujith2660b812009-02-09 13:27:26 +0530330 qi = &ah->txq[q];
Sujithf1dc5602008-10-29 10:16:30 +0530331 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
Joe Perches38002762010-12-02 19:12:36 -0800332 ath_err(common, "TX queue: %u already active\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530333 return -1;
334 }
335 memset(qi, 0, sizeof(struct ath9k_tx_queue_info));
336 qi->tqi_type = type;
Rajkumar Manoharan479c6892011-08-13 10:28:12 +0530337 qi->tqi_physCompBuf = qinfo->tqi_physCompBuf;
338 (void) ath9k_hw_set_txq_props(ah, q, qinfo);
Sujithf1dc5602008-10-29 10:16:30 +0530339
340 return q;
341}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400342EXPORT_SYMBOL(ath9k_hw_setuptxqueue);
Sujithf1dc5602008-10-29 10:16:30 +0530343
Felix Fietkau7e030722012-03-14 16:40:21 +0100344static void ath9k_hw_clear_queue_interrupts(struct ath_hw *ah, u32 q)
345{
346 ah->txok_interrupt_mask &= ~(1 << q);
347 ah->txerr_interrupt_mask &= ~(1 << q);
348 ah->txdesc_interrupt_mask &= ~(1 << q);
349 ah->txeol_interrupt_mask &= ~(1 << q);
350 ah->txurn_interrupt_mask &= ~(1 << q);
351}
352
Sujithcbe61d82009-02-09 13:27:12 +0530353bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +0530354{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700355 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530356 struct ath9k_tx_queue_info *qi;
357
Sujith2660b812009-02-09 13:27:26 +0530358 qi = &ah->txq[q];
Sujithf1dc5602008-10-29 10:16:30 +0530359 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800360 ath_dbg(common, QUEUE, "Release TXQ, inactive queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530361 return false;
362 }
363
Joe Perchesd2182b62011-12-15 14:55:53 -0800364 ath_dbg(common, QUEUE, "Release TX queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530365
366 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
Felix Fietkau7e030722012-03-14 16:40:21 +0100367 ath9k_hw_clear_queue_interrupts(ah, q);
Sujithf1dc5602008-10-29 10:16:30 +0530368 ath9k_hw_set_txq_interrupts(ah, qi);
369
370 return true;
371}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400372EXPORT_SYMBOL(ath9k_hw_releasetxqueue);
Sujithf1dc5602008-10-29 10:16:30 +0530373
Sujithcbe61d82009-02-09 13:27:12 +0530374bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
Sujithf1dc5602008-10-29 10:16:30 +0530375{
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700376 struct ath_common *common = ath9k_hw_common(ah);
Sujithf1dc5602008-10-29 10:16:30 +0530377 struct ath9k_tx_queue_info *qi;
378 u32 cwMin, chanCwMin, value;
379
Sujith2660b812009-02-09 13:27:26 +0530380 qi = &ah->txq[q];
Sujithf1dc5602008-10-29 10:16:30 +0530381 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800382 ath_dbg(common, QUEUE, "Reset TXQ, inactive queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530383 return true;
384 }
385
Joe Perchesd2182b62011-12-15 14:55:53 -0800386 ath_dbg(common, QUEUE, "Reset TX queue: %u\n", q);
Sujithf1dc5602008-10-29 10:16:30 +0530387
388 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
Felix Fietkau1a5e6322013-10-11 23:30:54 +0200389 chanCwMin = INIT_CWMIN;
Sujithf1dc5602008-10-29 10:16:30 +0530390
391 for (cwMin = 1; cwMin < chanCwMin; cwMin = (cwMin << 1) | 1);
392 } else
393 cwMin = qi->tqi_cwmin;
394
Sujith7d0d0df2010-04-16 11:53:57 +0530395 ENABLE_REGWRITE_BUFFER(ah);
396
Sujithf1dc5602008-10-29 10:16:30 +0530397 REG_WRITE(ah, AR_DLCL_IFS(q),
398 SM(cwMin, AR_D_LCL_IFS_CWMIN) |
399 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) |
400 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
401
402 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
403 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH) |
404 SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG) |
405 SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH));
406
407 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
Rajkumar Manoharan94333f52011-05-09 19:11:27 +0530408
Felix Fietkau86c157b2013-05-23 12:20:56 +0200409 if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah))
Rajkumar Manoharan94333f52011-05-09 19:11:27 +0530410 REG_WRITE(ah, AR_DMISC(q),
411 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
412 else
413 REG_WRITE(ah, AR_DMISC(q),
414 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
Sujithf1dc5602008-10-29 10:16:30 +0530415
416 if (qi->tqi_cbrPeriod) {
417 REG_WRITE(ah, AR_QCBRCFG(q),
418 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL) |
419 SM(qi->tqi_cbrOverflowLimit, AR_Q_CBRCFG_OVF_THRESH));
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100420 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_FSP_CBR |
421 (qi->tqi_cbrOverflowLimit ?
422 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN : 0));
Sujithf1dc5602008-10-29 10:16:30 +0530423 }
424 if (qi->tqi_readyTime && (qi->tqi_type != ATH9K_TX_QUEUE_CAB)) {
425 REG_WRITE(ah, AR_QRDYTIMECFG(q),
426 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
427 AR_Q_RDYTIMECFG_EN);
428 }
429
430 REG_WRITE(ah, AR_DCHNTIME(q),
431 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
432 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
433
434 if (qi->tqi_burstTime
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100435 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE))
436 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_RDYTIME_EXP_POLICY);
Sujithf1dc5602008-10-29 10:16:30 +0530437
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100438 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE)
439 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
Sujith7d0d0df2010-04-16 11:53:57 +0530440
441 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530442
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100443 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE)
444 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_FRAG_BKOFF_EN);
445
Sujithf1dc5602008-10-29 10:16:30 +0530446 switch (qi->tqi_type) {
447 case ATH9K_TX_QUEUE_BEACON:
Sujith7d0d0df2010-04-16 11:53:57 +0530448 ENABLE_REGWRITE_BUFFER(ah);
449
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100450 REG_SET_BIT(ah, AR_QMISC(q),
451 AR_Q_MISC_FSP_DBA_GATED
452 | AR_Q_MISC_BEACON_USE
453 | AR_Q_MISC_CBR_INCR_DIS1);
Sujithf1dc5602008-10-29 10:16:30 +0530454
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100455 REG_SET_BIT(ah, AR_DMISC(q),
456 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
Sujithf1dc5602008-10-29 10:16:30 +0530457 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100458 | AR_D_MISC_BEACON_USE
459 | AR_D_MISC_POST_FR_BKOFF_DIS);
Sujith7d0d0df2010-04-16 11:53:57 +0530460
461 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530462
Luis R. Rodriguez9a2af882010-06-14 20:17:36 -0400463 /*
464 * cwmin and cwmax should be 0 for beacon queue
465 * but not for IBSS as we would create an imbalance
466 * on beaconing fairness for participating nodes.
467 */
468 if (AR_SREV_9300_20_OR_LATER(ah) &&
469 ah->opmode != NL80211_IFTYPE_ADHOC) {
Luis R. Rodriguez3deb4da2010-04-15 17:39:32 -0400470 REG_WRITE(ah, AR_DLCL_IFS(q), SM(0, AR_D_LCL_IFS_CWMIN)
471 | SM(0, AR_D_LCL_IFS_CWMAX)
472 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
473 }
Sujithf1dc5602008-10-29 10:16:30 +0530474 break;
475 case ATH9K_TX_QUEUE_CAB:
Sujith7d0d0df2010-04-16 11:53:57 +0530476 ENABLE_REGWRITE_BUFFER(ah);
477
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100478 REG_SET_BIT(ah, AR_QMISC(q),
479 AR_Q_MISC_FSP_DBA_GATED
480 | AR_Q_MISC_CBR_INCR_DIS1
481 | AR_Q_MISC_CBR_INCR_DIS0);
Sujithf1dc5602008-10-29 10:16:30 +0530482 value = (qi->tqi_readyTime -
Sujith2660b812009-02-09 13:27:26 +0530483 (ah->config.sw_beacon_response_time -
Felix Fietkau49685632013-12-14 18:03:42 +0100484 ah->config.dma_beacon_response_time)) * 1024;
Sujithf1dc5602008-10-29 10:16:30 +0530485 REG_WRITE(ah, AR_QRDYTIMECFG(q),
486 value | AR_Q_RDYTIMECFG_EN);
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100487 REG_SET_BIT(ah, AR_DMISC(q),
488 (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
Sujithf1dc5602008-10-29 10:16:30 +0530489 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
Sujith7d0d0df2010-04-16 11:53:57 +0530490
491 REGWRITE_BUFFER_FLUSH(ah);
Sujith7d0d0df2010-04-16 11:53:57 +0530492
Sujithf1dc5602008-10-29 10:16:30 +0530493 break;
494 case ATH9K_TX_QUEUE_PSPOLL:
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100495 REG_SET_BIT(ah, AR_QMISC(q), AR_Q_MISC_CBR_INCR_DIS1);
Sujithf1dc5602008-10-29 10:16:30 +0530496 break;
497 case ATH9K_TX_QUEUE_UAPSD:
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100498 REG_SET_BIT(ah, AR_DMISC(q), AR_D_MISC_POST_FR_BKOFF_DIS);
Sujithf1dc5602008-10-29 10:16:30 +0530499 break;
500 default:
501 break;
502 }
503
504 if (qi->tqi_intFlags & ATH9K_TXQ_USE_LOCKOUT_BKOFF_DIS) {
Felix Fietkauca7a4de2011-03-23 20:57:26 +0100505 REG_SET_BIT(ah, AR_DMISC(q),
506 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
507 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
508 AR_D_MISC_POST_FR_BKOFF_DIS);
Sujithf1dc5602008-10-29 10:16:30 +0530509 }
510
Luis R. Rodriguez79de2372010-04-15 17:39:31 -0400511 if (AR_SREV_9300_20_OR_LATER(ah))
512 REG_WRITE(ah, AR_Q_DESC_CRCCHK, AR_Q_DESC_CRCCHK_EN);
513
Felix Fietkau7e030722012-03-14 16:40:21 +0100514 ath9k_hw_clear_queue_interrupts(ah, q);
Felix Fietkauce8fdf62012-03-14 16:40:22 +0100515 if (qi->tqi_qflags & TXQ_FLAG_TXINT_ENABLE) {
Sujith2660b812009-02-09 13:27:26 +0530516 ah->txok_interrupt_mask |= 1 << q;
Sujith2660b812009-02-09 13:27:26 +0530517 ah->txerr_interrupt_mask |= 1 << q;
Felix Fietkauce8fdf62012-03-14 16:40:22 +0100518 }
Sujithf1dc5602008-10-29 10:16:30 +0530519 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
Sujith2660b812009-02-09 13:27:26 +0530520 ah->txdesc_interrupt_mask |= 1 << q;
Sujithf1dc5602008-10-29 10:16:30 +0530521 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
Sujith2660b812009-02-09 13:27:26 +0530522 ah->txeol_interrupt_mask |= 1 << q;
Sujithf1dc5602008-10-29 10:16:30 +0530523 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
Sujith2660b812009-02-09 13:27:26 +0530524 ah->txurn_interrupt_mask |= 1 << q;
Sujithf1dc5602008-10-29 10:16:30 +0530525 ath9k_hw_set_txq_interrupts(ah, qi);
526
527 return true;
528}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400529EXPORT_SYMBOL(ath9k_hw_resettxqueue);
Sujithf1dc5602008-10-29 10:16:30 +0530530
Sujithcbe61d82009-02-09 13:27:12 +0530531int ath9k_hw_rxprocdesc(struct ath_hw *ah, struct ath_desc *ds,
Rajkumar Manoharan3de21112011-08-13 10:28:11 +0530532 struct ath_rx_status *rs)
Sujithf1dc5602008-10-29 10:16:30 +0530533{
534 struct ar5416_desc ads;
535 struct ar5416_desc *adsp = AR5416DESC(ds);
536 u32 phyerr;
537
538 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
539 return -EINPROGRESS;
540
541 ads.u.rx = adsp->u.rx;
542
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700543 rs->rs_status = 0;
544 rs->rs_flags = 0;
Oleksij Rempelab276102013-05-24 12:18:30 +0200545 rs->flag = 0;
Sujithf1dc5602008-10-29 10:16:30 +0530546
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700547 rs->rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
548 rs->rs_tstamp = ads.AR_RcvTimestamp;
Sujithf1dc5602008-10-29 10:16:30 +0530549
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400550 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr) {
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700551 rs->rs_rssi = ATH9K_RSSI_BAD;
Felix Fietkaue45e91d2013-12-14 18:03:36 +0100552 rs->rs_rssi_ctl[0] = ATH9K_RSSI_BAD;
553 rs->rs_rssi_ctl[1] = ATH9K_RSSI_BAD;
554 rs->rs_rssi_ctl[2] = ATH9K_RSSI_BAD;
555 rs->rs_rssi_ext[0] = ATH9K_RSSI_BAD;
556 rs->rs_rssi_ext[1] = ATH9K_RSSI_BAD;
557 rs->rs_rssi_ext[2] = ATH9K_RSSI_BAD;
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400558 } else {
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700559 rs->rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
Felix Fietkaue45e91d2013-12-14 18:03:36 +0100560 rs->rs_rssi_ctl[0] = MS(ads.ds_rxstatus0,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400561 AR_RxRSSIAnt00);
Felix Fietkaue45e91d2013-12-14 18:03:36 +0100562 rs->rs_rssi_ctl[1] = MS(ads.ds_rxstatus0,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400563 AR_RxRSSIAnt01);
Felix Fietkaue45e91d2013-12-14 18:03:36 +0100564 rs->rs_rssi_ctl[2] = MS(ads.ds_rxstatus0,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400565 AR_RxRSSIAnt02);
Felix Fietkaue45e91d2013-12-14 18:03:36 +0100566 rs->rs_rssi_ext[0] = MS(ads.ds_rxstatus4,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400567 AR_RxRSSIAnt10);
Felix Fietkaue45e91d2013-12-14 18:03:36 +0100568 rs->rs_rssi_ext[1] = MS(ads.ds_rxstatus4,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400569 AR_RxRSSIAnt11);
Felix Fietkaue45e91d2013-12-14 18:03:36 +0100570 rs->rs_rssi_ext[2] = MS(ads.ds_rxstatus4,
Senthil Balasubramaniandd8b15b2009-07-14 20:17:08 -0400571 AR_RxRSSIAnt12);
572 }
Sujithf1dc5602008-10-29 10:16:30 +0530573 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700574 rs->rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
Sujithf1dc5602008-10-29 10:16:30 +0530575 else
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700576 rs->rs_keyix = ATH9K_RXKEYIX_INVALID;
Sujithf1dc5602008-10-29 10:16:30 +0530577
Felix Fietkau1b8714f2011-09-15 14:25:35 +0200578 rs->rs_rate = MS(ads.ds_rxstatus0, AR_RxRate);
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700579 rs->rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
Sujithf1dc5602008-10-29 10:16:30 +0530580
Sujith Manoharan009af8f2013-08-14 21:15:55 +0530581 rs->rs_firstaggr = (ads.ds_rxstatus8 & AR_RxFirstAggr) ? 1 : 0;
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700582 rs->rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
Sujith Manoharan009af8f2013-08-14 21:15:55 +0530583 rs->rs_moreaggr = (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700584 rs->rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
Oleksij Rempelab276102013-05-24 12:18:30 +0200585
586 /* directly mapped flags for ieee80211_rx_status */
587 rs->flag |=
588 (ads.ds_rxstatus3 & AR_GI) ? RX_FLAG_SHORT_GI : 0;
589 rs->flag |=
590 (ads.ds_rxstatus3 & AR_2040) ? RX_FLAG_40MHZ : 0;
Oleksij Rempelb0a1ae92013-05-24 20:30:59 +0200591 if (AR_SREV_9280_20_OR_LATER(ah))
592 rs->flag |=
593 (ads.ds_rxstatus3 & AR_STBC) ?
594 /* we can only Nss=1 STBC */
595 (1 << RX_FLAG_STBC_SHIFT) : 0;
Sujithf1dc5602008-10-29 10:16:30 +0530596
597 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700598 rs->rs_flags |= ATH9K_RX_DELIM_CRC_PRE;
Sujithf1dc5602008-10-29 10:16:30 +0530599 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700600 rs->rs_flags |= ATH9K_RX_DELIM_CRC_POST;
Sujithf1dc5602008-10-29 10:16:30 +0530601 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700602 rs->rs_flags |= ATH9K_RX_DECRYPT_BUSY;
Sujithf1dc5602008-10-29 10:16:30 +0530603
604 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
Felix Fietkau115dad72011-01-14 00:06:27 +0100605 /*
606 * Treat these errors as mutually exclusive to avoid spurious
607 * extra error reports from the hardware. If a CRC error is
608 * reported, then decryption and MIC errors are irrelevant,
609 * the frame is going to be dropped either way
610 */
Simon Wunderlich3a325562013-01-23 17:38:06 +0100611 if (ads.ds_rxstatus8 & AR_PHYErr) {
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700612 rs->rs_status |= ATH9K_RXERR_PHY;
Sujithf1dc5602008-10-29 10:16:30 +0530613 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700614 rs->rs_phyerr = phyerr;
Simon Wunderlich3a325562013-01-23 17:38:06 +0100615 } else if (ads.ds_rxstatus8 & AR_CRCErr)
616 rs->rs_status |= ATH9K_RXERR_CRC;
617 else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700618 rs->rs_status |= ATH9K_RXERR_DECRYPT;
Felix Fietkau115dad72011-01-14 00:06:27 +0100619 else if (ads.ds_rxstatus8 & AR_MichaelErr)
Felix Fietkau8e6f5aa2010-03-29 20:09:27 -0700620 rs->rs_status |= ATH9K_RXERR_MIC;
Felix Fietkau3747c3e2013-04-08 00:04:12 +0200621 } else {
622 if (ads.ds_rxstatus8 &
623 (AR_CRCErr | AR_PHYErr | AR_DecryptCRCErr | AR_MichaelErr))
624 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC;
625
626 /* Only up to MCS16 supported, everything above is invalid */
627 if (rs->rs_rate >= 0x90)
628 rs->rs_status |= ATH9K_RXERR_CORRUPT_DESC;
Sujithf1dc5602008-10-29 10:16:30 +0530629 }
630
Felix Fietkau7a532fe2012-01-14 15:08:34 +0100631 if (ads.ds_rxstatus8 & AR_KeyMiss)
632 rs->rs_status |= ATH9K_RXERR_KEYMISS;
633
Sujithf1dc5602008-10-29 10:16:30 +0530634 return 0;
635}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400636EXPORT_SYMBOL(ath9k_hw_rxprocdesc);
Sujithf1dc5602008-10-29 10:16:30 +0530637
Luis R. Rodrigueze7824a52009-11-24 02:53:25 -0500638/*
639 * This can stop or re-enables RX.
640 *
641 * If bool is set this will kill any frame which is currently being
642 * transferred between the MAC and baseband and also prevent any new
643 * frames from getting started.
644 */
Sujithcbe61d82009-02-09 13:27:12 +0530645bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
Sujithf1dc5602008-10-29 10:16:30 +0530646{
647 u32 reg;
648
649 if (set) {
650 REG_SET_BIT(ah, AR_DIAG_SW,
651 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
652
Sujith0caa7b12009-02-16 13:23:20 +0530653 if (!ath9k_hw_wait(ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE,
654 0, AH_WAIT_TIMEOUT)) {
Sujithf1dc5602008-10-29 10:16:30 +0530655 REG_CLR_BIT(ah, AR_DIAG_SW,
656 (AR_DIAG_RX_DIS |
657 AR_DIAG_RX_ABORT));
658
659 reg = REG_READ(ah, AR_OBS_BUS_1);
Joe Perches38002762010-12-02 19:12:36 -0800660 ath_err(ath9k_hw_common(ah),
661 "RX failed to go idle in 10 ms RXSM=0x%x\n",
662 reg);
Sujithf1dc5602008-10-29 10:16:30 +0530663
664 return false;
665 }
666 } else {
667 REG_CLR_BIT(ah, AR_DIAG_SW,
668 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
669 }
670
671 return true;
672}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400673EXPORT_SYMBOL(ath9k_hw_setrxabort);
Sujithf1dc5602008-10-29 10:16:30 +0530674
Sujithcbe61d82009-02-09 13:27:12 +0530675void ath9k_hw_putrxbuf(struct ath_hw *ah, u32 rxdp)
Sujithf1dc5602008-10-29 10:16:30 +0530676{
677 REG_WRITE(ah, AR_RXDP, rxdp);
678}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400679EXPORT_SYMBOL(ath9k_hw_putrxbuf);
Sujithf1dc5602008-10-29 10:16:30 +0530680
Luis R. Rodriguez40346b62010-06-12 00:33:44 -0400681void ath9k_hw_startpcureceive(struct ath_hw *ah, bool is_scanning)
Sujithf1dc5602008-10-29 10:16:30 +0530682{
Sujithf1dc5602008-10-29 10:16:30 +0530683 ath9k_enable_mib_counters(ah);
684
Luis R. Rodriguez40346b62010-06-12 00:33:44 -0400685 ath9k_ani_reset(ah, is_scanning);
Senthil Balasubramaniane7594072008-12-08 19:43:48 +0530686
Senthil Balasubramanian8aa15e12008-12-08 19:43:50 +0530687 REG_CLR_BIT(ah, AR_DIAG_SW, (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
Sujithf1dc5602008-10-29 10:16:30 +0530688}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400689EXPORT_SYMBOL(ath9k_hw_startpcureceive);
Sujithf1dc5602008-10-29 10:16:30 +0530690
Vasanthakumar Thiagarajan9b9cc612010-04-15 17:39:41 -0400691void ath9k_hw_abortpcurecv(struct ath_hw *ah)
692{
693 REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_ABORT | AR_DIAG_RX_DIS);
694
695 ath9k_hw_disable_mib_counters(ah);
696}
697EXPORT_SYMBOL(ath9k_hw_abortpcurecv);
698
Felix Fietkau5882da022011-04-08 20:13:18 +0200699bool ath9k_hw_stopdmarecv(struct ath_hw *ah, bool *reset)
Sujithf1dc5602008-10-29 10:16:30 +0530700{
Sujith0caa7b12009-02-16 13:23:20 +0530701#define AH_RX_STOP_DMA_TIMEOUT 10000 /* usec */
Luis R. Rodriguezc46917b2009-09-13 02:42:02 -0700702 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau5882da022011-04-08 20:13:18 +0200703 u32 mac_status, last_mac_status = 0;
Sujith0caa7b12009-02-16 13:23:20 +0530704 int i;
705
Felix Fietkau5882da022011-04-08 20:13:18 +0200706 /* Enable access to the DMA observation bus */
707 REG_WRITE(ah, AR_MACMISC,
708 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
709 (AR_MACMISC_MISC_OBS_BUS_1 <<
710 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
711
Sujithf1dc5602008-10-29 10:16:30 +0530712 REG_WRITE(ah, AR_CR, AR_CR_RXD);
713
Sujith0caa7b12009-02-16 13:23:20 +0530714 /* Wait for rx enable bit to go low */
715 for (i = AH_RX_STOP_DMA_TIMEOUT / AH_TIME_QUANTUM; i != 0; i--) {
716 if ((REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
717 break;
Felix Fietkau5882da022011-04-08 20:13:18 +0200718
719 if (!AR_SREV_9300_20_OR_LATER(ah)) {
720 mac_status = REG_READ(ah, AR_DMADBG_7) & 0x7f0;
721 if (mac_status == 0x1c0 && mac_status == last_mac_status) {
722 *reset = true;
723 break;
724 }
725
726 last_mac_status = mac_status;
727 }
728
Sujith0caa7b12009-02-16 13:23:20 +0530729 udelay(AH_TIME_QUANTUM);
730 }
731
732 if (i == 0) {
Joe Perches38002762010-12-02 19:12:36 -0800733 ath_err(common,
Felix Fietkau5882da022011-04-08 20:13:18 +0200734 "DMA failed to stop in %d ms AR_CR=0x%08x AR_DIAG_SW=0x%08x DMADBG_7=0x%08x\n",
Joe Perches38002762010-12-02 19:12:36 -0800735 AH_RX_STOP_DMA_TIMEOUT / 1000,
736 REG_READ(ah, AR_CR),
Felix Fietkau5882da022011-04-08 20:13:18 +0200737 REG_READ(ah, AR_DIAG_SW),
738 REG_READ(ah, AR_DMADBG_7));
Sujithf1dc5602008-10-29 10:16:30 +0530739 return false;
740 } else {
741 return true;
742 }
Sujith0caa7b12009-02-16 13:23:20 +0530743
Sujith0caa7b12009-02-16 13:23:20 +0530744#undef AH_RX_STOP_DMA_TIMEOUT
Sujithf1dc5602008-10-29 10:16:30 +0530745}
Luis R. Rodriguez7322fd12009-09-23 23:07:00 -0400746EXPORT_SYMBOL(ath9k_hw_stopdmarecv);
Luis R. Rodriguez536b3a72009-10-06 21:19:11 -0400747
748int ath9k_hw_beaconq_setup(struct ath_hw *ah)
749{
750 struct ath9k_tx_queue_info qi;
751
752 memset(&qi, 0, sizeof(qi));
753 qi.tqi_aifs = 1;
754 qi.tqi_cwmin = 0;
755 qi.tqi_cwmax = 0;
Felix Fietkau627e67a2012-02-27 19:58:41 +0100756
757 if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
Felix Fietkauce8fdf62012-03-14 16:40:22 +0100758 qi.tqi_qflags = TXQ_FLAG_TXINT_ENABLE;
Felix Fietkau627e67a2012-02-27 19:58:41 +0100759
Luis R. Rodriguez536b3a72009-10-06 21:19:11 -0400760 return ath9k_hw_setuptxqueue(ah, ATH9K_TX_QUEUE_BEACON, &qi);
761}
762EXPORT_SYMBOL(ath9k_hw_beaconq_setup);
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400763
764bool ath9k_hw_intrpend(struct ath_hw *ah)
765{
766 u32 host_isr;
767
768 if (AR_SREV_9100(ah))
769 return true;
770
771 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
Mohammed Shafi Shajakhane3584812011-11-30 10:41:20 +0530772
773 if (((host_isr & AR_INTR_MAC_IRQ) ||
774 (host_isr & AR_INTR_ASYNC_MASK_MCI)) &&
775 (host_isr != AR_INTR_SPURIOUS))
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400776 return true;
777
778 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
779 if ((host_isr & AR_INTR_SYNC_DEFAULT)
780 && (host_isr != AR_INTR_SPURIOUS))
781 return true;
782
783 return false;
784}
785EXPORT_SYMBOL(ath9k_hw_intrpend);
786
Felix Fietkauf41a9b32012-08-08 16:25:03 +0200787void ath9k_hw_kill_interrupts(struct ath_hw *ah)
Felix Fietkau4df30712010-11-08 20:54:47 +0100788{
789 struct ath_common *common = ath9k_hw_common(ah);
790
Joe Perchesd2182b62011-12-15 14:55:53 -0800791 ath_dbg(common, INTERRUPT, "disable IER\n");
Felix Fietkau4df30712010-11-08 20:54:47 +0100792 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
793 (void) REG_READ(ah, AR_IER);
794 if (!AR_SREV_9100(ah)) {
795 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
796 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
797
798 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
799 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
800 }
801}
Felix Fietkauf41a9b32012-08-08 16:25:03 +0200802EXPORT_SYMBOL(ath9k_hw_kill_interrupts);
803
804void ath9k_hw_disable_interrupts(struct ath_hw *ah)
805{
806 if (!(ah->imask & ATH9K_INT_GLOBAL))
807 atomic_set(&ah->intr_ref_cnt, -1);
808 else
809 atomic_dec(&ah->intr_ref_cnt);
810
811 ath9k_hw_kill_interrupts(ah);
812}
Felix Fietkau4df30712010-11-08 20:54:47 +0100813EXPORT_SYMBOL(ath9k_hw_disable_interrupts);
814
815void ath9k_hw_enable_interrupts(struct ath_hw *ah)
816{
817 struct ath_common *common = ath9k_hw_common(ah);
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530818 u32 sync_default = AR_INTR_SYNC_DEFAULT;
Mohammed Shafi Shajakhanf229f812011-11-30 10:41:19 +0530819 u32 async_mask;
Felix Fietkau4df30712010-11-08 20:54:47 +0100820
821 if (!(ah->imask & ATH9K_INT_GLOBAL))
822 return;
823
Rajkumar Manoharane8fe7332011-08-05 18:59:41 +0530824 if (!atomic_inc_and_test(&ah->intr_ref_cnt)) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800825 ath_dbg(common, INTERRUPT, "Do not enable IER ref count %d\n",
Rajkumar Manoharane8fe7332011-08-05 18:59:41 +0530826 atomic_read(&ah->intr_ref_cnt));
827 return;
828 }
829
Gabor Juhos3b8a0572012-07-03 19:13:29 +0200830 if (AR_SREV_9340(ah) || AR_SREV_9550(ah))
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530831 sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
832
Mohammed Shafi Shajakhanf229f812011-11-30 10:41:19 +0530833 async_mask = AR_INTR_MAC_IRQ;
834
835 if (ah->imask & ATH9K_INT_MCI)
836 async_mask |= AR_INTR_ASYNC_MASK_MCI;
837
Joe Perchesd2182b62011-12-15 14:55:53 -0800838 ath_dbg(common, INTERRUPT, "enable IER\n");
Felix Fietkau4df30712010-11-08 20:54:47 +0100839 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
840 if (!AR_SREV_9100(ah)) {
Mohammed Shafi Shajakhanf229f812011-11-30 10:41:19 +0530841 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, async_mask);
842 REG_WRITE(ah, AR_INTR_ASYNC_MASK, async_mask);
Felix Fietkau4df30712010-11-08 20:54:47 +0100843
Vasanthakumar Thiagarajan79d1d2b2011-04-19 19:29:19 +0530844 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, sync_default);
845 REG_WRITE(ah, AR_INTR_SYNC_MASK, sync_default);
Felix Fietkau4df30712010-11-08 20:54:47 +0100846 }
Joe Perchesd2182b62011-12-15 14:55:53 -0800847 ath_dbg(common, INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
Joe Perches226afe62010-12-02 19:12:37 -0800848 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
Felix Fietkau4df30712010-11-08 20:54:47 +0100849}
850EXPORT_SYMBOL(ath9k_hw_enable_interrupts);
851
Felix Fietkau72d874c2011-10-08 20:06:19 +0200852void ath9k_hw_set_interrupts(struct ath_hw *ah)
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400853{
Felix Fietkau72d874c2011-10-08 20:06:19 +0200854 enum ath9k_int ints = ah->imask;
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400855 u32 mask, mask2;
856 struct ath9k_hw_capabilities *pCap = &ah->caps;
857 struct ath_common *common = ath9k_hw_common(ah);
858
Felix Fietkau4df30712010-11-08 20:54:47 +0100859 if (!(ints & ATH9K_INT_GLOBAL))
Stanislaw Gruszka385918c2011-02-21 15:02:41 +0100860 ath9k_hw_disable_interrupts(ah);
Felix Fietkau4df30712010-11-08 20:54:47 +0100861
Joe Perchesd2182b62011-12-15 14:55:53 -0800862 ath_dbg(common, INTERRUPT, "New interrupt mask 0x%x\n", ints);
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400863
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400864 mask = ints & ATH9K_INT_COMMON;
865 mask2 = 0;
866
867 if (ints & ATH9K_INT_TX) {
868 if (ah->config.tx_intr_mitigation)
869 mask |= AR_IMR_TXMINTR | AR_IMR_TXINTM;
Luis R. Rodriguez5bea4002010-04-26 15:04:41 -0400870 else {
871 if (ah->txok_interrupt_mask)
872 mask |= AR_IMR_TXOK;
873 if (ah->txdesc_interrupt_mask)
874 mask |= AR_IMR_TXDESC;
875 }
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400876 if (ah->txerr_interrupt_mask)
877 mask |= AR_IMR_TXERR;
878 if (ah->txeol_interrupt_mask)
879 mask |= AR_IMR_TXEOL;
880 }
881 if (ints & ATH9K_INT_RX) {
882 if (AR_SREV_9300_20_OR_LATER(ah)) {
883 mask |= AR_IMR_RXERR | AR_IMR_RXOK_HP;
884 if (ah->config.rx_intr_mitigation) {
885 mask &= ~AR_IMR_RXOK_LP;
886 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
887 } else {
888 mask |= AR_IMR_RXOK_LP;
889 }
890 } else {
891 if (ah->config.rx_intr_mitigation)
892 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
893 else
894 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
895 }
896 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
897 mask |= AR_IMR_GENTMR;
898 }
899
Vivek Natarajanf78eb652011-04-26 10:39:54 +0530900 if (ints & ATH9K_INT_GENTIMER)
901 mask |= AR_IMR_GENTMR;
902
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400903 if (ints & (ATH9K_INT_BMISC)) {
904 mask |= AR_IMR_BCNMISC;
905 if (ints & ATH9K_INT_TIM)
906 mask2 |= AR_IMR_S2_TIM;
907 if (ints & ATH9K_INT_DTIM)
908 mask2 |= AR_IMR_S2_DTIM;
909 if (ints & ATH9K_INT_DTIMSYNC)
910 mask2 |= AR_IMR_S2_DTIMSYNC;
911 if (ints & ATH9K_INT_CABEND)
912 mask2 |= AR_IMR_S2_CABEND;
913 if (ints & ATH9K_INT_TSFOOR)
914 mask2 |= AR_IMR_S2_TSFOOR;
915 }
916
917 if (ints & (ATH9K_INT_GTT | ATH9K_INT_CST)) {
918 mask |= AR_IMR_BCNMISC;
919 if (ints & ATH9K_INT_GTT)
920 mask2 |= AR_IMR_S2_GTT;
921 if (ints & ATH9K_INT_CST)
922 mask2 |= AR_IMR_S2_CST;
923 }
924
Sujith Manoharana6bb8602013-12-24 10:44:22 +0530925 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) {
926 if (ints & ATH9K_INT_BB_WATCHDOG) {
927 mask |= AR_IMR_BCNMISC;
928 mask2 |= AR_IMR_S2_BB_WATCHDOG;
929 }
930 }
931
Joe Perchesd2182b62011-12-15 14:55:53 -0800932 ath_dbg(common, INTERRUPT, "new IMR 0x%x\n", mask);
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400933 REG_WRITE(ah, AR_IMR, mask);
Sujith Manoharana6bb8602013-12-24 10:44:22 +0530934 ah->imrs2_reg &= ~(AR_IMR_S2_TIM |
935 AR_IMR_S2_DTIM |
936 AR_IMR_S2_DTIMSYNC |
937 AR_IMR_S2_CABEND |
938 AR_IMR_S2_CABTO |
939 AR_IMR_S2_TSFOOR |
940 AR_IMR_S2_GTT |
941 AR_IMR_S2_CST);
942
943 if (ah->config.hw_hang_checks & HW_BB_WATCHDOG) {
944 if (ints & ATH9K_INT_BB_WATCHDOG)
945 ah->imrs2_reg &= ~AR_IMR_S2_BB_WATCHDOG;
946 }
947
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400948 ah->imrs2_reg |= mask2;
949 REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
950
951 if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
952 if (ints & ATH9K_INT_TIM_TIMER)
953 REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
954 else
955 REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
956 }
957
Felix Fietkau4df30712010-11-08 20:54:47 +0100958 return;
Vasanthakumar Thiagarajan55e82df2010-04-15 17:39:06 -0400959}
960EXPORT_SYMBOL(ath9k_hw_set_interrupts);