Blame - arch/powerpc/include/asm/cputable.h - kernel/msm-5.4

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Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	1	#ifndef __ASM_POWERPC_CPUTABLE_H
				2	#define __ASM_POWERPC_CPUTABLE_H
				3
Adrian Bunk	d1cdcf2	2008-06-24 03:48:21 +1000	[diff] [blame]	4
				5	#include <asm/asm-compat.h>
Michael Ellerman	c5157e5	2008-06-24 11:32:39 +1000	[diff] [blame]	6	#include <asm/feature-fixups.h>
David Howells	c3617f7	2012-10-09 09:47:26 +0100	[diff] [blame]	7	#include <uapi/asm/cputable.h>
Adrian Bunk	d1cdcf2	2008-06-24 03:48:21 +1000	[diff] [blame]	8
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	9	#ifndef __ASSEMBLY__
				10
				11	/* This structure can grow, it's real size is used by head.S code
				12	* via the mkdefs mechanism.
				13	*/
				14	struct cpu_spec;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	15
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	16	typedef void (cpu_setup_t)(unsigned long offset, struct cpu_spec spec);
Olof Johansson	f39b7a5	2006-08-11 00:07:08 -0500	[diff] [blame]	17	typedef void (*cpu_restore_t)(void);
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	18
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	19	enum powerpc_oprofile_type {
Andy Whitcroft	7a45fb1	2006-01-13 12:35:49 +0000	[diff] [blame]	20	PPC_OPROFILE_INVALID = 0,
				21	PPC_OPROFILE_RS64 = 1,
				22	PPC_OPROFILE_POWER4 = 2,
				23	PPC_OPROFILE_G4 = 3,
Andy Fleming	39aef68	2008-02-04 18:27:55 -0600	[diff] [blame]	24	PPC_OPROFILE_FSL_EMB = 4,
Maynard Johnson	18f2190	2006-11-20 18:45:16 +0100	[diff] [blame]	25	PPC_OPROFILE_CELL = 5,
Olof Johansson	25fc530	2007-04-18 16:38:21 +1000	[diff] [blame]	26	PPC_OPROFILE_PA6T = 6,
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	27	};
				28
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	29	enum powerpc_pmc_type {
				30	PPC_PMC_DEFAULT = 0,
				31	PPC_PMC_IBM = 1,
				32	PPC_PMC_PA6T = 2,
Benjamin Herrenschmidt	b950bdd	2008-08-18 14:23:51 +1000	[diff] [blame]	33	PPC_PMC_G4 = 3,
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	34	};
				35
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	36	struct pt_regs;
				37
				38	extern int machine_check_generic(struct pt_regs *regs);
				39	extern int machine_check_4xx(struct pt_regs *regs);
				40	extern int machine_check_440A(struct pt_regs *regs);
Scott Wood	fe04b11	2010-04-08 00:38:22 -0500	[diff] [blame]	41	extern int machine_check_e500mc(struct pt_regs *regs);
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	42	extern int machine_check_e500(struct pt_regs *regs);
				43	extern int machine_check_e200(struct pt_regs *regs);
Dave Kleikamp	fc5e709	2010-03-05 03:43:18 +0000	[diff] [blame]	44	extern int machine_check_47x(struct pt_regs *regs);
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	45
Paul Mackerras	87a72f9	2007-10-04 14:18:01 +1000	[diff] [blame]	46	/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	47	struct cpu_spec {
				48	/* CPU is matched via (PVR & pvr_mask) == pvr_value */
				49	unsigned int pvr_mask;
				50	unsigned int pvr_value;
				51
				52	char *cpu_name;
				53	unsigned long cpu_features; /* Kernel features */
				54	unsigned int cpu_user_features; /* Userland features */
Michael Neuling	2171364	2013-04-17 17:33:11 +0000	[diff] [blame]	55	unsigned int cpu_user_features2; /* Userland features v2 */
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	56	unsigned int mmu_features; /* MMU features */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	57
				58	/* cache line sizes */
				59	unsigned int icache_bsize;
				60	unsigned int dcache_bsize;
				61
				62	/* number of performance monitor counters */
				63	unsigned int num_pmcs;
Olof Johansson	1bd2e5a	2007-01-28 21:23:54 -0600	[diff] [blame]	64	enum powerpc_pmc_type pmc_type;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	65
				66	/* this is called to initialize various CPU bits like L1 cache,
				67	* BHT, SPD, etc... from head.S before branching to identify_machine
				68	*/
				69	cpu_setup_t cpu_setup;
Olof Johansson	f39b7a5	2006-08-11 00:07:08 -0500	[diff] [blame]	70	/* Used to restore cpu setup on secondary processors and at resume */
				71	cpu_restore_t cpu_restore;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	72
				73	/* Used by oprofile userspace to select the right counters */
				74	char *oprofile_cpu_type;
				75
				76	/* Processor specific oprofile operations */
Anton Blanchard	32a3399	2006-01-09 15:41:31 +1100	[diff] [blame]	77	enum powerpc_oprofile_type oprofile_type;
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	78
Michael Neuling	e78dbc8	2006-06-08 14:42:34 +1000	[diff] [blame]	79	/* Bit locations inside the mmcra change */
				80	unsigned long oprofile_mmcra_sihv;
				81	unsigned long oprofile_mmcra_sipr;
				82
				83	/* Bits to clear during an oprofile exception */
				84	unsigned long oprofile_mmcra_clear;
				85
Paul Mackerras	80f15dc	2006-01-14 10:11:39 +1100	[diff] [blame]	86	/* Name of processor class, for the ELF AT_PLATFORM entry */
				87	char *platform;
Benjamin Herrenschmidt	47c0bd1	2007-12-21 15:39:21 +1100	[diff] [blame]	88
				89	/* Processor specific machine check handling. Return negative
				90	* if the error is fatal, 1 if it was fully recovered and 0 to
				91	* pass up (not CPU originated) */
				92	int (machine_check)(struct pt_regs regs);
Mahesh Salgaonkar	4c70341	2013-10-30 20:04:40 +0530	[diff] [blame]	93
				94	/*
				95	* Processor specific early machine check handler which is
				96	* called in real mode to handle SLB and TLB errors.
				97	*/
				98	long (machine_check_early)(struct pt_regs regs);
				99
Mahesh Salgaonkar	0440705	2013-10-30 20:04:56 +0530	[diff] [blame]	100	/*
				101	* Processor specific routine to flush tlbs.
				102	*/
				103	void (*flush_tlb)(unsigned long inval_selector);
				104
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	105	};
				106
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	107	extern struct cpu_spec *cur_cpu_spec;
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	108
Benjamin Herrenschmidt	42c4aaa	2006-10-24 16:42:40 +1000	[diff] [blame]	109	extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
				110
Paul Mackerras	974a76f	2006-11-10 20:38:53 +1100	[diff] [blame]	111	extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Benjamin Herrenschmidt	0909c8c	2006-10-20 11:47:18 +1000	[diff] [blame]	112	extern void do_feature_fixups(unsigned long value, void *fixup_start,
				113	void *fixup_end);
Paul Mackerras	9b6b563	2005-10-06 12:06:20 +1000	[diff] [blame]	114
Nathan Lynch	9115d13	2008-07-16 09:58:51 +1000	[diff] [blame]	115	extern const char *powerpc_base_platform;
				116
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	117	#endif /* __ASSEMBLY__ */
				118
				119	/* CPU kernel features */
				120
				121	/* Retain the 32b definitions all use bottom half of word */
Michael Neuling	cde4d49	2012-12-20 14:06:39 +0000	[diff] [blame]	122	#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x00000001)
				123	#define CPU_FTR_L2CR ASM_CONST(0x00000002)
				124	#define CPU_FTR_SPEC7450 ASM_CONST(0x00000004)
				125	#define CPU_FTR_ALTIVEC ASM_CONST(0x00000008)
				126	#define CPU_FTR_TAU ASM_CONST(0x00000010)
				127	#define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020)
				128	#define CPU_FTR_USE_TB ASM_CONST(0x00000040)
				129	#define CPU_FTR_L2CSR ASM_CONST(0x00000080)
				130	#define CPU_FTR_601 ASM_CONST(0x00000100)
				131	#define CPU_FTR_DBELL ASM_CONST(0x00000200)
				132	#define CPU_FTR_CAN_NAP ASM_CONST(0x00000400)
				133	#define CPU_FTR_L3CR ASM_CONST(0x00000800)
				134	#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x00001000)
				135	#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x00002000)
				136	#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x00004000)
				137	#define CPU_FTR_NO_DPM ASM_CONST(0x00008000)
				138	#define CPU_FTR_476_DD2 ASM_CONST(0x00010000)
				139	#define CPU_FTR_NEED_COHERENT ASM_CONST(0x00020000)
				140	#define CPU_FTR_NO_BTIC ASM_CONST(0x00040000)
				141	#define CPU_FTR_DEBUG_LVL_EXC ASM_CONST(0x00080000)
				142	#define CPU_FTR_NODSISRALIGN ASM_CONST(0x00100000)
				143	#define CPU_FTR_PPC_LE ASM_CONST(0x00200000)
				144	#define CPU_FTR_REAL_LE ASM_CONST(0x00400000)
				145	#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x00800000)
				146	#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x01000000)
				147	#define CPU_FTR_SPE ASM_CONST(0x02000000)
				148	#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x04000000)
				149	#define CPU_FTR_LWSYNC ASM_CONST(0x08000000)
				150	#define CPU_FTR_NOEXECUTE ASM_CONST(0x10000000)
				151	#define CPU_FTR_INDEXED_DCR ASM_CONST(0x20000000)
				152	#define CPU_FTR_EMB_HV ASM_CONST(0x40000000)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	153
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	154	/*
				155	* Add the 64-bit processor unique features in the top half of the word;
				156	* on 32-bit, make the names available but defined to be 0.
				157	*/
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	158	#ifdef __powerpc64__
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	159	#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	160	#else
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	161	#define LONG_ASM_CONST(x) 0
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	162	#endif
				163
Michael Neuling	1580b3b	2012-12-20 14:06:40 +0000	[diff] [blame]	164	#define CPU_FTR_HVMODE LONG_ASM_CONST(0x0000000100000000)
				165	#define CPU_FTR_ARCH_201 LONG_ASM_CONST(0x0000000200000000)
				166	#define CPU_FTR_ARCH_206 LONG_ASM_CONST(0x0000000400000000)
Michael Ellerman	1de2bd4	2013-04-30 20:17:02 +0000	[diff] [blame]	167	#define CPU_FTR_ARCH_207S LONG_ASM_CONST(0x0000000800000000)
Michael Neuling	1580b3b	2012-12-20 14:06:40 +0000	[diff] [blame]	168	#define CPU_FTR_IABR LONG_ASM_CONST(0x0000001000000000)
				169	#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000002000000000)
				170	#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000004000000000)
				171	#define CPU_FTR_SMT LONG_ASM_CONST(0x0000008000000000)
				172	#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000010000000000)
				173	#define CPU_FTR_PURR LONG_ASM_CONST(0x0000020000000000)
				174	#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000040000000000)
				175	#define CPU_FTR_SPURR LONG_ASM_CONST(0x0000080000000000)
				176	#define CPU_FTR_DSCR LONG_ASM_CONST(0x0000100000000000)
				177	#define CPU_FTR_VSX LONG_ASM_CONST(0x0000200000000000)
				178	#define CPU_FTR_SAO LONG_ASM_CONST(0x0000400000000000)
				179	#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0000800000000000)
				180	#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0001000000000000)
				181	#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0002000000000000)
				182	#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0004000000000000)
				183	#define CPU_FTR_POPCNTB LONG_ASM_CONST(0x0008000000000000)
				184	#define CPU_FTR_POPCNTD LONG_ASM_CONST(0x0010000000000000)
				185	#define CPU_FTR_ICSWX LONG_ASM_CONST(0x0020000000000000)
				186	#define CPU_FTR_VMX_COPY LONG_ASM_CONST(0x0040000000000000)
				187	#define CPU_FTR_TM LONG_ASM_CONST(0x0080000000000000)
Michael Ellerman	1de2bd4	2013-04-30 20:17:02 +0000	[diff] [blame]	188	#define CPU_FTR_CFAR LONG_ASM_CONST(0x0100000000000000)
Michael Neuling	1580b3b	2012-12-20 14:06:40 +0000	[diff] [blame]	189	#define CPU_FTR_HAS_PPR LONG_ASM_CONST(0x0200000000000000)
Michael Neuling	79879c1	2012-12-20 14:06:42 +0000	[diff] [blame]	190	#define CPU_FTR_DAWR LONG_ASM_CONST(0x0400000000000000)
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	191	#define CPU_FTR_DABRX LONG_ASM_CONST(0x0800000000000000)
Michael Ellerman	68f2f0d	2014-03-14 16:00:28 +1100	[diff] [blame]	192	#define CPU_FTR_PMAO_BUG LONG_ASM_CONST(0x1000000000000000)
Paul Mackerras	3965f8c	2006-06-28 13:50:39 +1000	[diff] [blame]	193
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	194	#ifndef __ASSEMBLY__
				195
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	196	#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_NOEXECUTE \| CPU_FTR_NODSISRALIGN)
				197
Michael Ellerman	13b3d13	2014-07-10 12:29:20 +1000	[diff] [blame^]	198	#define MMU_FTR_PPCAS_ARCH_V2 (MMU_FTR_TLBIEL \| MMU_FTR_16M_PAGE)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	199
				200	/* We only set the altivec features if the kernel was compiled with altivec
				201	* support
				202	*/
				203	#ifdef CONFIG_ALTIVEC
				204	#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
				205	#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
				206	#else
				207	#define CPU_FTR_ALTIVEC_COMP 0
				208	#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
				209	#endif
				210
Michael Neuling	b962ce9	2008-06-25 14:07:18 +1000	[diff] [blame]	211	/* We only set the VSX features if the kernel was compiled with VSX
				212	* support
				213	*/
				214	#ifdef CONFIG_VSX
				215	#define CPU_FTR_VSX_COMP CPU_FTR_VSX
				216	#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
				217	#else
				218	#define CPU_FTR_VSX_COMP 0
				219	#define PPC_FEATURE_HAS_VSX_COMP 0
				220	#endif
				221
Kumar Gala	5e14d21	2007-09-13 01:44:20 -0500	[diff] [blame]	222	/* We only set the spe features if the kernel was compiled with spe
				223	* support
				224	*/
				225	#ifdef CONFIG_SPE
				226	#define CPU_FTR_SPE_COMP CPU_FTR_SPE
				227	#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
				228	#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
				229	#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
				230	#else
				231	#define CPU_FTR_SPE_COMP 0
				232	#define PPC_FEATURE_HAS_SPE_COMP 0
				233	#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
				234	#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
				235	#endif
				236
Michael Neuling	6a6d541	2013-02-13 16:21:29 +0000	[diff] [blame]	237	/* We only set the TM feature if the kernel was compiled with TM supprt */
				238	#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
				239	#define CPU_FTR_TM_COMP CPU_FTR_TM
Nishanth Aravamudan	cbbc6f1	2013-05-03 14:47:56 +0000	[diff] [blame]	240	#define PPC_FEATURE2_HTM_COMP PPC_FEATURE2_HTM
Michael Neuling	6a6d541	2013-02-13 16:21:29 +0000	[diff] [blame]	241	#else
				242	#define CPU_FTR_TM_COMP 0
Nishanth Aravamudan	cbbc6f1	2013-05-03 14:47:56 +0000	[diff] [blame]	243	#define PPC_FEATURE2_HTM_COMP 0
Michael Neuling	6a6d541	2013-02-13 16:21:29 +0000	[diff] [blame]	244	#endif
				245
Scott Wood	11af119	2007-09-14 15:32:14 -0500	[diff] [blame]	246	/* We need to mark all pages as being coherent if we're SMP or we have a
				247	* 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
				248	* require it for PCI "streaming/prefetch" to work properly.
Piotr Ziecik	c931092	2009-03-17 09:17:50 -0600	[diff] [blame]	249	* This is also required by 52xx family.
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	250	*/
Kumar Gala	1775dbb	2006-02-22 09:46:02 -0600	[diff] [blame]	251	#if defined(CONFIG_SMP) \|\| defined(CONFIG_MPC10X_BRIDGE) \
Piotr Ziecik	c931092	2009-03-17 09:17:50 -0600	[diff] [blame]	252	\|\| defined(CONFIG_PPC_83xx) \|\| defined(CONFIG_8260) \
				253	\|\| defined(CONFIG_PPC_MPC52xx)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	254	#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
				255	#else
				256	#define CPU_FTR_COMMON 0
				257	#endif
				258
				259	/* The powersave features NAP & DOZE seems to confuse BDI when
				260	debugging. So if a BDI is used, disable theses
				261	*/
				262	#ifndef CONFIG_BDI_SWITCH
				263	#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
				264	#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
				265	#else
				266	#define CPU_FTR_MAYBE_CAN_DOZE 0
				267	#define CPU_FTR_MAYBE_CAN_NAP 0
				268	#endif
				269
				270	#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
				271	!defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
				272	!defined(CONFIG_BOOKE))
				273
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	274	#define CPU_FTRS_PPC601 (CPU_FTR_COMMON \| CPU_FTR_601 \| \
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	275	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_UNIFIED_ID_CACHE)
				276	#define CPU_FTRS_603 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	277	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	278	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	279	#define CPU_FTRS_604 (CPU_FTR_COMMON \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	280	CPU_FTR_USE_TB \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	281	#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	282	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	283	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	284	#define CPU_FTRS_740 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	285	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	286	CPU_FTR_TAU \| CPU_FTR_MAYBE_CAN_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	287	CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	288	#define CPU_FTRS_750 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	289	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	290	CPU_FTR_TAU \| CPU_FTR_MAYBE_CAN_NAP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	291	CPU_FTR_PPC_LE)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	292	#define CPU_FTRS_750CL (CPU_FTRS_750)
Josh Boyer	b6f41cc	2007-07-03 02:06:53 +1000	[diff] [blame]	293	#define CPU_FTRS_750FX1 (CPU_FTRS_750 \| CPU_FTR_DUAL_PLL_750FX \| CPU_FTR_NO_DPM)
				294	#define CPU_FTRS_750FX2 (CPU_FTRS_750 \| CPU_FTR_NO_DPM)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	295	#define CPU_FTRS_750FX (CPU_FTRS_750 \| CPU_FTR_DUAL_PLL_750FX)
Josh Boyer	b6f41cc	2007-07-03 02:06:53 +1000	[diff] [blame]	296	#define CPU_FTRS_750GX (CPU_FTRS_750FX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	297	#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	298	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	299	CPU_FTR_ALTIVEC_COMP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	300	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	301	#define CPU_FTRS_7400 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	302	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| CPU_FTR_L2CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	303	CPU_FTR_TAU \| CPU_FTR_ALTIVEC_COMP \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	304	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	305	#define CPU_FTRS_7450_20 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	306	CPU_FTR_USE_TB \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	307	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	308	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	309	#define CPU_FTRS_7450_21 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	310	CPU_FTR_USE_TB \| \
				311	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	312	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	313	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	314	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	315	#define CPU_FTRS_7450_23 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	316	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	317	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	318	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Paul Mackerras	fab5db9	2006-06-07 16:14:40 +1000	[diff] [blame]	319	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	320	#define CPU_FTRS_7455_1 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	321	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	322	CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| CPU_FTR_L3CR \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	323	CPU_FTR_SPEC7450 \| CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	324	#define CPU_FTRS_7455_20 (CPU_FTR_COMMON \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	325	CPU_FTR_USE_TB \| CPU_FTR_NEED_PAIRED_STWCX \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	326	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	327	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	328	CPU_FTR_NAP_DISABLE_L2_PR \| CPU_FTR_L3_DISABLE_NAP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	329	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	330	#define CPU_FTRS_7455 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	331	CPU_FTR_USE_TB \| \
				332	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	333	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	334	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	335	#define CPU_FTRS_7447_10 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	336	CPU_FTR_USE_TB \| \
				337	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	338	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	339	CPU_FTR_NEED_COHERENT \| CPU_FTR_NO_BTIC \| CPU_FTR_PPC_LE \| \
				340	CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	341	#define CPU_FTRS_7447 (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	342	CPU_FTR_USE_TB \| \
				343	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	344	CPU_FTR_L3CR \| CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	345	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	346	#define CPU_FTRS_7447A (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	347	CPU_FTR_USE_TB \| \
				348	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	349	CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	350	CPU_FTR_NEED_COHERENT \| CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	351	#define CPU_FTRS_7448 (CPU_FTR_COMMON \| \
James.Yang	3d37254	2007-05-02 16:34:43 -0500	[diff] [blame]	352	CPU_FTR_USE_TB \| \
				353	CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_L2CR \| CPU_FTR_ALTIVEC_COMP \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	354	CPU_FTR_SPEC7450 \| CPU_FTR_NAP_DISABLE_L2_PR \| \
Becky Bruce	b64f87c	2007-11-10 09:17:49 +1100	[diff] [blame]	355	CPU_FTR_PPC_LE \| CPU_FTR_NEED_PAIRED_STWCX)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	356	#define CPU_FTRS_82XX (CPU_FTR_COMMON \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	357	CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB)
Scott Wood	11af119	2007-09-14 15:32:14 -0500	[diff] [blame]	358	#define CPU_FTRS_G2_LE (CPU_FTR_COMMON \| CPU_FTR_MAYBE_CAN_DOZE \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	359	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	360	#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	361	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	362	CPU_FTR_COMMON)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	363	#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	364	CPU_FTR_USE_TB \| CPU_FTR_MAYBE_CAN_NAP \| \
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	365	CPU_FTR_COMMON \| CPU_FTR_FPU_UNAVAILABLE)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	366	#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON \| CPU_FTR_USE_TB)
David Gibson	4508dc2	2007-06-13 14:52:57 +1000	[diff] [blame]	367	#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
Benjamin Herrenschmidt	8309ce72	2008-12-12 17:33:25 +1100	[diff] [blame]	368	#define CPU_FTRS_40X (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
				369	#define CPU_FTRS_44X (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
Benjamin Herrenschmidt	6d2170b	2008-12-18 19:13:22 +0000	[diff] [blame]	370	#define CPU_FTRS_440x6 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE \| \
				371	CPU_FTR_INDEXED_DCR)
Dave Kleikamp	e7f75ad	2010-03-05 10:43:12 +0000	[diff] [blame]	372	#define CPU_FTRS_47X (CPU_FTRS_440x6)
Kumar Gala	5e14d21	2007-09-13 01:44:20 -0500	[diff] [blame]	373	#define CPU_FTRS_E200 (CPU_FTR_USE_TB \| CPU_FTR_SPE_COMP \| \
				374	CPU_FTR_NODSISRALIGN \| CPU_FTR_COHERENT_ICACHE \| \
Scott Wood	52b066f	2011-12-20 15:34:12 +0000	[diff] [blame]	375	CPU_FTR_UNIFIED_ID_CACHE \| CPU_FTR_NOEXECUTE \| \
				376	CPU_FTR_DEBUG_LVL_EXC)
Kumar Gala	fc4033b	2008-06-18 16:26:52 -0500	[diff] [blame]	377	#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Benjamin Herrenschmidt	8309ce72	2008-12-12 17:33:25 +1100	[diff] [blame]	378	CPU_FTR_SPE_COMP \| CPU_FTR_MAYBE_CAN_NAP \| CPU_FTR_NODSISRALIGN \| \
				379	CPU_FTR_NOEXECUTE)
Kumar Gala	fc4033b	2008-06-18 16:26:52 -0500	[diff] [blame]	380	#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE \| CPU_FTR_USE_TB \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	381	CPU_FTR_SPE_COMP \| CPU_FTR_MAYBE_CAN_NAP \| \
Benjamin Herrenschmidt	8309ce72	2008-12-12 17:33:25 +1100	[diff] [blame]	382	CPU_FTR_NODSISRALIGN \| CPU_FTR_NOEXECUTE)
Scott Wood	d51ad91	2010-05-27 17:35:12 -0500	[diff] [blame]	383	#define CPU_FTRS_E500MC (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| \
Kumar Gala	620165f	2009-02-12 13:54:53 +0000	[diff] [blame]	384	CPU_FTR_L2CSR \| CPU_FTR_LWSYNC \| CPU_FTR_NOEXECUTE \| \
Scott Wood	73196cd3	2011-12-20 15:34:47 +0000	[diff] [blame]	385	CPU_FTR_DBELL \| CPU_FTR_DEBUG_LVL_EXC \| CPU_FTR_EMB_HV)
Scott Wood	d52459c	2013-07-23 20:21:11 -0500	[diff] [blame]	386	/*
				387	* e5500/e6500 erratum A-006958 is a timebase bug that can use the
				388	* same workaround as CPU_FTR_CELL_TB_BUG.
				389	*/
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	390	#define CPU_FTRS_E5500 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| \
				391	CPU_FTR_L2CSR \| CPU_FTR_LWSYNC \| CPU_FTR_NOEXECUTE \| \
Kumar Gala	d36b4c4	2011-04-06 00:18:48 -0500	[diff] [blame]	392	CPU_FTR_DBELL \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Scott Wood	d52459c	2013-07-23 20:21:11 -0500	[diff] [blame]	393	CPU_FTR_DEBUG_LVL_EXC \| CPU_FTR_EMB_HV \| CPU_FTR_CELL_TB_BUG)
Kumar Gala	1024184	2011-11-06 11:51:07 -0600	[diff] [blame]	394	#define CPU_FTRS_E6500 (CPU_FTR_USE_TB \| CPU_FTR_NODSISRALIGN \| \
				395	CPU_FTR_L2CSR \| CPU_FTR_LWSYNC \| CPU_FTR_NOEXECUTE \| \
				396	CPU_FTR_DBELL \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Scott Wood	d52459c	2013-07-23 20:21:11 -0500	[diff] [blame]	397	CPU_FTR_DEBUG_LVL_EXC \| CPU_FTR_EMB_HV \| CPU_FTR_ALTIVEC_COMP \| \
				398	CPU_FTR_CELL_TB_BUG)
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	399	#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON \| CPU_FTR_NODSISRALIGN)
Michael Ellerman	0b8e2e1	2006-11-23 00:46:46 +0100	[diff] [blame]	400
				401	/* 64-bit CPUs */
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	402	#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	403	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Anton Blanchard	f89451f	2010-08-11 01:40:27 +0000	[diff] [blame]	404	CPU_FTR_MMCRA \| CPU_FTR_CP_USE_DCBTZ \| \
				405	CPU_FTR_STCX_CHECKS_ADDRESS)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	406	#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	407	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| CPU_FTR_ARCH_201 \| \
Mark Nelson	2a92943	2008-08-22 14:36:19 +1000	[diff] [blame]	408	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_CAN_NAP \| CPU_FTR_MMCRA \| \
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	409	CPU_FTR_CP_USE_DCBTZ \| CPU_FTR_STCX_CHECKS_ADDRESS \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	410	CPU_FTR_HVMODE \| CPU_FTR_DABRX)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	411	#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	412	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	413	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	414	CPU_FTR_COHERENT_ICACHE \| CPU_FTR_PURR \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	415	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_DABRX)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	416	#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	417	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Anton Blanchard	03054d5	2006-04-29 09:51:06 +1000	[diff] [blame]	418	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	419	CPU_FTR_COHERENT_ICACHE \| \
Anton Blanchard	4c198557	2006-12-08 17:46:58 +1100	[diff] [blame]	420	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
Anton Blanchard	f89451f	2010-08-11 01:40:27 +0000	[diff] [blame]	421	CPU_FTR_DSCR \| CPU_FTR_UNALIGNED_LD_STD \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	422	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_CFAR \| \
				423	CPU_FTR_DABRX)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	424	#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Paul Mackerras	969391c	2011-06-29 00:26:11 +0000	[diff] [blame]	425	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| CPU_FTR_ARCH_206 \|\
Michael Neuling	e952e6c	2008-06-18 10:47:26 +1000	[diff] [blame]	426	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	427	CPU_FTR_COHERENT_ICACHE \| \
Michael Neuling	e952e6c	2008-06-18 10:47:26 +1000	[diff] [blame]	428	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
Anton Blanchard	f89451f	2010-08-11 01:40:27 +0000	[diff] [blame]	429	CPU_FTR_DSCR \| CPU_FTR_SAO \| CPU_FTR_ASYM_SMT \| \
Tseng-Hui (Frank) Lin	851d2e2	2011-05-02 20:43:04 +0000	[diff] [blame]	430	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Haren Myneni	d2613868	2012-12-06 21:47:42 +0000	[diff] [blame]	431	CPU_FTR_ICSWX \| CPU_FTR_CFAR \| CPU_FTR_HVMODE \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	432	CPU_FTR_VMX_COPY \| CPU_FTR_HAS_PPR \| CPU_FTR_DABRX)
Michael Neuling	71e1849	2012-10-30 19:34:15 +0000	[diff] [blame]	433	#define CPU_FTRS_POWER8 (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
				434	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| CPU_FTR_ARCH_206 \|\
				435	CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
				436	CPU_FTR_COHERENT_ICACHE \| \
				437	CPU_FTR_PURR \| CPU_FTR_SPURR \| CPU_FTR_REAL_LE \| \
				438	CPU_FTR_DSCR \| CPU_FTR_SAO \| \
				439	CPU_FTR_STCX_CHECKS_ADDRESS \| CPU_FTR_POPCNTB \| CPU_FTR_POPCNTD \| \
Ian Munsie	e5e84f0	2012-11-14 18:49:50 +0000	[diff] [blame]	440	CPU_FTR_ICSWX \| CPU_FTR_CFAR \| CPU_FTR_HVMODE \| CPU_FTR_VMX_COPY \| \
Michael Ellerman	1de2bd4	2013-04-30 20:17:02 +0000	[diff] [blame]	441	CPU_FTR_DBELL \| CPU_FTR_HAS_PPR \| CPU_FTR_DAWR \| \
				442	CPU_FTR_ARCH_207S \| CPU_FTR_TM_COMP)
Michael Ellerman	68f2f0d	2014-03-14 16:00:28 +1100	[diff] [blame]	443	#define CPU_FTRS_POWER8E (CPU_FTRS_POWER8 \| CPU_FTR_PMAO_BUG)
Joel Stanley	bd6ba35	2014-07-18 11:41:37 +0930	[diff] [blame]	444	#define CPU_FTRS_POWER8_DD1 (CPU_FTRS_POWER8 & ~CPU_FTR_DBELL)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	445	#define CPU_FTRS_CELL (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	446	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_CTRL \| \
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	447	CPU_FTR_ALTIVEC_COMP \| CPU_FTR_MMCRA \| CPU_FTR_SMT \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	448	CPU_FTR_PAUSE_ZERO \| CPU_FTR_CELL_TB_BUG \| CPU_FTR_CP_USE_DCBTZ \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	449	CPU_FTR_UNALIGNED_LD_STD \| CPU_FTR_DABRX)
Kumar Gala	2d1b202	2008-07-02 01:16:40 +1000	[diff] [blame]	450	#define CPU_FTRS_PA6T (CPU_FTR_USE_TB \| CPU_FTR_LWSYNC \| \
Matt Evans	44ae3ab	2011-04-06 19:48:50 +0000	[diff] [blame]	451	CPU_FTR_PPCAS_ARCH_V2 \| CPU_FTR_ALTIVEC_COMP \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	452	CPU_FTR_PURR \| CPU_FTR_REAL_LE \| CPU_FTR_DABRX)
Benjamin Herrenschmidt	7c03d65	2008-12-18 19:13:32 +0000	[diff] [blame]	453	#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB \| CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	454
Benjamin Herrenschmidt	76b4eda	2011-04-14 22:32:01 +0000	[diff] [blame]	455	#define CPU_FTRS_A2 (CPU_FTR_USE_TB \| CPU_FTR_SMT \| CPU_FTR_DBELL \| \
Michael Neuling	82a9f16	2013-05-16 20:27:31 +0000	[diff] [blame]	456	CPU_FTR_NOEXECUTE \| CPU_FTR_NODSISRALIGN \| \
				457	CPU_FTR_ICSWX \| CPU_FTR_DABRX )
Benjamin Herrenschmidt	76b4eda	2011-04-14 22:32:01 +0000	[diff] [blame]	458
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	459	#ifdef __powerpc64__
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	460	#ifdef CONFIG_PPC_BOOK3E
Kumar Gala	1024184	2011-11-06 11:51:07 -0600	[diff] [blame]	461	#define CPU_FTRS_POSSIBLE (CPU_FTRS_E6500 \| CPU_FTRS_E5500 \| CPU_FTRS_A2)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	462	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	463	#define CPU_FTRS_POSSIBLE \
Michael Ellerman	468a330	2014-07-10 12:29:18 +1000	[diff] [blame]	464	(CPU_FTRS_POWER4 \| CPU_FTRS_PPC970 \| CPU_FTRS_POWER5 \| \
				465	CPU_FTRS_POWER6 \| CPU_FTRS_POWER7 \| CPU_FTRS_POWER8E \| \
				466	CPU_FTRS_POWER8 \| CPU_FTRS_CELL \| CPU_FTRS_PA6T \| CPU_FTR_VSX)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	467	#endif
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	468	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	469	enum {
				470	CPU_FTRS_POSSIBLE =
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	471	#if CLASSIC_PPC
				472	CPU_FTRS_PPC601 \| CPU_FTRS_603 \| CPU_FTRS_604 \| CPU_FTRS_740_NOTAU \|
				473	CPU_FTRS_740 \| CPU_FTRS_750 \| CPU_FTRS_750FX1 \|
				474	CPU_FTRS_750FX2 \| CPU_FTRS_750FX \| CPU_FTRS_750GX \|
				475	CPU_FTRS_7400_NOTAU \| CPU_FTRS_7400 \| CPU_FTRS_7450_20 \|
				476	CPU_FTRS_7450_21 \| CPU_FTRS_7450_23 \| CPU_FTRS_7455_1 \|
				477	CPU_FTRS_7455_20 \| CPU_FTRS_7455 \| CPU_FTRS_7447_10 \|
				478	CPU_FTRS_7447 \| CPU_FTRS_7447A \| CPU_FTRS_82XX \|
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	479	CPU_FTRS_G2_LE \| CPU_FTRS_E300 \| CPU_FTRS_E300C2 \|
				480	CPU_FTRS_CLASSIC32 \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	481	#else
				482	CPU_FTRS_GENERIC_32 \|
				483	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	484	#ifdef CONFIG_8xx
				485	CPU_FTRS_8XX \|
				486	#endif
				487	#ifdef CONFIG_40x
				488	CPU_FTRS_40X \|
				489	#endif
				490	#ifdef CONFIG_44x
Benjamin Herrenschmidt	6d2170b	2008-12-18 19:13:22 +0000	[diff] [blame]	491	CPU_FTRS_44X \| CPU_FTRS_440x6 \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	492	#endif
Dave Kleikamp	e7f75ad	2010-03-05 10:43:12 +0000	[diff] [blame]	493	#ifdef CONFIG_PPC_47x
Dave Kleikamp	c48d0db	2011-01-26 06:17:58 +0000	[diff] [blame]	494	CPU_FTRS_47X \| CPU_FTR_476_DD2 \|
Dave Kleikamp	e7f75ad	2010-03-05 10:43:12 +0000	[diff] [blame]	495	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	496	#ifdef CONFIG_E200
				497	CPU_FTRS_E200 \|
				498	#endif
				499	#ifdef CONFIG_E500
Scott Wood	06aae86	2011-12-20 15:34:14 +0000	[diff] [blame]	500	CPU_FTRS_E500 \| CPU_FTRS_E500_2 \|
				501	#endif
				502	#ifdef CONFIG_PPC_E500MC
				503	CPU_FTRS_E500MC \| CPU_FTRS_E5500 \| CPU_FTRS_E6500 \|
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	504	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	505	0,
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	506	};
				507	#endif /* __powerpc64__ */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	508
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	509	#ifdef __powerpc64__
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	510	#ifdef CONFIG_PPC_BOOK3E
Kumar Gala	1024184	2011-11-06 11:51:07 -0600	[diff] [blame]	511	#define CPU_FTRS_ALWAYS (CPU_FTRS_E6500 & CPU_FTRS_E5500 & CPU_FTRS_A2)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	512	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	513	#define CPU_FTRS_ALWAYS \
Michael Ellerman	468a330	2014-07-10 12:29:18 +1000	[diff] [blame]	514	(CPU_FTRS_POWER4 & CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & \
				515	CPU_FTRS_POWER6 & CPU_FTRS_POWER7 & CPU_FTRS_CELL & \
				516	CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Kumar Gala	11ed0db	2011-04-06 00:11:06 -0500	[diff] [blame]	517	#endif
Anton Blanchard	2406f60	2005-12-13 07:45:33 +1100	[diff] [blame]	518	#else
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	519	enum {
				520	CPU_FTRS_ALWAYS =
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	521	#if CLASSIC_PPC
				522	CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
				523	CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
				524	CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
				525	CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
				526	CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
				527	CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
				528	CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
Kim Phillips	aa42c69	2006-12-08 02:43:30 -0600	[diff] [blame]	529	CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
				530	CPU_FTRS_CLASSIC32 &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	531	#else
				532	CPU_FTRS_GENERIC_32 &
				533	#endif
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	534	#ifdef CONFIG_8xx
				535	CPU_FTRS_8XX &
				536	#endif
				537	#ifdef CONFIG_40x
				538	CPU_FTRS_40X &
				539	#endif
				540	#ifdef CONFIG_44x
Benjamin Herrenschmidt	6d2170b	2008-12-18 19:13:22 +0000	[diff] [blame]	541	CPU_FTRS_44X & CPU_FTRS_440x6 &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	542	#endif
				543	#ifdef CONFIG_E200
				544	CPU_FTRS_E200 &
				545	#endif
				546	#ifdef CONFIG_E500
Scott Wood	06aae86	2011-12-20 15:34:14 +0000	[diff] [blame]	547	CPU_FTRS_E500 & CPU_FTRS_E500_2 &
				548	#endif
				549	#ifdef CONFIG_PPC_E500MC
				550	CPU_FTRS_E500MC & CPU_FTRS_E5500 & CPU_FTRS_E6500 &
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	551	#endif
Scott Wood	73196cd3	2011-12-20 15:34:47 +0000	[diff] [blame]	552	~CPU_FTR_EMB_HV & /* can be removed at runtime */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	553	CPU_FTRS_POSSIBLE,
				554	};
Stephen Rothwell	7c92943	2006-03-23 17:36:59 +1100	[diff] [blame]	555	#endif /* __powerpc64__ */
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	556
				557	static inline int cpu_has_feature(unsigned long feature)
				558	{
				559	return (CPU_FTRS_ALWAYS & feature) \|\|
				560	(CPU_FTRS_POSSIBLE
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	561	& cur_cpu_spec->cpu_features
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	562	& feature);
				563	}
				564
K.Prasad	5aae8a5	2010-06-15 11:35:19 +0530	[diff] [blame]	565	#define HBP_NUM 1
K.Prasad	5aae8a5	2010-06-15 11:35:19 +0530	[diff] [blame]	566
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	567	#endif /* !__ASSEMBLY__ */
				568
Kumar Gala	10b35d9	2005-09-23 14:08:58 -0500	[diff] [blame]	569	#endif /* __ASM_POWERPC_CPUTABLE_H */