| Sasha Neftin | 13b5b7f | 2018-10-11 10:17:19 +0300 | [diff] [blame^] | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
| 2 | /* Copyright (c) 2018 Intel Corporation */ |
| 3 | |
| 4 | #ifndef _IGC_BASE_H |
| 5 | #define _IGC_BASE_H |
| 6 | |
| 7 | /* forward declaration */ |
| 8 | void igc_rx_fifo_flush_base(struct igc_hw *hw); |
| 9 | |
| 10 | /* Transmit Descriptor - Advanced */ |
| 11 | union igc_adv_tx_desc { |
| 12 | struct { |
| 13 | __le64 buffer_addr; /* Address of descriptor's data buf */ |
| 14 | __le32 cmd_type_len; |
| 15 | __le32 olinfo_status; |
| 16 | } read; |
| 17 | struct { |
| 18 | __le64 rsvd; /* Reserved */ |
| 19 | __le32 nxtseq_seed; |
| 20 | __le32 status; |
| 21 | } wb; |
| 22 | }; |
| 23 | |
| 24 | struct igc_adv_data_desc { |
| 25 | __le64 buffer_addr; /* Address of the descriptor's data buffer */ |
| 26 | union { |
| 27 | u32 data; |
| 28 | struct { |
| 29 | u32 datalen:16; /* Data buffer length */ |
| 30 | u32 rsvd:4; |
| 31 | u32 dtyp:4; /* Descriptor type */ |
| 32 | u32 dcmd:8; /* Descriptor command */ |
| 33 | } config; |
| 34 | } lower; |
| 35 | union { |
| 36 | u32 data; |
| 37 | struct { |
| 38 | u32 status:4; /* Descriptor status */ |
| 39 | u32 idx:4; |
| 40 | u32 popts:6; /* Packet Options */ |
| 41 | u32 paylen:18; /* Payload length */ |
| 42 | } options; |
| 43 | } upper; |
| 44 | }; |
| 45 | |
| 46 | /* Receive Descriptor - Advanced */ |
| 47 | union igc_adv_rx_desc { |
| 48 | struct { |
| 49 | __le64 pkt_addr; /* Packet buffer address */ |
| 50 | __le64 hdr_addr; /* Header buffer address */ |
| 51 | } read; |
| 52 | struct { |
| 53 | struct { |
| 54 | union { |
| 55 | __le32 data; |
| 56 | struct { |
| 57 | __le16 pkt_info; /*RSS type, Pkt type*/ |
| 58 | /* Split Header, header buffer len */ |
| 59 | __le16 hdr_info; |
| 60 | } hs_rss; |
| 61 | } lo_dword; |
| 62 | union { |
| 63 | __le32 rss; /* RSS Hash */ |
| 64 | struct { |
| 65 | __le16 ip_id; /* IP id */ |
| 66 | __le16 csum; /* Packet Checksum */ |
| 67 | } csum_ip; |
| 68 | } hi_dword; |
| 69 | } lower; |
| 70 | struct { |
| 71 | __le32 status_error; /* ext status/error */ |
| 72 | __le16 length; /* Packet length */ |
| 73 | __le16 vlan; /* VLAN tag */ |
| 74 | } upper; |
| 75 | } wb; /* writeback */ |
| 76 | }; |
| 77 | |
| 78 | /* Additional Transmit Descriptor Control definitions */ |
| 79 | #define IGC_TXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Tx Queue */ |
| 80 | |
| 81 | /* Additional Receive Descriptor Control definitions */ |
| 82 | #define IGC_RXDCTL_QUEUE_ENABLE 0x02000000 /* Ena specific Rx Queue */ |
| 83 | |
| 84 | /* SRRCTL bit definitions */ |
| 85 | #define IGC_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ |
| 86 | #define IGC_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ |
| 87 | #define IGC_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 |
| 88 | |
| 89 | #endif /* _IGC_BASE_H */ |