| Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 1 | /* |
| 2 | * linux/arch/arm/mach-mmp/include/mach/regs-apbc.h |
| 3 | * |
| 4 | * Application Peripheral Bus Clock Unit |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #ifndef __ASM_MACH_REGS_APBC_H |
| 12 | #define __ASM_MACH_REGS_APBC_H |
| 13 | |
| 14 | #include <mach/addr-map.h> |
| 15 | |
| 16 | #define APBC_VIRT_BASE (APB_VIRT_BASE + 0x015000) |
| 17 | #define APBC_REG(x) (APBC_VIRT_BASE + (x)) |
| 18 | |
| 19 | /* |
| 20 | * APB clock register offsets for PXA168 |
| 21 | */ |
| 22 | #define APBC_PXA168_UART1 APBC_REG(0x000) |
| 23 | #define APBC_PXA168_UART2 APBC_REG(0x004) |
| 24 | #define APBC_PXA168_GPIO APBC_REG(0x008) |
| 25 | #define APBC_PXA168_PWM0 APBC_REG(0x00c) |
| 26 | #define APBC_PXA168_PWM1 APBC_REG(0x010) |
| 27 | #define APBC_PXA168_SSP1 APBC_REG(0x01c) |
| 28 | #define APBC_PXA168_SSP2 APBC_REG(0x020) |
| 29 | #define APBC_PXA168_RTC APBC_REG(0x028) |
| 30 | #define APBC_PXA168_TWSI0 APBC_REG(0x02c) |
| 31 | #define APBC_PXA168_KPC APBC_REG(0x030) |
| 32 | #define APBC_PXA168_TIMERS APBC_REG(0x034) |
| 33 | #define APBC_PXA168_AIB APBC_REG(0x03c) |
| 34 | #define APBC_PXA168_SW_JTAG APBC_REG(0x040) |
| 35 | #define APBC_PXA168_ONEWIRE APBC_REG(0x048) |
| 36 | #define APBC_PXA168_SSP3 APBC_REG(0x04c) |
| 37 | #define APBC_PXA168_ASFAR APBC_REG(0x050) |
| 38 | #define APBC_PXA168_ASSAR APBC_REG(0x054) |
| 39 | #define APBC_PXA168_SSP4 APBC_REG(0x058) |
| 40 | #define APBC_PXA168_SSP5 APBC_REG(0x05c) |
| 41 | #define APBC_PXA168_TWSI1 APBC_REG(0x06c) |
| 42 | #define APBC_PXA168_UART3 APBC_REG(0x070) |
| 43 | #define APBC_PXA168_AC97 APBC_REG(0x084) |
| 44 | |
| Eric Miao | 14c6b5e | 2009-03-20 12:50:22 +0800 | [diff] [blame^] | 45 | /* |
| 46 | * APB Clock register offsets for PXA910 |
| 47 | */ |
| 48 | #define APBC_PXA910_UART0 APBC_REG(0x000) |
| 49 | #define APBC_PXA910_UART1 APBC_REG(0x004) |
| 50 | #define APBC_PXA910_GPIO APBC_REG(0x008) |
| 51 | #define APBC_PXA910_PWM0 APBC_REG(0x00c) |
| 52 | #define APBC_PXA910_PWM1 APBC_REG(0x010) |
| 53 | #define APBC_PXA910_PWM2 APBC_REG(0x014) |
| 54 | #define APBC_PXA910_PWM3 APBC_REG(0x018) |
| 55 | #define APBC_PXA910_SSP1 APBC_REG(0x01c) |
| 56 | #define APBC_PXA910_SSP2 APBC_REG(0x020) |
| 57 | #define APBC_PXA910_IPC APBC_REG(0x024) |
| 58 | #define APBC_PXA910_TWSI0 APBC_REG(0x02c) |
| 59 | #define APBC_PXA910_KPC APBC_REG(0x030) |
| 60 | #define APBC_PXA910_TIMERS APBC_REG(0x034) |
| 61 | #define APBC_PXA910_TBROT APBC_REG(0x038) |
| 62 | #define APBC_PXA910_AIB APBC_REG(0x03c) |
| 63 | #define APBC_PXA910_SW_JTAG APBC_REG(0x040) |
| 64 | #define APBC_PXA910_TIMERS1 APBC_REG(0x044) |
| 65 | #define APBC_PXA910_ONEWIRE APBC_REG(0x048) |
| 66 | #define APBC_PXA910_SSP3 APBC_REG(0x04c) |
| 67 | #define APBC_PXA910_ASFAR APBC_REG(0x050) |
| 68 | #define APBC_PXA910_ASSAR APBC_REG(0x054) |
| 69 | |
| Eric Miao | 49cbe78 | 2009-01-20 14:15:18 +0800 | [diff] [blame] | 70 | /* Common APB clock register bit definitions */ |
| 71 | #define APBC_APBCLK (1 << 0) /* APB Bus Clock Enable */ |
| 72 | #define APBC_FNCLK (1 << 1) /* Functional Clock Enable */ |
| 73 | #define APBC_RST (1 << 2) /* Reset Generation */ |
| 74 | |
| 75 | /* Functional Clock Selection Mask */ |
| 76 | #define APBC_FNCLKSEL(x) (((x) & 0xf) << 4) |
| 77 | |
| 78 | #endif /* __ASM_MACH_REGS_APBC_H */ |