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gerrit-public.fairphone.software / kernel / msm-5.4 / 18a8de1bc37e97dff1c96ee6cf49adbd02a0f775 / . / drivers / gpu / drm / amd / amdgpu / si_dpm.c
blob: 33b504bafb8824727f3ba60fe2b103608ffe61c0 [file] [log] [blame]
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1/*
2 * Copyright 2013 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include "drmP.h"
25#include "amdgpu.h"
26#include "amdgpu_pm.h"
27#include "amdgpu_dpm.h"
28#include "amdgpu_atombios.h"
Alex Deucher689957b2017-01-24 18:00:57 -0500[diff] [blame]29#include "sid.h"
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]30#include "r600_dpm.h"
31#include "si_dpm.h"
32#include "atom.h"
33#include "../include/pptable.h"
34#include <linux/math64.h>
35#include <linux/seq_file.h>
36#include <linux/firmware.h>
37
38#define MC_CG_ARB_FREQ_F0 0x0a
39#define MC_CG_ARB_FREQ_F1 0x0b
40#define MC_CG_ARB_FREQ_F2 0x0c
41#define MC_CG_ARB_FREQ_F3 0x0d
42
43#define SMC_RAM_END 0x20000
44
45#define SCLK_MIN_DEEPSLEEP_FREQ 1350
46
47
48/* sizeof(ATOM_PPLIB_EXTENDEDHEADER) */
49#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V2 12
50#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V3 14
51#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V4 16
52#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V5 18
53#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V6 20
54#define SIZE_OF_ATOM_PPLIB_EXTENDEDHEADER_V7 22
55
56#define BIOS_SCRATCH_4 0x5cd
57
58MODULE_FIRMWARE("radeon/tahiti_smc.bin");
59MODULE_FIRMWARE("radeon/pitcairn_smc.bin");
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]60MODULE_FIRMWARE("radeon/pitcairn_k_smc.bin");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]61MODULE_FIRMWARE("radeon/verde_smc.bin");
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]62MODULE_FIRMWARE("radeon/verde_k_smc.bin");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]63MODULE_FIRMWARE("radeon/oland_smc.bin");
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]64MODULE_FIRMWARE("radeon/oland_k_smc.bin");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]65MODULE_FIRMWARE("radeon/hainan_smc.bin");
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]66MODULE_FIRMWARE("radeon/hainan_k_smc.bin");
Alex Deucher17324b62017-01-17 15:06:58 -0500[diff] [blame]67MODULE_FIRMWARE("radeon/banks_k_2_smc.bin");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]68
69union power_info {
70 struct _ATOM_POWERPLAY_INFO info;
71 struct _ATOM_POWERPLAY_INFO_V2 info_2;
72 struct _ATOM_POWERPLAY_INFO_V3 info_3;
73 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
74 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
75 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
76 struct _ATOM_PPLIB_POWERPLAYTABLE4 pplib4;
77 struct _ATOM_PPLIB_POWERPLAYTABLE5 pplib5;
78};
79
80union fan_info {
81 struct _ATOM_PPLIB_FANTABLE fan;
82 struct _ATOM_PPLIB_FANTABLE2 fan2;
83 struct _ATOM_PPLIB_FANTABLE3 fan3;
84};
85
86union pplib_clock_info {
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]87 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
88 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
89 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
90 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
91 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]92};
93
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]94static const u32 r600_utc[R600_PM_NUMBER_OF_TC] =
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]95{
96 R600_UTC_DFLT_00,
97 R600_UTC_DFLT_01,
98 R600_UTC_DFLT_02,
99 R600_UTC_DFLT_03,
100 R600_UTC_DFLT_04,
101 R600_UTC_DFLT_05,
102 R600_UTC_DFLT_06,
103 R600_UTC_DFLT_07,
104 R600_UTC_DFLT_08,
105 R600_UTC_DFLT_09,
106 R600_UTC_DFLT_10,
107 R600_UTC_DFLT_11,
108 R600_UTC_DFLT_12,
109 R600_UTC_DFLT_13,
110 R600_UTC_DFLT_14,
111};
112
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]113static const u32 r600_dtc[R600_PM_NUMBER_OF_TC] =
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]114{
115 R600_DTC_DFLT_00,
116 R600_DTC_DFLT_01,
117 R600_DTC_DFLT_02,
118 R600_DTC_DFLT_03,
119 R600_DTC_DFLT_04,
120 R600_DTC_DFLT_05,
121 R600_DTC_DFLT_06,
122 R600_DTC_DFLT_07,
123 R600_DTC_DFLT_08,
124 R600_DTC_DFLT_09,
125 R600_DTC_DFLT_10,
126 R600_DTC_DFLT_11,
127 R600_DTC_DFLT_12,
128 R600_DTC_DFLT_13,
129 R600_DTC_DFLT_14,
130};
131
132static const struct si_cac_config_reg cac_weights_tahiti[] =
133{
134 { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
135 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
136 { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
137 { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
138 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
139 { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
140 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
141 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
142 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
143 { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
144 { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
145 { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
146 { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
147 { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
148 { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
149 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
150 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
151 { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
152 { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
153 { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
154 { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
155 { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
156 { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
157 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
158 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
159 { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
160 { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
161 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
162 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
163 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
164 { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
165 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
166 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
167 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
168 { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
169 { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
170 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
171 { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
172 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
173 { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
174 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
175 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
176 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
177 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
178 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
179 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
180 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
181 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
182 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
183 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
184 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
185 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
186 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
187 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
188 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
189 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
190 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
191 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
192 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
193 { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
194 { 0xFFFFFFFF }
195};
196
197static const struct si_cac_config_reg lcac_tahiti[] =
198{
199 { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
200 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
201 { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
202 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
203 { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
204 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
205 { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
206 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
207 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
208 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
209 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
210 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
211 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
212 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
213 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
214 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
215 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
216 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
217 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
218 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
219 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
220 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
221 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
222 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
223 { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
224 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
225 { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
226 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
227 { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
228 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
229 { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
230 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
231 { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
232 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
233 { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
234 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
235 { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
236 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
237 { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
238 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
239 { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
240 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
241 { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
242 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
243 { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
244 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
245 { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
246 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
247 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
248 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
249 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
250 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
251 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
252 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
253 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
254 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
255 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
256 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
257 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
258 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
259 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
260 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
261 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
262 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
263 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
264 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
265 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
266 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
267 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
268 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
269 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
270 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
271 { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
272 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
273 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
274 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
275 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
276 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
277 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
278 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
279 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
280 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
281 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
282 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
283 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
284 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
285 { 0xFFFFFFFF }
286
287};
288
289static const struct si_cac_config_reg cac_override_tahiti[] =
290{
291 { 0xFFFFFFFF }
292};
293
294static const struct si_powertune_data powertune_data_tahiti =
295{
296 ((1 << 16) | 27027),
297 6,
298 0,
299 4,
300 95,
301 {
302 0UL,
303 0UL,
304 4521550UL,
305 309631529UL,
306 -1270850L,
307 4513710L,
308 40
309 },
310 595000000UL,
311 12,
312 {
313 0,
314 0,
315 0,
316 0,
317 0,
318 0,
319 0,
320 0
321 },
322 true
323};
324
325static const struct si_dte_data dte_data_tahiti =
326{
327 { 1159409, 0, 0, 0, 0 },
328 { 777, 0, 0, 0, 0 },
329 2,
330 54000,
331 127000,
332 25,
333 2,
334 10,
335 13,
336 { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
337 { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
338 { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
339 85,
340 false
341};
342
Tom St Denise5c53042016-09-06 12:07:21 -0400[diff] [blame]343#if 0
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]344static const struct si_dte_data dte_data_tahiti_le =
345{
346 { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
347 { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
348 0x5,
349 0xAFC8,
350 0x64,
351 0x32,
352 1,
353 0,
354 0x10,
355 { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
356 { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
357 { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
358 85,
359 true
360};
Tom St Denise5c53042016-09-06 12:07:21 -0400[diff] [blame]361#endif
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]362
363static const struct si_dte_data dte_data_tahiti_pro =
364{
365 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
366 { 0x0, 0x0, 0x0, 0x0, 0x0 },
367 5,
368 45000,
369 100,
370 0xA,
371 1,
372 0,
373 0x10,
374 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
375 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
376 { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
377 90,
378 true
379};
380
381static const struct si_dte_data dte_data_new_zealand =
382{
383 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
384 { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
385 0x5,
386 0xAFC8,
387 0x69,
388 0x32,
389 1,
390 0,
391 0x10,
392 { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
393 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
394 { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
395 85,
396 true
397};
398
399static const struct si_dte_data dte_data_aruba_pro =
400{
401 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
402 { 0x0, 0x0, 0x0, 0x0, 0x0 },
403 5,
404 45000,
405 100,
406 0xA,
407 1,
408 0,
409 0x10,
410 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
411 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
412 { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
413 90,
414 true
415};
416
417static const struct si_dte_data dte_data_malta =
418{
419 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
420 { 0x0, 0x0, 0x0, 0x0, 0x0 },
421 5,
422 45000,
423 100,
424 0xA,
425 1,
426 0,
427 0x10,
428 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
429 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
430 { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
431 90,
432 true
433};
434
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]435static const struct si_cac_config_reg cac_weights_pitcairn[] =
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]436{
437 { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
438 { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
439 { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
440 { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
441 { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
442 { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
443 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
444 { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
445 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
446 { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
447 { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
448 { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
449 { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
450 { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
451 { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
452 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
453 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
454 { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
455 { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
456 { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
457 { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
458 { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
459 { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
460 { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
461 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
462 { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
463 { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
464 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
465 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
466 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
467 { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
468 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
469 { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
470 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
471 { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
472 { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
473 { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
474 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
475 { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
476 { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
477 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
478 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
479 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
480 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
481 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
482 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
483 { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
484 { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
485 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
486 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
487 { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
488 { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
489 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
490 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
491 { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
492 { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
493 { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
494 { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
495 { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
496 { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
497 { 0xFFFFFFFF }
498};
499
500static const struct si_cac_config_reg lcac_pitcairn[] =
501{
502 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
503 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
504 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
505 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
506 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
507 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
508 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
509 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
510 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
511 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
512 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
513 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
514 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
515 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
516 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
517 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
518 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
519 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
520 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
521 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
522 { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
523 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
524 { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
525 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
526 { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
527 { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
528 { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
529 { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
530 { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
531 { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
532 { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
533 { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
534 { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
535 { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
536 { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
537 { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
538 { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
539 { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
540 { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
541 { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
542 { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
543 { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
544 { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
545 { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
546 { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
547 { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
548 { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
549 { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
550 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
551 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
552 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
553 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
554 { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
555 { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
556 { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
557 { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
558 { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
559 { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
560 { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
561 { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
562 { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
563 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
564 { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
565 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
566 { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
567 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
568 { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
569 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
570 { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
571 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
572 { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
573 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
574 { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
575 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
576 { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
577 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
578 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
579 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
580 { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
581 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
582 { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
583 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
584 { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
585 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
586 { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
587 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
588 { 0xFFFFFFFF }
589};
590
591static const struct si_cac_config_reg cac_override_pitcairn[] =
592{
593 { 0xFFFFFFFF }
594};
595
596static const struct si_powertune_data powertune_data_pitcairn =
597{
598 ((1 << 16) | 27027),
599 5,
600 0,
601 6,
602 100,
603 {
604 51600000UL,
605 1800000UL,
606 7194395UL,
607 309631529UL,
608 -1270850L,
609 4513710L,
610 100
611 },
612 117830498UL,
613 12,
614 {
615 0,
616 0,
617 0,
618 0,
619 0,
620 0,
621 0,
622 0
623 },
624 true
625};
626
627static const struct si_dte_data dte_data_pitcairn =
628{
629 { 0, 0, 0, 0, 0 },
630 { 0, 0, 0, 0, 0 },
631 0,
632 0,
633 0,
634 0,
635 0,
636 0,
637 0,
638 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
639 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
640 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
641 0,
642 false
643};
644
645static const struct si_dte_data dte_data_curacao_xt =
646{
647 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
648 { 0x0, 0x0, 0x0, 0x0, 0x0 },
649 5,
650 45000,
651 100,
652 0xA,
653 1,
654 0,
655 0x10,
656 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
657 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
658 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
659 90,
660 true
661};
662
663static const struct si_dte_data dte_data_curacao_pro =
664{
665 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
666 { 0x0, 0x0, 0x0, 0x0, 0x0 },
667 5,
668 45000,
669 100,
670 0xA,
671 1,
672 0,
673 0x10,
674 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
675 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
676 { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
677 90,
678 true
679};
680
681static const struct si_dte_data dte_data_neptune_xt =
682{
683 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
684 { 0x0, 0x0, 0x0, 0x0, 0x0 },
685 5,
686 45000,
687 100,
688 0xA,
689 1,
690 0,
691 0x10,
692 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
693 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
694 { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
695 90,
696 true
697};
698
699static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
700{
701 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
702 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
703 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
704 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
705 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
706 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
707 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
708 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
709 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
710 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
711 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
712 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
713 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
714 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
715 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
716 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
717 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
718 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
719 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
720 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
721 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
722 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
723 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
724 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
725 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
726 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
727 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
728 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
729 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
730 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
731 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
732 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
733 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
734 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
735 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
736 { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
737 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
738 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
739 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
740 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
741 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
742 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
743 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
744 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
745 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
746 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
747 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
748 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
749 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
750 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
751 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
752 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
753 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
754 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
755 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
756 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
757 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
758 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
759 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
760 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
761 { 0xFFFFFFFF }
762};
763
764static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
765{
766 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
767 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
768 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
769 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
770 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
771 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
772 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
773 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
774 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
775 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
776 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
777 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
778 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
779 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
780 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
781 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
782 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
783 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
784 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
785 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
786 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
787 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
788 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
789 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
790 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
791 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
792 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
793 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
794 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
795 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
796 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
797 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
798 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
799 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
800 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
801 { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
802 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
803 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
804 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
805 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
806 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
807 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
808 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
809 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
810 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
811 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
812 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
813 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
814 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
815 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
816 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
817 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
818 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
819 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
820 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
821 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
822 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
823 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
824 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
825 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
826 { 0xFFFFFFFF }
827};
828
829static const struct si_cac_config_reg cac_weights_heathrow[] =
830{
831 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
832 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
833 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
834 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
835 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
836 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
837 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
838 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
839 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
840 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
841 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
842 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
843 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
844 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
845 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
846 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
847 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
848 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
849 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
850 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
851 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
852 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
853 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
854 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
855 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
856 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
857 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
858 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
859 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
860 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
861 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
862 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
863 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
864 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
865 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
866 { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
867 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
868 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
869 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
870 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
871 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
872 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
873 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
874 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
875 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
876 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
877 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
878 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
879 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
880 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
881 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
882 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
883 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
884 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
885 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
886 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
887 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
888 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
889 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
890 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
891 { 0xFFFFFFFF }
892};
893
894static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
895{
896 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
897 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
898 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
899 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
900 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
901 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
902 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
903 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
904 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
905 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
906 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
907 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
908 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
909 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
910 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
911 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
912 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
913 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
914 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
915 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
916 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
917 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
918 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
919 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
920 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
921 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
922 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
923 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
924 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
925 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
926 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
927 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
928 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
929 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
930 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
931 { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
932 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
933 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
934 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
935 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
936 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
937 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
938 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
939 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
940 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
941 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
942 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
943 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
944 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
945 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
946 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
947 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
948 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
949 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
950 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
951 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
952 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
953 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
954 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
955 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
956 { 0xFFFFFFFF }
957};
958
959static const struct si_cac_config_reg cac_weights_cape_verde[] =
960{
961 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
962 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
963 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
964 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
965 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
966 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
967 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
968 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
969 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
970 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
971 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
972 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
973 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
974 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
975 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
976 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
977 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
978 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
979 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
980 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
981 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
982 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
983 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
984 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
985 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
986 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
987 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
988 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
989 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
990 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
991 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
992 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
993 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
994 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
995 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
996 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
997 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
998 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
999 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1000 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1001 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1002 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1003 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1004 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1005 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1006 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1007 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1008 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1009 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1010 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1011 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1012 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1013 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1014 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1015 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1016 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1017 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1018 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1019 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1020 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1021 { 0xFFFFFFFF }
1022};
1023
1024static const struct si_cac_config_reg lcac_cape_verde[] =
1025{
1026 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1027 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1028 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1029 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1030 { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1031 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1032 { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1033 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1034 { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1035 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1036 { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1037 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1038 { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1039 { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1040 { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1041 { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1042 { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1043 { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1044 { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
1045 { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1046 { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1047 { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1048 { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1049 { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1050 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1051 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1052 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1053 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1054 { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1055 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1056 { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1057 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1058 { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1059 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1060 { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1061 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1062 { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1063 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1064 { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1065 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1066 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1067 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1068 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1069 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1070 { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1071 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1072 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1073 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1074 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1075 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1076 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1077 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1078 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1079 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1080 { 0xFFFFFFFF }
1081};
1082
1083static const struct si_cac_config_reg cac_override_cape_verde[] =
1084{
1085 { 0xFFFFFFFF }
1086};
1087
1088static const struct si_powertune_data powertune_data_cape_verde =
1089{
1090 ((1 << 16) | 0x6993),
1091 5,
1092 0,
1093 7,
1094 105,
1095 {
1096 0UL,
1097 0UL,
1098 7194395UL,
1099 309631529UL,
1100 -1270850L,
1101 4513710L,
1102 100
1103 },
1104 117830498UL,
1105 12,
1106 {
1107 0,
1108 0,
1109 0,
1110 0,
1111 0,
1112 0,
1113 0,
1114 0
1115 },
1116 true
1117};
1118
1119static const struct si_dte_data dte_data_cape_verde =
1120{
1121 { 0, 0, 0, 0, 0 },
1122 { 0, 0, 0, 0, 0 },
1123 0,
1124 0,
1125 0,
1126 0,
1127 0,
1128 0,
1129 0,
1130 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1131 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1132 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1133 0,
1134 false
1135};
1136
1137static const struct si_dte_data dte_data_venus_xtx =
1138{
1139 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1140 { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1141 5,
1142 55000,
1143 0x69,
1144 0xA,
1145 1,
1146 0,
1147 0x3,
1148 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1149 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1150 { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1151 90,
1152 true
1153};
1154
1155static const struct si_dte_data dte_data_venus_xt =
1156{
1157 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1158 { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1159 5,
1160 55000,
1161 0x69,
1162 0xA,
1163 1,
1164 0,
1165 0x3,
1166 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1167 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1168 { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1169 90,
1170 true
1171};
1172
1173static const struct si_dte_data dte_data_venus_pro =
1174{
1175 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1176 { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1177 5,
1178 55000,
1179 0x69,
1180 0xA,
1181 1,
1182 0,
1183 0x3,
1184 { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1185 { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1186 { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1187 90,
1188 true
1189};
1190
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]1191static const struct si_cac_config_reg cac_weights_oland[] =
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1192{
1193 { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1194 { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1195 { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1196 { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1197 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1198 { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1199 { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1200 { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1201 { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1202 { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1203 { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1204 { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1205 { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1206 { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1207 { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1208 { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1209 { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1210 { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1211 { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1212 { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1213 { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1214 { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1215 { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1216 { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1217 { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1218 { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1219 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1220 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1221 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1222 { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1223 { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1224 { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1225 { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1226 { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1227 { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1228 { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1229 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1230 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1231 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1232 { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1233 { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1234 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1235 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1236 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1237 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1239 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1240 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1241 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1242 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1243 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1244 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1245 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1246 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1247 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1248 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1249 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1250 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1251 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1252 { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1253 { 0xFFFFFFFF }
1254};
1255
1256static const struct si_cac_config_reg cac_weights_mars_pro[] =
1257{
1258 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1259 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1260 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1261 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1262 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1263 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1264 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1265 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1266 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1267 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1268 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1269 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1270 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1271 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1272 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1273 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1274 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1275 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1276 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1277 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1278 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1279 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1280 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1281 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1282 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1283 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1284 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1285 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1286 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1287 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1288 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1289 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1290 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1291 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1292 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1293 { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1294 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1295 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1296 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1297 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1298 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1299 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1300 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1301 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1302 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1304 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1305 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1306 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1307 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1308 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1309 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1310 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1311 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1312 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1313 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1314 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1315 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1316 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1317 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1318 { 0xFFFFFFFF }
1319};
1320
1321static const struct si_cac_config_reg cac_weights_mars_xt[] =
1322{
1323 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1324 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1325 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1326 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1327 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1328 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1329 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1330 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1331 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1332 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1333 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1334 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1335 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1336 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1337 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1338 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1339 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1340 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1341 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1342 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1343 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1344 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1345 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1346 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1347 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1348 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1349 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1350 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1351 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1352 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1353 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1354 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1355 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1356 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1357 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1358 { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1359 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1360 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1361 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1362 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1363 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1364 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1365 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1366 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1367 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1369 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1370 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1371 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1372 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1373 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1374 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1375 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1376 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1377 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1378 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1379 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1380 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1381 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1382 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1383 { 0xFFFFFFFF }
1384};
1385
1386static const struct si_cac_config_reg cac_weights_oland_pro[] =
1387{
1388 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1389 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1390 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1391 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1392 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1393 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1394 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1395 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1396 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1397 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1398 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1399 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1400 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1401 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1402 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1403 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1404 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1405 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1406 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1407 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1408 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1409 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1410 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1411 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1412 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1413 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1414 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1415 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1416 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1417 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1418 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1419 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1420 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1421 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1422 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1423 { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1424 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1425 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1426 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1427 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1428 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1429 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1430 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1431 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1432 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1433 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1434 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1435 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1436 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1437 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1438 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1439 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1440 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1441 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1442 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1443 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1444 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1445 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1446 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1447 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1448 { 0xFFFFFFFF }
1449};
1450
1451static const struct si_cac_config_reg cac_weights_oland_xt[] =
1452{
1453 { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1454 { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1455 { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1456 { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1457 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1458 { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1459 { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1460 { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1461 { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1462 { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1463 { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1464 { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1465 { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1466 { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1467 { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1468 { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1469 { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1470 { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1471 { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1472 { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1473 { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1474 { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1475 { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1476 { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1477 { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1478 { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1479 { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1480 { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1481 { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1482 { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1483 { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1484 { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1485 { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1486 { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1487 { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1488 { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1489 { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1490 { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1491 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1492 { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1493 { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1494 { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1495 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1496 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1497 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1498 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1499 { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1500 { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1501 { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1502 { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1503 { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1504 { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1505 { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1506 { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1507 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1508 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1509 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1510 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1511 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1512 { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1513 { 0xFFFFFFFF }
1514};
1515
1516static const struct si_cac_config_reg lcac_oland[] =
1517{
1518 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1519 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1520 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1521 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1522 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1523 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1524 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1525 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1526 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1527 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1528 { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1529 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1530 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1531 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1532 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1533 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1534 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1535 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1536 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1537 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1538 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1539 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1540 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1541 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1542 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1543 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1544 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1545 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1546 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1547 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1548 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1549 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1550 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1551 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1552 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1553 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1554 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1555 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1556 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1557 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1558 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1559 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1560 { 0xFFFFFFFF }
1561};
1562
1563static const struct si_cac_config_reg lcac_mars_pro[] =
1564{
1565 { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1566 { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1567 { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1568 { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1569 { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1570 { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1571 { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1572 { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1573 { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1574 { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1575 { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1576 { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1577 { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1578 { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1579 { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1580 { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1581 { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1582 { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1583 { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1584 { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1585 { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1586 { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1587 { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1588 { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1589 { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1590 { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1591 { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1592 { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1593 { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1594 { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1595 { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1596 { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1597 { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1598 { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1599 { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1600 { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1601 { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1602 { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1603 { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1604 { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1605 { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1606 { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1607 { 0xFFFFFFFF }
1608};
1609
1610static const struct si_cac_config_reg cac_override_oland[] =
1611{
1612 { 0xFFFFFFFF }
1613};
1614
1615static const struct si_powertune_data powertune_data_oland =
1616{
1617 ((1 << 16) | 0x6993),
1618 5,
1619 0,
1620 7,
1621 105,
1622 {
1623 0UL,
1624 0UL,
1625 7194395UL,
1626 309631529UL,
1627 -1270850L,
1628 4513710L,
1629 100
1630 },
1631 117830498UL,
1632 12,
1633 {
1634 0,
1635 0,
1636 0,
1637 0,
1638 0,
1639 0,
1640 0,
1641 0
1642 },
1643 true
1644};
1645
1646static const struct si_powertune_data powertune_data_mars_pro =
1647{
1648 ((1 << 16) | 0x6993),
1649 5,
1650 0,
1651 7,
1652 105,
1653 {
1654 0UL,
1655 0UL,
1656 7194395UL,
1657 309631529UL,
1658 -1270850L,
1659 4513710L,
1660 100
1661 },
1662 117830498UL,
1663 12,
1664 {
1665 0,
1666 0,
1667 0,
1668 0,
1669 0,
1670 0,
1671 0,
1672 0
1673 },
1674 true
1675};
1676
1677static const struct si_dte_data dte_data_oland =
1678{
1679 { 0, 0, 0, 0, 0 },
1680 { 0, 0, 0, 0, 0 },
1681 0,
1682 0,
1683 0,
1684 0,
1685 0,
1686 0,
1687 0,
1688 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1689 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1690 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1691 0,
1692 false
1693};
1694
1695static const struct si_dte_data dte_data_mars_pro =
1696{
1697 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1698 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1699 5,
1700 55000,
1701 105,
1702 0xA,
1703 1,
1704 0,
1705 0x10,
1706 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1707 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1708 { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1709 90,
1710 true
1711};
1712
1713static const struct si_dte_data dte_data_sun_xt =
1714{
1715 { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1716 { 0x0, 0x0, 0x0, 0x0, 0x0 },
1717 5,
1718 55000,
1719 105,
1720 0xA,
1721 1,
1722 0,
1723 0x10,
1724 { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1725 { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1726 { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1727 90,
1728 true
1729};
1730
1731
1732static const struct si_cac_config_reg cac_weights_hainan[] =
1733{
1734 { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1735 { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1736 { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1737 { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1738 { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1739 { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1740 { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1741 { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1742 { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1743 { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1744 { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1745 { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1746 { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1747 { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1748 { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1749 { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1750 { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1751 { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1752 { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1753 { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1754 { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1755 { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1756 { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1757 { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1758 { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1759 { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1760 { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1761 { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1762 { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1763 { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1764 { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1765 { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1766 { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1767 { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1768 { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1769 { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1770 { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1771 { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1772 { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1773 { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1774 { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1775 { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1776 { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1777 { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1778 { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1779 { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1780 { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1781 { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1782 { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1783 { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1784 { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1785 { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1786 { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1787 { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1788 { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1789 { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1790 { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1791 { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1792 { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1793 { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1794 { 0xFFFFFFFF }
1795};
1796
1797static const struct si_powertune_data powertune_data_hainan =
1798{
1799 ((1 << 16) | 0x6993),
1800 5,
1801 0,
1802 9,
1803 105,
1804 {
1805 0UL,
1806 0UL,
1807 7194395UL,
1808 309631529UL,
1809 -1270850L,
1810 4513710L,
1811 100
1812 },
1813 117830498UL,
1814 12,
1815 {
1816 0,
1817 0,
1818 0,
1819 0,
1820 0,
1821 0,
1822 0,
1823 0
1824 },
1825 true
1826};
1827
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]1828static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev);
1829static struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev);
1830static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev);
1831static struct si_ps *si_get_ps(struct amdgpu_ps *rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1832
1833static int si_populate_voltage_value(struct amdgpu_device *adev,
1834 const struct atom_voltage_table *table,
1835 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1836static int si_get_std_voltage_value(struct amdgpu_device *adev,
1837 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1838 u16 *std_voltage);
1839static int si_write_smc_soft_register(struct amdgpu_device *adev,
1840 u16 reg_offset, u32 value);
1841static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
1842 struct rv7xx_pl *pl,
1843 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1844static int si_calculate_sclk_params(struct amdgpu_device *adev,
1845 u32 engine_clock,
1846 SISLANDS_SMC_SCLK_VALUE *sclk);
1847
1848static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev);
1849static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev);
1850static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev);
1851static void si_dpm_set_irq_funcs(struct amdgpu_device *adev);
1852
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1853static struct si_power_info *si_get_pi(struct amdgpu_device *adev)
1854{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1855 struct si_power_info *pi = adev->pm.dpm.priv;
1856 return pi;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1857}
1858
1859static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1860 u16 v, s32 t, u32 ileakage, u32 *leakage)
1861{
1862 s64 kt, kv, leakage_w, i_leakage, vddc;
1863 s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1864 s64 tmp;
1865
1866 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1867 vddc = div64_s64(drm_int2fixp(v), 1000);
1868 temperature = div64_s64(drm_int2fixp(t), 1000);
1869
1870 t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1871 t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1872 av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1873 bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1874 t_ref = drm_int2fixp(coeff->t_ref);
1875
1876 tmp = drm_fixp_mul(t_slope, vddc) + t_intercept;
1877 kt = drm_fixp_exp(drm_fixp_mul(tmp, temperature));
1878 kt = drm_fixp_div(kt, drm_fixp_exp(drm_fixp_mul(tmp, t_ref)));
1879 kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1880
1881 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1882
1883 *leakage = drm_fixp2int(leakage_w * 1000);
1884}
1885
1886static void si_calculate_leakage_for_v_and_t(struct amdgpu_device *adev,
1887 const struct ni_leakage_coeffients *coeff,
1888 u16 v,
1889 s32 t,
1890 u32 i_leakage,
1891 u32 *leakage)
1892{
1893 si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1894}
1895
1896static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1897 const u32 fixed_kt, u16 v,
1898 u32 ileakage, u32 *leakage)
1899{
1900 s64 kt, kv, leakage_w, i_leakage, vddc;
1901
1902 i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1903 vddc = div64_s64(drm_int2fixp(v), 1000);
1904
1905 kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1906 kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1907 drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1908
1909 leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1910
1911 *leakage = drm_fixp2int(leakage_w * 1000);
1912}
1913
1914static void si_calculate_leakage_for_v(struct amdgpu_device *adev,
1915 const struct ni_leakage_coeffients *coeff,
1916 const u32 fixed_kt,
1917 u16 v,
1918 u32 i_leakage,
1919 u32 *leakage)
1920{
1921 si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1922}
1923
1924
1925static void si_update_dte_from_pl2(struct amdgpu_device *adev,
1926 struct si_dte_data *dte_data)
1927{
1928 u32 p_limit1 = adev->pm.dpm.tdp_limit;
1929 u32 p_limit2 = adev->pm.dpm.near_tdp_limit;
1930 u32 k = dte_data->k;
1931 u32 t_max = dte_data->max_t;
1932 u32 t_split[5] = { 10, 15, 20, 25, 30 };
1933 u32 t_0 = dte_data->t0;
1934 u32 i;
1935
1936 if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1937 dte_data->tdep_count = 3;
1938
1939 for (i = 0; i < k; i++) {
1940 dte_data->r[i] =
1941 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1942 (p_limit2 * (u32)100);
1943 }
1944
1945 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1946
1947 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1948 dte_data->tdep_r[i] = dte_data->r[4];
1949 }
1950 } else {
1951 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1952 }
1953}
1954
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]1955static struct rv7xx_power_info *rv770_get_pi(struct amdgpu_device *adev)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1956{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1957 struct rv7xx_power_info *pi = adev->pm.dpm.priv;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1958
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1959 return pi;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1960}
1961
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]1962static struct ni_power_info *ni_get_pi(struct amdgpu_device *adev)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1963{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1964 struct ni_power_info *pi = adev->pm.dpm.priv;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1965
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1966 return pi;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1967}
1968
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]1969static struct si_ps *si_get_ps(struct amdgpu_ps *aps)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1970{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1971 struct si_ps *ps = aps->ps_priv;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1972
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]1973 return ps;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]1974}
1975
1976static void si_initialize_powertune_defaults(struct amdgpu_device *adev)
1977{
1978 struct ni_power_info *ni_pi = ni_get_pi(adev);
1979 struct si_power_info *si_pi = si_get_pi(adev);
1980 bool update_dte_from_pl2 = false;
1981
1982 if (adev->asic_type == CHIP_TAHITI) {
1983 si_pi->cac_weights = cac_weights_tahiti;
1984 si_pi->lcac_config = lcac_tahiti;
1985 si_pi->cac_override = cac_override_tahiti;
1986 si_pi->powertune_data = &powertune_data_tahiti;
1987 si_pi->dte_data = dte_data_tahiti;
1988
1989 switch (adev->pdev->device) {
1990 case 0x6798:
1991 si_pi->dte_data.enable_dte_by_default = true;
1992 break;
1993 case 0x6799:
1994 si_pi->dte_data = dte_data_new_zealand;
1995 break;
1996 case 0x6790:
1997 case 0x6791:
1998 case 0x6792:
1999 case 0x679E:
2000 si_pi->dte_data = dte_data_aruba_pro;
2001 update_dte_from_pl2 = true;
2002 break;
2003 case 0x679B:
2004 si_pi->dte_data = dte_data_malta;
2005 update_dte_from_pl2 = true;
2006 break;
2007 case 0x679A:
2008 si_pi->dte_data = dte_data_tahiti_pro;
2009 update_dte_from_pl2 = true;
2010 break;
2011 default:
2012 if (si_pi->dte_data.enable_dte_by_default == true)
2013 DRM_ERROR("DTE is not enabled!\n");
2014 break;
2015 }
2016 } else if (adev->asic_type == CHIP_PITCAIRN) {
Tom St Denisc3d986452016-09-06 09:44:47 -0400[diff] [blame]2017 si_pi->cac_weights = cac_weights_pitcairn;
2018 si_pi->lcac_config = lcac_pitcairn;
2019 si_pi->cac_override = cac_override_pitcairn;
2020 si_pi->powertune_data = &powertune_data_pitcairn;
2021
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2022 switch (adev->pdev->device) {
2023 case 0x6810:
2024 case 0x6818:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2025 si_pi->dte_data = dte_data_curacao_xt;
2026 update_dte_from_pl2 = true;
2027 break;
2028 case 0x6819:
2029 case 0x6811:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2030 si_pi->dte_data = dte_data_curacao_pro;
2031 update_dte_from_pl2 = true;
2032 break;
2033 case 0x6800:
2034 case 0x6806:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2035 si_pi->dte_data = dte_data_neptune_xt;
2036 update_dte_from_pl2 = true;
2037 break;
2038 default:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2039 si_pi->dte_data = dte_data_pitcairn;
2040 break;
2041 }
2042 } else if (adev->asic_type == CHIP_VERDE) {
2043 si_pi->lcac_config = lcac_cape_verde;
2044 si_pi->cac_override = cac_override_cape_verde;
2045 si_pi->powertune_data = &powertune_data_cape_verde;
2046
2047 switch (adev->pdev->device) {
2048 case 0x683B:
2049 case 0x683F:
2050 case 0x6829:
2051 case 0x6835:
2052 si_pi->cac_weights = cac_weights_cape_verde_pro;
2053 si_pi->dte_data = dte_data_cape_verde;
2054 break;
2055 case 0x682C:
2056 si_pi->cac_weights = cac_weights_cape_verde_pro;
2057 si_pi->dte_data = dte_data_sun_xt;
2058 break;
2059 case 0x6825:
2060 case 0x6827:
2061 si_pi->cac_weights = cac_weights_heathrow;
2062 si_pi->dte_data = dte_data_cape_verde;
2063 break;
2064 case 0x6824:
2065 case 0x682D:
2066 si_pi->cac_weights = cac_weights_chelsea_xt;
2067 si_pi->dte_data = dte_data_cape_verde;
2068 break;
2069 case 0x682F:
2070 si_pi->cac_weights = cac_weights_chelsea_pro;
2071 si_pi->dte_data = dte_data_cape_verde;
2072 break;
2073 case 0x6820:
2074 si_pi->cac_weights = cac_weights_heathrow;
2075 si_pi->dte_data = dte_data_venus_xtx;
2076 break;
2077 case 0x6821:
2078 si_pi->cac_weights = cac_weights_heathrow;
2079 si_pi->dte_data = dte_data_venus_xt;
2080 break;
2081 case 0x6823:
2082 case 0x682B:
2083 case 0x6822:
2084 case 0x682A:
2085 si_pi->cac_weights = cac_weights_chelsea_pro;
2086 si_pi->dte_data = dte_data_venus_pro;
2087 break;
2088 default:
2089 si_pi->cac_weights = cac_weights_cape_verde;
2090 si_pi->dte_data = dte_data_cape_verde;
2091 break;
2092 }
2093 } else if (adev->asic_type == CHIP_OLAND) {
Tom St Denisc3d986452016-09-06 09:44:47 -0400[diff] [blame]2094 si_pi->lcac_config = lcac_mars_pro;
2095 si_pi->cac_override = cac_override_oland;
2096 si_pi->powertune_data = &powertune_data_mars_pro;
2097 si_pi->dte_data = dte_data_mars_pro;
2098
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2099 switch (adev->pdev->device) {
2100 case 0x6601:
2101 case 0x6621:
2102 case 0x6603:
2103 case 0x6605:
2104 si_pi->cac_weights = cac_weights_mars_pro;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2105 update_dte_from_pl2 = true;
2106 break;
2107 case 0x6600:
2108 case 0x6606:
2109 case 0x6620:
2110 case 0x6604:
2111 si_pi->cac_weights = cac_weights_mars_xt;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2112 update_dte_from_pl2 = true;
2113 break;
2114 case 0x6611:
2115 case 0x6613:
2116 case 0x6608:
2117 si_pi->cac_weights = cac_weights_oland_pro;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2118 update_dte_from_pl2 = true;
2119 break;
2120 case 0x6610:
2121 si_pi->cac_weights = cac_weights_oland_xt;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2122 update_dte_from_pl2 = true;
2123 break;
2124 default:
2125 si_pi->cac_weights = cac_weights_oland;
2126 si_pi->lcac_config = lcac_oland;
2127 si_pi->cac_override = cac_override_oland;
2128 si_pi->powertune_data = &powertune_data_oland;
2129 si_pi->dte_data = dte_data_oland;
2130 break;
2131 }
2132 } else if (adev->asic_type == CHIP_HAINAN) {
2133 si_pi->cac_weights = cac_weights_hainan;
2134 si_pi->lcac_config = lcac_oland;
2135 si_pi->cac_override = cac_override_oland;
2136 si_pi->powertune_data = &powertune_data_hainan;
2137 si_pi->dte_data = dte_data_sun_xt;
2138 update_dte_from_pl2 = true;
2139 } else {
2140 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2141 return;
2142 }
2143
2144 ni_pi->enable_power_containment = false;
2145 ni_pi->enable_cac = false;
2146 ni_pi->enable_sq_ramping = false;
2147 si_pi->enable_dte = false;
2148
2149 if (si_pi->powertune_data->enable_powertune_by_default) {
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]2150 ni_pi->enable_power_containment = true;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2151 ni_pi->enable_cac = true;
2152 if (si_pi->dte_data.enable_dte_by_default) {
2153 si_pi->enable_dte = true;
2154 if (update_dte_from_pl2)
2155 si_update_dte_from_pl2(adev, &si_pi->dte_data);
2156
2157 }
2158 ni_pi->enable_sq_ramping = true;
2159 }
2160
2161 ni_pi->driver_calculate_cac_leakage = true;
2162 ni_pi->cac_configuration_required = true;
2163
2164 if (ni_pi->cac_configuration_required) {
2165 ni_pi->support_cac_long_term_average = true;
2166 si_pi->dyn_powertune_data.l2_lta_window_size =
2167 si_pi->powertune_data->l2_lta_window_size_default;
2168 si_pi->dyn_powertune_data.lts_truncate =
2169 si_pi->powertune_data->lts_truncate_default;
2170 } else {
2171 ni_pi->support_cac_long_term_average = false;
2172 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2173 si_pi->dyn_powertune_data.lts_truncate = 0;
2174 }
2175
2176 si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2177}
2178
2179static u32 si_get_smc_power_scaling_factor(struct amdgpu_device *adev)
2180{
2181 return 1;
2182}
2183
2184static u32 si_calculate_cac_wintime(struct amdgpu_device *adev)
2185{
2186 u32 xclk;
2187 u32 wintime;
2188 u32 cac_window;
2189 u32 cac_window_size;
2190
2191 xclk = amdgpu_asic_get_xclk(adev);
2192
2193 if (xclk == 0)
2194 return 0;
2195
2196 cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2197 cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2198
2199 wintime = (cac_window_size * 100) / xclk;
2200
2201 return wintime;
2202}
2203
2204static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2205{
2206 return power_in_watts;
2207}
2208
2209static int si_calculate_adjusted_tdp_limits(struct amdgpu_device *adev,
2210 bool adjust_polarity,
2211 u32 tdp_adjustment,
2212 u32 *tdp_limit,
2213 u32 *near_tdp_limit)
2214{
2215 u32 adjustment_delta, max_tdp_limit;
2216
2217 if (tdp_adjustment > (u32)adev->pm.dpm.tdp_od_limit)
2218 return -EINVAL;
2219
2220 max_tdp_limit = ((100 + 100) * adev->pm.dpm.tdp_limit) / 100;
2221
2222 if (adjust_polarity) {
2223 *tdp_limit = ((100 + tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2224 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - adev->pm.dpm.tdp_limit);
2225 } else {
2226 *tdp_limit = ((100 - tdp_adjustment) * adev->pm.dpm.tdp_limit) / 100;
2227 adjustment_delta = adev->pm.dpm.tdp_limit - *tdp_limit;
2228 if (adjustment_delta < adev->pm.dpm.near_tdp_limit_adjusted)
2229 *near_tdp_limit = adev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2230 else
2231 *near_tdp_limit = 0;
2232 }
2233
2234 if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2235 return -EINVAL;
2236 if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2237 return -EINVAL;
2238
2239 return 0;
2240}
2241
2242static int si_populate_smc_tdp_limits(struct amdgpu_device *adev,
2243 struct amdgpu_ps *amdgpu_state)
2244{
2245 struct ni_power_info *ni_pi = ni_get_pi(adev);
2246 struct si_power_info *si_pi = si_get_pi(adev);
2247
2248 if (ni_pi->enable_power_containment) {
2249 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2250 PP_SIslands_PAPMParameters *papm_parm;
2251 struct amdgpu_ppm_table *ppm = adev->pm.dpm.dyn_state.ppm_table;
2252 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2253 u32 tdp_limit;
2254 u32 near_tdp_limit;
2255 int ret;
2256
2257 if (scaling_factor == 0)
2258 return -EINVAL;
2259
2260 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2261
2262 ret = si_calculate_adjusted_tdp_limits(adev,
2263 false, /* ??? */
2264 adev->pm.dpm.tdp_adjustment,
2265 &tdp_limit,
2266 &near_tdp_limit);
2267 if (ret)
2268 return ret;
2269
2270 smc_table->dpm2Params.TDPLimit =
2271 cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2272 smc_table->dpm2Params.NearTDPLimit =
2273 cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2274 smc_table->dpm2Params.SafePowerLimit =
2275 cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2276
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2277 ret = amdgpu_si_copy_bytes_to_smc(adev,
2278 (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2279 offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2280 (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2281 sizeof(u32) * 3,
2282 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2283 if (ret)
2284 return ret;
2285
2286 if (si_pi->enable_ppm) {
2287 papm_parm = &si_pi->papm_parm;
2288 memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2289 papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2290 papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2291 papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2292 papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2293 papm_parm->PlatformPowerLimit = 0xffffffff;
2294 papm_parm->NearTDPLimitPAPM = 0xffffffff;
2295
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2296 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->papm_cfg_table_start,
2297 (u8 *)papm_parm,
2298 sizeof(PP_SIslands_PAPMParameters),
2299 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2300 if (ret)
2301 return ret;
2302 }
2303 }
2304 return 0;
2305}
2306
2307static int si_populate_smc_tdp_limits_2(struct amdgpu_device *adev,
2308 struct amdgpu_ps *amdgpu_state)
2309{
2310 struct ni_power_info *ni_pi = ni_get_pi(adev);
2311 struct si_power_info *si_pi = si_get_pi(adev);
2312
2313 if (ni_pi->enable_power_containment) {
2314 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2315 u32 scaling_factor = si_get_smc_power_scaling_factor(adev);
2316 int ret;
2317
2318 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2319
2320 smc_table->dpm2Params.NearTDPLimit =
2321 cpu_to_be32(si_scale_power_for_smc(adev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2322 smc_table->dpm2Params.SafePowerLimit =
2323 cpu_to_be32(si_scale_power_for_smc((adev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2324
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2325 ret = amdgpu_si_copy_bytes_to_smc(adev,
2326 (si_pi->state_table_start +
2327 offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2328 offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2329 (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2330 sizeof(u32) * 2,
2331 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2332 if (ret)
2333 return ret;
2334 }
2335
2336 return 0;
2337}
2338
2339static u16 si_calculate_power_efficiency_ratio(struct amdgpu_device *adev,
2340 const u16 prev_std_vddc,
2341 const u16 curr_std_vddc)
2342{
2343 u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2344 u64 prev_vddc = (u64)prev_std_vddc;
2345 u64 curr_vddc = (u64)curr_std_vddc;
2346 u64 pwr_efficiency_ratio, n, d;
2347
2348 if ((prev_vddc == 0) || (curr_vddc == 0))
2349 return 0;
2350
2351 n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2352 d = prev_vddc * prev_vddc;
2353 pwr_efficiency_ratio = div64_u64(n, d);
2354
2355 if (pwr_efficiency_ratio > (u64)0xFFFF)
2356 return 0;
2357
2358 return (u16)pwr_efficiency_ratio;
2359}
2360
2361static bool si_should_disable_uvd_powertune(struct amdgpu_device *adev,
2362 struct amdgpu_ps *amdgpu_state)
2363{
2364 struct si_power_info *si_pi = si_get_pi(adev);
2365
2366 if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2367 amdgpu_state->vclk && amdgpu_state->dclk)
2368 return true;
2369
2370 return false;
2371}
2372
2373struct evergreen_power_info *evergreen_get_pi(struct amdgpu_device *adev)
2374{
2375 struct evergreen_power_info *pi = adev->pm.dpm.priv;
2376
2377 return pi;
2378}
2379
2380static int si_populate_power_containment_values(struct amdgpu_device *adev,
2381 struct amdgpu_ps *amdgpu_state,
2382 SISLANDS_SMC_SWSTATE *smc_state)
2383{
2384 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
2385 struct ni_power_info *ni_pi = ni_get_pi(adev);
2386 struct si_ps *state = si_get_ps(amdgpu_state);
2387 SISLANDS_SMC_VOLTAGE_VALUE vddc;
2388 u32 prev_sclk;
2389 u32 max_sclk;
2390 u32 min_sclk;
2391 u16 prev_std_vddc;
2392 u16 curr_std_vddc;
2393 int i;
2394 u16 pwr_efficiency_ratio;
2395 u8 max_ps_percent;
2396 bool disable_uvd_power_tune;
2397 int ret;
2398
2399 if (ni_pi->enable_power_containment == false)
2400 return 0;
2401
2402 if (state->performance_level_count == 0)
2403 return -EINVAL;
2404
2405 if (smc_state->levelCount != state->performance_level_count)
2406 return -EINVAL;
2407
2408 disable_uvd_power_tune = si_should_disable_uvd_powertune(adev, amdgpu_state);
2409
2410 smc_state->levels[0].dpm2.MaxPS = 0;
2411 smc_state->levels[0].dpm2.NearTDPDec = 0;
2412 smc_state->levels[0].dpm2.AboveSafeInc = 0;
2413 smc_state->levels[0].dpm2.BelowSafeInc = 0;
2414 smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2415
2416 for (i = 1; i < state->performance_level_count; i++) {
2417 prev_sclk = state->performance_levels[i-1].sclk;
2418 max_sclk = state->performance_levels[i].sclk;
2419 if (i == 1)
2420 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2421 else
2422 max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2423
2424 if (prev_sclk > max_sclk)
2425 return -EINVAL;
2426
2427 if ((max_ps_percent == 0) ||
2428 (prev_sclk == max_sclk) ||
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]2429 disable_uvd_power_tune)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2430 min_sclk = max_sclk;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]2431 else if (i == 1)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2432 min_sclk = prev_sclk;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]2433 else
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2434 min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2435
2436 if (min_sclk < state->performance_levels[0].sclk)
2437 min_sclk = state->performance_levels[0].sclk;
2438
2439 if (min_sclk == 0)
2440 return -EINVAL;
2441
2442 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2443 state->performance_levels[i-1].vddc, &vddc);
2444 if (ret)
2445 return ret;
2446
2447 ret = si_get_std_voltage_value(adev, &vddc, &prev_std_vddc);
2448 if (ret)
2449 return ret;
2450
2451 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
2452 state->performance_levels[i].vddc, &vddc);
2453 if (ret)
2454 return ret;
2455
2456 ret = si_get_std_voltage_value(adev, &vddc, &curr_std_vddc);
2457 if (ret)
2458 return ret;
2459
2460 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(adev,
2461 prev_std_vddc, curr_std_vddc);
2462
2463 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2464 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2465 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2466 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2467 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2468 }
2469
2470 return 0;
2471}
2472
2473static int si_populate_sq_ramping_values(struct amdgpu_device *adev,
2474 struct amdgpu_ps *amdgpu_state,
2475 SISLANDS_SMC_SWSTATE *smc_state)
2476{
2477 struct ni_power_info *ni_pi = ni_get_pi(adev);
2478 struct si_ps *state = si_get_ps(amdgpu_state);
2479 u32 sq_power_throttle, sq_power_throttle2;
2480 bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2481 int i;
2482
2483 if (state->performance_level_count == 0)
2484 return -EINVAL;
2485
2486 if (smc_state->levelCount != state->performance_level_count)
2487 return -EINVAL;
2488
2489 if (adev->pm.dpm.sq_ramping_threshold == 0)
2490 return -EINVAL;
2491
2492 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2493 enable_sq_ramping = false;
2494
2495 if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2496 enable_sq_ramping = false;
2497
2498 if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2499 enable_sq_ramping = false;
2500
2501 if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2502 enable_sq_ramping = false;
2503
2504 if (SISLANDS_DPM2_SQ_RAMP_LTI_RATIO > (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2505 enable_sq_ramping = false;
2506
2507 for (i = 0; i < state->performance_level_count; i++) {
2508 sq_power_throttle = 0;
2509 sq_power_throttle2 = 0;
2510
2511 if ((state->performance_levels[i].sclk >= adev->pm.dpm.sq_ramping_threshold) &&
2512 enable_sq_ramping) {
2513 sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2514 sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2515 sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2516 sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2517 sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2518 } else {
2519 sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2520 sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2521 }
2522
2523 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2524 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2525 }
2526
2527 return 0;
2528}
2529
2530static int si_enable_power_containment(struct amdgpu_device *adev,
2531 struct amdgpu_ps *amdgpu_new_state,
2532 bool enable)
2533{
2534 struct ni_power_info *ni_pi = ni_get_pi(adev);
2535 PPSMC_Result smc_result;
2536 int ret = 0;
2537
2538 if (ni_pi->enable_power_containment) {
2539 if (enable) {
2540 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2541 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingActive);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2542 if (smc_result != PPSMC_Result_OK) {
2543 ret = -EINVAL;
2544 ni_pi->pc_enabled = false;
2545 } else {
2546 ni_pi->pc_enabled = true;
2547 }
2548 }
2549 } else {
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2550 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_TDPClampingInactive);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2551 if (smc_result != PPSMC_Result_OK)
2552 ret = -EINVAL;
2553 ni_pi->pc_enabled = false;
2554 }
2555 }
2556
2557 return ret;
2558}
2559
2560static int si_initialize_smc_dte_tables(struct amdgpu_device *adev)
2561{
2562 struct si_power_info *si_pi = si_get_pi(adev);
2563 int ret = 0;
2564 struct si_dte_data *dte_data = &si_pi->dte_data;
2565 Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2566 u32 table_size;
2567 u8 tdep_count;
2568 u32 i;
2569
2570 if (dte_data == NULL)
2571 si_pi->enable_dte = false;
2572
2573 if (si_pi->enable_dte == false)
2574 return 0;
2575
2576 if (dte_data->k <= 0)
2577 return -EINVAL;
2578
2579 dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2580 if (dte_tables == NULL) {
2581 si_pi->enable_dte = false;
2582 return -ENOMEM;
2583 }
2584
2585 table_size = dte_data->k;
2586
2587 if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2588 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2589
2590 tdep_count = dte_data->tdep_count;
2591 if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2592 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2593
2594 dte_tables->K = cpu_to_be32(table_size);
2595 dte_tables->T0 = cpu_to_be32(dte_data->t0);
2596 dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2597 dte_tables->WindowSize = dte_data->window_size;
2598 dte_tables->temp_select = dte_data->temp_select;
2599 dte_tables->DTE_mode = dte_data->dte_mode;
2600 dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2601
2602 if (tdep_count > 0)
2603 table_size--;
2604
2605 for (i = 0; i < table_size; i++) {
2606 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2607 dte_tables->R[i] = cpu_to_be32(dte_data->r[i]);
2608 }
2609
2610 dte_tables->Tdep_count = tdep_count;
2611
2612 for (i = 0; i < (u32)tdep_count; i++) {
2613 dte_tables->T_limits[i] = dte_data->t_limits[i];
2614 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2615 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2616 }
2617
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2618 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->dte_table_start,
2619 (u8 *)dte_tables,
2620 sizeof(Smc_SIslands_DTE_Configuration),
2621 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2622 kfree(dte_tables);
2623
2624 return ret;
2625}
2626
2627static int si_get_cac_std_voltage_max_min(struct amdgpu_device *adev,
2628 u16 *max, u16 *min)
2629{
2630 struct si_power_info *si_pi = si_get_pi(adev);
2631 struct amdgpu_cac_leakage_table *table =
2632 &adev->pm.dpm.dyn_state.cac_leakage_table;
2633 u32 i;
2634 u32 v0_loadline;
2635
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2636 if (table == NULL)
2637 return -EINVAL;
2638
2639 *max = 0;
2640 *min = 0xFFFF;
2641
2642 for (i = 0; i < table->count; i++) {
2643 if (table->entries[i].vddc > *max)
2644 *max = table->entries[i].vddc;
2645 if (table->entries[i].vddc < *min)
2646 *min = table->entries[i].vddc;
2647 }
2648
2649 if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2650 return -EINVAL;
2651
2652 v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2653
2654 if (v0_loadline > 0xFFFFUL)
2655 return -EINVAL;
2656
2657 *min = (u16)v0_loadline;
2658
2659 if ((*min > *max) || (*max == 0) || (*min == 0))
2660 return -EINVAL;
2661
2662 return 0;
2663}
2664
2665static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2666{
2667 return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2668 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2669}
2670
2671static int si_init_dte_leakage_table(struct amdgpu_device *adev,
2672 PP_SIslands_CacConfig *cac_tables,
2673 u16 vddc_max, u16 vddc_min, u16 vddc_step,
2674 u16 t0, u16 t_step)
2675{
2676 struct si_power_info *si_pi = si_get_pi(adev);
2677 u32 leakage;
2678 unsigned int i, j;
2679 s32 t;
2680 u32 smc_leakage;
2681 u32 scaling_factor;
2682 u16 voltage;
2683
2684 scaling_factor = si_get_smc_power_scaling_factor(adev);
2685
2686 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2687 t = (1000 * (i * t_step + t0));
2688
2689 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2690 voltage = vddc_max - (vddc_step * j);
2691
2692 si_calculate_leakage_for_v_and_t(adev,
2693 &si_pi->powertune_data->leakage_coefficients,
2694 voltage,
2695 t,
2696 si_pi->dyn_powertune_data.cac_leakage,
2697 &leakage);
2698
2699 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2700
2701 if (smc_leakage > 0xFFFF)
2702 smc_leakage = 0xFFFF;
2703
2704 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2705 cpu_to_be16((u16)smc_leakage);
2706 }
2707 }
2708 return 0;
2709}
2710
2711static int si_init_simplified_leakage_table(struct amdgpu_device *adev,
2712 PP_SIslands_CacConfig *cac_tables,
2713 u16 vddc_max, u16 vddc_min, u16 vddc_step)
2714{
2715 struct si_power_info *si_pi = si_get_pi(adev);
2716 u32 leakage;
2717 unsigned int i, j;
2718 u32 smc_leakage;
2719 u32 scaling_factor;
2720 u16 voltage;
2721
2722 scaling_factor = si_get_smc_power_scaling_factor(adev);
2723
2724 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2725 voltage = vddc_max - (vddc_step * j);
2726
2727 si_calculate_leakage_for_v(adev,
2728 &si_pi->powertune_data->leakage_coefficients,
2729 si_pi->powertune_data->fixed_kt,
2730 voltage,
2731 si_pi->dyn_powertune_data.cac_leakage,
2732 &leakage);
2733
2734 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2735
2736 if (smc_leakage > 0xFFFF)
2737 smc_leakage = 0xFFFF;
2738
2739 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2740 cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2741 cpu_to_be16((u16)smc_leakage);
2742 }
2743 return 0;
2744}
2745
2746static int si_initialize_smc_cac_tables(struct amdgpu_device *adev)
2747{
2748 struct ni_power_info *ni_pi = ni_get_pi(adev);
2749 struct si_power_info *si_pi = si_get_pi(adev);
2750 PP_SIslands_CacConfig *cac_tables = NULL;
2751 u16 vddc_max, vddc_min, vddc_step;
2752 u16 t0, t_step;
2753 u32 load_line_slope, reg;
2754 int ret = 0;
2755 u32 ticks_per_us = amdgpu_asic_get_xclk(adev) / 100;
2756
2757 if (ni_pi->enable_cac == false)
2758 return 0;
2759
2760 cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2761 if (!cac_tables)
2762 return -ENOMEM;
2763
2764 reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2765 reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2766 WREG32(CG_CAC_CTRL, reg);
2767
2768 si_pi->dyn_powertune_data.cac_leakage = adev->pm.dpm.cac_leakage;
2769 si_pi->dyn_powertune_data.dc_pwr_value =
2770 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2771 si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(adev);
2772 si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2773
2774 si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2775
2776 ret = si_get_cac_std_voltage_max_min(adev, &vddc_max, &vddc_min);
2777 if (ret)
2778 goto done_free;
2779
2780 vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2781 vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2782 t_step = 4;
2783 t0 = 60;
2784
2785 if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2786 ret = si_init_dte_leakage_table(adev, cac_tables,
2787 vddc_max, vddc_min, vddc_step,
2788 t0, t_step);
2789 else
2790 ret = si_init_simplified_leakage_table(adev, cac_tables,
2791 vddc_max, vddc_min, vddc_step);
2792 if (ret)
2793 goto done_free;
2794
2795 load_line_slope = ((u32)adev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2796
2797 cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2798 cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2799 cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2800 cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2801 cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2802 cac_tables->R_LL = cpu_to_be32(load_line_slope);
2803 cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2804 cac_tables->calculation_repeats = cpu_to_be32(2);
2805 cac_tables->dc_cac = cpu_to_be32(0);
2806 cac_tables->log2_PG_LKG_SCALE = 12;
2807 cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2808 cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2809 cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2810
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2811 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->cac_table_start,
2812 (u8 *)cac_tables,
2813 sizeof(PP_SIslands_CacConfig),
2814 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2815
2816 if (ret)
2817 goto done_free;
2818
2819 ret = si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2820
2821done_free:
2822 if (ret) {
2823 ni_pi->enable_cac = false;
2824 ni_pi->enable_power_containment = false;
2825 }
2826
2827 kfree(cac_tables);
2828
Tom St Denisad2473a2016-09-07 08:42:41 -0400[diff] [blame]2829 return ret;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2830}
2831
2832static int si_program_cac_config_registers(struct amdgpu_device *adev,
2833 const struct si_cac_config_reg *cac_config_regs)
2834{
2835 const struct si_cac_config_reg *config_regs = cac_config_regs;
2836 u32 data = 0, offset;
2837
2838 if (!config_regs)
2839 return -EINVAL;
2840
2841 while (config_regs->offset != 0xFFFFFFFF) {
2842 switch (config_regs->type) {
2843 case SISLANDS_CACCONFIG_CGIND:
2844 offset = SMC_CG_IND_START + config_regs->offset;
2845 if (offset < SMC_CG_IND_END)
2846 data = RREG32_SMC(offset);
2847 break;
2848 default:
2849 data = RREG32(config_regs->offset);
2850 break;
2851 }
2852
2853 data &= ~config_regs->mask;
2854 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2855
2856 switch (config_regs->type) {
2857 case SISLANDS_CACCONFIG_CGIND:
2858 offset = SMC_CG_IND_START + config_regs->offset;
2859 if (offset < SMC_CG_IND_END)
2860 WREG32_SMC(offset, data);
2861 break;
2862 default:
2863 WREG32(config_regs->offset, data);
2864 break;
2865 }
2866 config_regs++;
2867 }
2868 return 0;
2869}
2870
2871static int si_initialize_hardware_cac_manager(struct amdgpu_device *adev)
2872{
2873 struct ni_power_info *ni_pi = ni_get_pi(adev);
2874 struct si_power_info *si_pi = si_get_pi(adev);
2875 int ret;
2876
2877 if ((ni_pi->enable_cac == false) ||
2878 (ni_pi->cac_configuration_required == false))
2879 return 0;
2880
2881 ret = si_program_cac_config_registers(adev, si_pi->lcac_config);
2882 if (ret)
2883 return ret;
2884 ret = si_program_cac_config_registers(adev, si_pi->cac_override);
2885 if (ret)
2886 return ret;
2887 ret = si_program_cac_config_registers(adev, si_pi->cac_weights);
2888 if (ret)
2889 return ret;
2890
2891 return 0;
2892}
2893
2894static int si_enable_smc_cac(struct amdgpu_device *adev,
2895 struct amdgpu_ps *amdgpu_new_state,
2896 bool enable)
2897{
2898 struct ni_power_info *ni_pi = ni_get_pi(adev);
2899 struct si_power_info *si_pi = si_get_pi(adev);
2900 PPSMC_Result smc_result;
2901 int ret = 0;
2902
2903 if (ni_pi->enable_cac) {
2904 if (enable) {
2905 if (!si_should_disable_uvd_powertune(adev, amdgpu_new_state)) {
2906 if (ni_pi->support_cac_long_term_average) {
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2907 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgEnable);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2908 if (smc_result != PPSMC_Result_OK)
2909 ni_pi->support_cac_long_term_average = false;
2910 }
2911
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2912 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableCac);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2913 if (smc_result != PPSMC_Result_OK) {
2914 ret = -EINVAL;
2915 ni_pi->cac_enabled = false;
2916 } else {
2917 ni_pi->cac_enabled = true;
2918 }
2919
2920 if (si_pi->enable_dte) {
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2921 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableDTE);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2922 if (smc_result != PPSMC_Result_OK)
2923 ret = -EINVAL;
2924 }
2925 }
2926 } else if (ni_pi->cac_enabled) {
2927 if (si_pi->enable_dte)
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2928 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableDTE);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2929
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2930 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableCac);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2931
2932 ni_pi->cac_enabled = false;
2933
2934 if (ni_pi->support_cac_long_term_average)
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2935 smc_result = amdgpu_si_send_msg_to_smc(adev, PPSMC_CACLongTermAvgDisable);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]2936 }
2937 }
2938 return ret;
2939}
2940
2941static int si_init_smc_spll_table(struct amdgpu_device *adev)
2942{
2943 struct ni_power_info *ni_pi = ni_get_pi(adev);
2944 struct si_power_info *si_pi = si_get_pi(adev);
2945 SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2946 SISLANDS_SMC_SCLK_VALUE sclk_params;
2947 u32 fb_div, p_div;
2948 u32 clk_s, clk_v;
2949 u32 sclk = 0;
2950 int ret = 0;
2951 u32 tmp;
2952 int i;
2953
2954 if (si_pi->spll_table_start == 0)
2955 return -EINVAL;
2956
2957 spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2958 if (spll_table == NULL)
2959 return -ENOMEM;
2960
2961 for (i = 0; i < 256; i++) {
2962 ret = si_calculate_sclk_params(adev, sclk, &sclk_params);
2963 if (ret)
2964 break;
2965 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2966 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2967 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2968 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2969
2970 fb_div &= ~0x00001FFF;
2971 fb_div >>= 1;
2972 clk_v >>= 6;
2973
2974 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2975 ret = -EINVAL;
2976 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2977 ret = -EINVAL;
2978 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2979 ret = -EINVAL;
2980 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2981 ret = -EINVAL;
2982
2983 if (ret)
2984 break;
2985
2986 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2987 ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2988 spll_table->freq[i] = cpu_to_be32(tmp);
2989
2990 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2991 ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2992 spll_table->ss[i] = cpu_to_be32(tmp);
2993
2994 sclk += 512;
2995 }
2996
2997
2998 if (!ret)
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]2999 ret = amdgpu_si_copy_bytes_to_smc(adev, si_pi->spll_table_start,
3000 (u8 *)spll_table,
3001 sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
3002 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3003
3004 if (ret)
3005 ni_pi->enable_power_containment = false;
3006
3007 kfree(spll_table);
3008
3009 return ret;
3010}
3011
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3012static u16 si_get_lower_of_leakage_and_vce_voltage(struct amdgpu_device *adev,
3013 u16 vce_voltage)
3014{
3015 u16 highest_leakage = 0;
3016 struct si_power_info *si_pi = si_get_pi(adev);
3017 int i;
3018
3019 for (i = 0; i < si_pi->leakage_voltage.count; i++){
3020 if (highest_leakage < si_pi->leakage_voltage.entries[i].voltage)
3021 highest_leakage = si_pi->leakage_voltage.entries[i].voltage;
3022 }
3023
3024 if (si_pi->leakage_voltage.count && (highest_leakage < vce_voltage))
3025 return highest_leakage;
3026
3027 return vce_voltage;
3028}
3029
3030static int si_get_vce_clock_voltage(struct amdgpu_device *adev,
3031 u32 evclk, u32 ecclk, u16 *voltage)
3032{
3033 u32 i;
3034 int ret = -EINVAL;
3035 struct amdgpu_vce_clock_voltage_dependency_table *table =
3036 &adev->pm.dpm.dyn_state.vce_clock_voltage_dependency_table;
3037
3038 if (((evclk == 0) && (ecclk == 0)) ||
3039 (table && (table->count == 0))) {
3040 *voltage = 0;
3041 return 0;
3042 }
3043
3044 for (i = 0; i < table->count; i++) {
3045 if ((evclk <= table->entries[i].evclk) &&
3046 (ecclk <= table->entries[i].ecclk)) {
3047 *voltage = table->entries[i].v;
3048 ret = 0;
3049 break;
3050 }
3051 }
3052
3053 /* if no match return the highest voltage */
3054 if (ret)
3055 *voltage = table->entries[table->count - 1].v;
3056
3057 *voltage = si_get_lower_of_leakage_and_vce_voltage(adev, *voltage);
3058
3059 return ret;
3060}
3061
3062static bool si_dpm_vblank_too_short(struct amdgpu_device *adev)
3063{
3064
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3065 u32 vblank_time = amdgpu_dpm_get_vblank_time(adev);
3066 /* we never hit the non-gddr5 limit so disable it */
3067 u32 switch_limit = adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5 ? 450 : 0;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3068
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3069 if (vblank_time < switch_limit)
3070 return true;
3071 else
3072 return false;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3073
3074}
3075
3076static int ni_copy_and_switch_arb_sets(struct amdgpu_device *adev,
3077 u32 arb_freq_src, u32 arb_freq_dest)
3078{
3079 u32 mc_arb_dram_timing;
3080 u32 mc_arb_dram_timing2;
3081 u32 burst_time;
3082 u32 mc_cg_config;
3083
3084 switch (arb_freq_src) {
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3085 case MC_CG_ARB_FREQ_F0:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3086 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING);
3087 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
3088 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE0_MASK) >> STATE0_SHIFT;
3089 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3090 case MC_CG_ARB_FREQ_F1:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3091 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_1);
3092 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_1);
3093 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE1_MASK) >> STATE1_SHIFT;
3094 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3095 case MC_CG_ARB_FREQ_F2:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3096 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_2);
3097 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_2);
3098 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE2_MASK) >> STATE2_SHIFT;
3099 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3100 case MC_CG_ARB_FREQ_F3:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3101 mc_arb_dram_timing = RREG32(MC_ARB_DRAM_TIMING_3);
3102 mc_arb_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2_3);
3103 burst_time = (RREG32(MC_ARB_BURST_TIME) & STATE3_MASK) >> STATE3_SHIFT;
3104 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3105 default:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3106 return -EINVAL;
3107 }
3108
3109 switch (arb_freq_dest) {
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3110 case MC_CG_ARB_FREQ_F0:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3111 WREG32(MC_ARB_DRAM_TIMING, mc_arb_dram_timing);
3112 WREG32(MC_ARB_DRAM_TIMING2, mc_arb_dram_timing2);
3113 WREG32_P(MC_ARB_BURST_TIME, STATE0(burst_time), ~STATE0_MASK);
3114 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3115 case MC_CG_ARB_FREQ_F1:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3116 WREG32(MC_ARB_DRAM_TIMING_1, mc_arb_dram_timing);
3117 WREG32(MC_ARB_DRAM_TIMING2_1, mc_arb_dram_timing2);
3118 WREG32_P(MC_ARB_BURST_TIME, STATE1(burst_time), ~STATE1_MASK);
3119 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3120 case MC_CG_ARB_FREQ_F2:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3121 WREG32(MC_ARB_DRAM_TIMING_2, mc_arb_dram_timing);
3122 WREG32(MC_ARB_DRAM_TIMING2_2, mc_arb_dram_timing2);
3123 WREG32_P(MC_ARB_BURST_TIME, STATE2(burst_time), ~STATE2_MASK);
3124 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3125 case MC_CG_ARB_FREQ_F3:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3126 WREG32(MC_ARB_DRAM_TIMING_3, mc_arb_dram_timing);
3127 WREG32(MC_ARB_DRAM_TIMING2_3, mc_arb_dram_timing2);
3128 WREG32_P(MC_ARB_BURST_TIME, STATE3(burst_time), ~STATE3_MASK);
3129 break;
3130 default:
3131 return -EINVAL;
3132 }
3133
3134 mc_cg_config = RREG32(MC_CG_CONFIG) | 0x0000000F;
3135 WREG32(MC_CG_CONFIG, mc_cg_config);
3136 WREG32_P(MC_ARB_CG, CG_ARB_REQ(arb_freq_dest), ~CG_ARB_REQ_MASK);
3137
3138 return 0;
3139}
3140
3141static void ni_update_current_ps(struct amdgpu_device *adev,
3142 struct amdgpu_ps *rps)
3143{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3144 struct si_ps *new_ps = si_get_ps(rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3145 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3146 struct ni_power_info *ni_pi = ni_get_pi(adev);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3147
3148 eg_pi->current_rps = *rps;
3149 ni_pi->current_ps = *new_ps;
3150 eg_pi->current_rps.ps_priv = &ni_pi->current_ps;
Rex Zhu8c8e2c32016-10-14 19:29:02 +0800[diff] [blame]3151 adev->pm.dpm.current_ps = &eg_pi->current_rps;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3152}
3153
3154static void ni_update_requested_ps(struct amdgpu_device *adev,
3155 struct amdgpu_ps *rps)
3156{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3157 struct si_ps *new_ps = si_get_ps(rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3158 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3159 struct ni_power_info *ni_pi = ni_get_pi(adev);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3160
3161 eg_pi->requested_rps = *rps;
3162 ni_pi->requested_ps = *new_ps;
3163 eg_pi->requested_rps.ps_priv = &ni_pi->requested_ps;
Rex Zhu8c8e2c32016-10-14 19:29:02 +0800[diff] [blame]3164 adev->pm.dpm.requested_ps = &eg_pi->requested_rps;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3165}
3166
3167static void ni_set_uvd_clock_before_set_eng_clock(struct amdgpu_device *adev,
3168 struct amdgpu_ps *new_ps,
3169 struct amdgpu_ps *old_ps)
3170{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3171 struct si_ps *new_state = si_get_ps(new_ps);
3172 struct si_ps *current_state = si_get_ps(old_ps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3173
3174 if ((new_ps->vclk == old_ps->vclk) &&
3175 (new_ps->dclk == old_ps->dclk))
3176 return;
3177
3178 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
3179 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3180 return;
3181
3182 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3183}
3184
3185static void ni_set_uvd_clock_after_set_eng_clock(struct amdgpu_device *adev,
3186 struct amdgpu_ps *new_ps,
3187 struct amdgpu_ps *old_ps)
3188{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3189 struct si_ps *new_state = si_get_ps(new_ps);
3190 struct si_ps *current_state = si_get_ps(old_ps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3191
3192 if ((new_ps->vclk == old_ps->vclk) &&
3193 (new_ps->dclk == old_ps->dclk))
3194 return;
3195
3196 if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
3197 current_state->performance_levels[current_state->performance_level_count - 1].sclk)
3198 return;
3199
3200 amdgpu_asic_set_uvd_clocks(adev, new_ps->vclk, new_ps->dclk);
3201}
3202
3203static u16 btc_find_voltage(struct atom_voltage_table *table, u16 voltage)
3204{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3205 unsigned int i;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3206
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3207 for (i = 0; i < table->count; i++)
3208 if (voltage <= table->entries[i].value)
3209 return table->entries[i].value;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3210
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3211 return table->entries[table->count - 1].value;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3212}
3213
3214static u32 btc_find_valid_clock(struct amdgpu_clock_array *clocks,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3215 u32 max_clock, u32 requested_clock)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3216{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3217 unsigned int i;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3218
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3219 if ((clocks == NULL) || (clocks->count == 0))
3220 return (requested_clock < max_clock) ? requested_clock : max_clock;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3221
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3222 for (i = 0; i < clocks->count; i++) {
3223 if (clocks->values[i] >= requested_clock)
3224 return (clocks->values[i] < max_clock) ? clocks->values[i] : max_clock;
3225 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3226
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3227 return (clocks->values[clocks->count - 1] < max_clock) ?
3228 clocks->values[clocks->count - 1] : max_clock;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3229}
3230
3231static u32 btc_get_valid_mclk(struct amdgpu_device *adev,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3232 u32 max_mclk, u32 requested_mclk)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3233{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3234 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_mclk_values,
3235 max_mclk, requested_mclk);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3236}
3237
3238static u32 btc_get_valid_sclk(struct amdgpu_device *adev,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3239 u32 max_sclk, u32 requested_sclk)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3240{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3241 return btc_find_valid_clock(&adev->pm.dpm.dyn_state.valid_sclk_values,
3242 max_sclk, requested_sclk);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3243}
3244
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]3245static void btc_get_max_clock_from_voltage_dependency_table(struct amdgpu_clock_voltage_dependency_table *table,
3246 u32 *max_clock)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3247{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3248 u32 i, clock = 0;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3249
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3250 if ((table == NULL) || (table->count == 0)) {
3251 *max_clock = clock;
3252 return;
3253 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3254
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3255 for (i = 0; i < table->count; i++) {
3256 if (clock < table->entries[i].clk)
3257 clock = table->entries[i].clk;
3258 }
3259 *max_clock = clock;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3260}
3261
3262static void btc_apply_voltage_dependency_rules(struct amdgpu_clock_voltage_dependency_table *table,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3263 u32 clock, u16 max_voltage, u16 *voltage)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3264{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3265 u32 i;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3266
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3267 if ((table == NULL) || (table->count == 0))
3268 return;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3269
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3270 for (i= 0; i < table->count; i++) {
3271 if (clock <= table->entries[i].clk) {
3272 if (*voltage < table->entries[i].v)
3273 *voltage = (u16)((table->entries[i].v < max_voltage) ?
3274 table->entries[i].v : max_voltage);
3275 return;
3276 }
3277 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3278
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3279 *voltage = (*voltage > max_voltage) ? *voltage : max_voltage;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3280}
3281
3282static void btc_adjust_clock_combinations(struct amdgpu_device *adev,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3283 const struct amdgpu_clock_and_voltage_limits *max_limits,
3284 struct rv7xx_pl *pl)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3285{
3286
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3287 if ((pl->mclk == 0) || (pl->sclk == 0))
3288 return;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3289
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3290 if (pl->mclk == pl->sclk)
3291 return;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3292
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3293 if (pl->mclk > pl->sclk) {
3294 if (((pl->mclk + (pl->sclk - 1)) / pl->sclk) > adev->pm.dpm.dyn_state.mclk_sclk_ratio)
3295 pl->sclk = btc_get_valid_sclk(adev,
3296 max_limits->sclk,
3297 (pl->mclk +
3298 (adev->pm.dpm.dyn_state.mclk_sclk_ratio - 1)) /
3299 adev->pm.dpm.dyn_state.mclk_sclk_ratio);
3300 } else {
3301 if ((pl->sclk - pl->mclk) > adev->pm.dpm.dyn_state.sclk_mclk_delta)
3302 pl->mclk = btc_get_valid_mclk(adev,
3303 max_limits->mclk,
3304 pl->sclk -
3305 adev->pm.dpm.dyn_state.sclk_mclk_delta);
3306 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3307}
3308
3309static void btc_apply_voltage_delta_rules(struct amdgpu_device *adev,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3310 u16 max_vddc, u16 max_vddci,
3311 u16 *vddc, u16 *vddci)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3312{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3313 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
3314 u16 new_voltage;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3315
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3316 if ((0 == *vddc) || (0 == *vddci))
3317 return;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3318
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3319 if (*vddc > *vddci) {
3320 if ((*vddc - *vddci) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3321 new_voltage = btc_find_voltage(&eg_pi->vddci_voltage_table,
3322 (*vddc - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3323 *vddci = (new_voltage < max_vddci) ? new_voltage : max_vddci;
3324 }
3325 } else {
3326 if ((*vddci - *vddc) > adev->pm.dpm.dyn_state.vddc_vddci_delta) {
3327 new_voltage = btc_find_voltage(&eg_pi->vddc_voltage_table,
3328 (*vddci - adev->pm.dpm.dyn_state.vddc_vddci_delta));
3329 *vddc = (new_voltage < max_vddc) ? new_voltage : max_vddc;
3330 }
3331 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3332}
3333
3334static enum amdgpu_pcie_gen r600_get_pcie_gen_support(struct amdgpu_device *adev,
3335 u32 sys_mask,
3336 enum amdgpu_pcie_gen asic_gen,
3337 enum amdgpu_pcie_gen default_gen)
3338{
3339 switch (asic_gen) {
3340 case AMDGPU_PCIE_GEN1:
3341 return AMDGPU_PCIE_GEN1;
3342 case AMDGPU_PCIE_GEN2:
3343 return AMDGPU_PCIE_GEN2;
3344 case AMDGPU_PCIE_GEN3:
3345 return AMDGPU_PCIE_GEN3;
3346 default:
3347 if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == AMDGPU_PCIE_GEN3))
3348 return AMDGPU_PCIE_GEN3;
3349 else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == AMDGPU_PCIE_GEN2))
3350 return AMDGPU_PCIE_GEN2;
3351 else
3352 return AMDGPU_PCIE_GEN1;
3353 }
3354 return AMDGPU_PCIE_GEN1;
3355}
3356
3357static void r600_calculate_u_and_p(u32 i, u32 r_c, u32 p_b,
3358 u32 *p, u32 *u)
3359{
3360 u32 b_c = 0;
3361 u32 i_c;
3362 u32 tmp;
3363
3364 i_c = (i * r_c) / 100;
3365 tmp = i_c >> p_b;
3366
3367 while (tmp) {
3368 b_c++;
3369 tmp >>= 1;
3370 }
3371
3372 *u = (b_c + 1) / 2;
3373 *p = i_c / (1 << (2 * (*u)));
3374}
3375
3376static int r600_calculate_at(u32 t, u32 h, u32 fh, u32 fl, u32 *tl, u32 *th)
3377{
3378 u32 k, a, ah, al;
3379 u32 t1;
3380
3381 if ((fl == 0) || (fh == 0) || (fl > fh))
3382 return -EINVAL;
3383
3384 k = (100 * fh) / fl;
3385 t1 = (t * (k - 100));
3386 a = (1000 * (100 * h + t1)) / (10000 + (t1 / 100));
3387 a = (a + 5) / 10;
3388 ah = ((a * t) + 5000) / 10000;
3389 al = a - ah;
3390
3391 *th = t - ah;
3392 *tl = t + al;
3393
3394 return 0;
3395}
3396
3397static bool r600_is_uvd_state(u32 class, u32 class2)
3398{
3399 if (class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
3400 return true;
3401 if (class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
3402 return true;
3403 if (class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
3404 return true;
3405 if (class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
3406 return true;
3407 if (class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
3408 return true;
3409 return false;
3410}
3411
3412static u8 rv770_get_memory_module_index(struct amdgpu_device *adev)
3413{
3414 return (u8) ((RREG32(BIOS_SCRATCH_4) >> 16) & 0xff);
3415}
3416
3417static void rv770_get_max_vddc(struct amdgpu_device *adev)
3418{
3419 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3420 u16 vddc;
3421
3422 if (amdgpu_atombios_get_max_vddc(adev, 0, 0, &vddc))
3423 pi->max_vddc = 0;
3424 else
3425 pi->max_vddc = vddc;
3426}
3427
3428static void rv770_get_engine_memory_ss(struct amdgpu_device *adev)
3429{
3430 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3431 struct amdgpu_atom_ss ss;
3432
3433 pi->sclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3434 ASIC_INTERNAL_ENGINE_SS, 0);
3435 pi->mclk_ss = amdgpu_atombios_get_asic_ss_info(adev, &ss,
3436 ASIC_INTERNAL_MEMORY_SS, 0);
3437
3438 if (pi->sclk_ss || pi->mclk_ss)
3439 pi->dynamic_ss = true;
3440 else
3441 pi->dynamic_ss = false;
3442}
3443
3444
3445static void si_apply_state_adjust_rules(struct amdgpu_device *adev,
3446 struct amdgpu_ps *rps)
3447{
3448 struct si_ps *ps = si_get_ps(rps);
3449 struct amdgpu_clock_and_voltage_limits *max_limits;
3450 bool disable_mclk_switching = false;
3451 bool disable_sclk_switching = false;
3452 u32 mclk, sclk;
3453 u16 vddc, vddci, min_vce_voltage = 0;
3454 u32 max_sclk_vddc, max_mclk_vddci, max_mclk_vddc;
3455 u32 max_sclk = 0, max_mclk = 0;
3456 int i;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3457
Alex Deucher85d2fce2017-01-24 16:59:35 -0500[diff] [blame]3458 if (adev->asic_type == CHIP_HAINAN) {
Alex Deucher71451bd2016-10-26 15:27:45 -0400[diff] [blame]3459 if ((adev->pdev->revision == 0x81) ||
3460 (adev->pdev->revision == 0x83) ||
3461 (adev->pdev->revision == 0xC3) ||
3462 (adev->pdev->device == 0x6664) ||
3463 (adev->pdev->device == 0x6665) ||
3464 (adev->pdev->device == 0x6667)) {
3465 max_sclk = 75000;
Alex Deucher71451bd2016-10-26 15:27:45 -0400[diff] [blame]3466 }
Alex Deucher18a8de12017-03-14 19:24:19 -0400[diff] [blame^]3467 } else if (adev->asic_type == CHIP_OLAND) {
3468 if ((adev->pdev->device == 0x6604) &&
3469 (adev->pdev->subsystem_vendor == 0x1028) &&
3470 (adev->pdev->subsystem_device == 0x066F)) {
3471 max_sclk = 75000;
3472 }
Alex Deucher71451bd2016-10-26 15:27:45 -0400[diff] [blame]3473 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3474
3475 if (rps->vce_active) {
3476 rps->evclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].evclk;
3477 rps->ecclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].ecclk;
3478 si_get_vce_clock_voltage(adev, rps->evclk, rps->ecclk,
3479 &min_vce_voltage);
3480 } else {
3481 rps->evclk = 0;
3482 rps->ecclk = 0;
3483 }
3484
3485 if ((adev->pm.dpm.new_active_crtc_count > 1) ||
3486 si_dpm_vblank_too_short(adev))
3487 disable_mclk_switching = true;
3488
3489 if (rps->vclk || rps->dclk) {
3490 disable_mclk_switching = true;
3491 disable_sclk_switching = true;
3492 }
3493
3494 if (adev->pm.dpm.ac_power)
3495 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
3496 else
3497 max_limits = &adev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
3498
3499 for (i = ps->performance_level_count - 2; i >= 0; i--) {
3500 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
3501 ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
3502 }
3503 if (adev->pm.dpm.ac_power == false) {
3504 for (i = 0; i < ps->performance_level_count; i++) {
3505 if (ps->performance_levels[i].mclk > max_limits->mclk)
3506 ps->performance_levels[i].mclk = max_limits->mclk;
3507 if (ps->performance_levels[i].sclk > max_limits->sclk)
3508 ps->performance_levels[i].sclk = max_limits->sclk;
3509 if (ps->performance_levels[i].vddc > max_limits->vddc)
3510 ps->performance_levels[i].vddc = max_limits->vddc;
3511 if (ps->performance_levels[i].vddci > max_limits->vddci)
3512 ps->performance_levels[i].vddci = max_limits->vddci;
3513 }
3514 }
3515
3516 /* limit clocks to max supported clocks based on voltage dependency tables */
3517 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3518 &max_sclk_vddc);
3519 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3520 &max_mclk_vddci);
3521 btc_get_max_clock_from_voltage_dependency_table(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3522 &max_mclk_vddc);
3523
3524 for (i = 0; i < ps->performance_level_count; i++) {
3525 if (max_sclk_vddc) {
3526 if (ps->performance_levels[i].sclk > max_sclk_vddc)
3527 ps->performance_levels[i].sclk = max_sclk_vddc;
3528 }
3529 if (max_mclk_vddci) {
3530 if (ps->performance_levels[i].mclk > max_mclk_vddci)
3531 ps->performance_levels[i].mclk = max_mclk_vddci;
3532 }
3533 if (max_mclk_vddc) {
3534 if (ps->performance_levels[i].mclk > max_mclk_vddc)
3535 ps->performance_levels[i].mclk = max_mclk_vddc;
3536 }
3537 if (max_mclk) {
3538 if (ps->performance_levels[i].mclk > max_mclk)
3539 ps->performance_levels[i].mclk = max_mclk;
3540 }
3541 if (max_sclk) {
3542 if (ps->performance_levels[i].sclk > max_sclk)
3543 ps->performance_levels[i].sclk = max_sclk;
3544 }
3545 }
3546
3547 /* XXX validate the min clocks required for display */
3548
3549 if (disable_mclk_switching) {
3550 mclk = ps->performance_levels[ps->performance_level_count - 1].mclk;
3551 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
3552 } else {
3553 mclk = ps->performance_levels[0].mclk;
3554 vddci = ps->performance_levels[0].vddci;
3555 }
3556
3557 if (disable_sclk_switching) {
3558 sclk = ps->performance_levels[ps->performance_level_count - 1].sclk;
3559 vddc = ps->performance_levels[ps->performance_level_count - 1].vddc;
3560 } else {
3561 sclk = ps->performance_levels[0].sclk;
3562 vddc = ps->performance_levels[0].vddc;
3563 }
3564
3565 if (rps->vce_active) {
3566 if (sclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk)
3567 sclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].sclk;
3568 if (mclk < adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk)
3569 mclk = adev->pm.dpm.vce_states[adev->pm.dpm.vce_level].mclk;
3570 }
3571
3572 /* adjusted low state */
3573 ps->performance_levels[0].sclk = sclk;
3574 ps->performance_levels[0].mclk = mclk;
3575 ps->performance_levels[0].vddc = vddc;
3576 ps->performance_levels[0].vddci = vddci;
3577
3578 if (disable_sclk_switching) {
3579 sclk = ps->performance_levels[0].sclk;
3580 for (i = 1; i < ps->performance_level_count; i++) {
3581 if (sclk < ps->performance_levels[i].sclk)
3582 sclk = ps->performance_levels[i].sclk;
3583 }
3584 for (i = 0; i < ps->performance_level_count; i++) {
3585 ps->performance_levels[i].sclk = sclk;
3586 ps->performance_levels[i].vddc = vddc;
3587 }
3588 } else {
3589 for (i = 1; i < ps->performance_level_count; i++) {
3590 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
3591 ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
3592 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
3593 ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
3594 }
3595 }
3596
3597 if (disable_mclk_switching) {
3598 mclk = ps->performance_levels[0].mclk;
3599 for (i = 1; i < ps->performance_level_count; i++) {
3600 if (mclk < ps->performance_levels[i].mclk)
3601 mclk = ps->performance_levels[i].mclk;
3602 }
3603 for (i = 0; i < ps->performance_level_count; i++) {
3604 ps->performance_levels[i].mclk = mclk;
3605 ps->performance_levels[i].vddci = vddci;
3606 }
3607 } else {
3608 for (i = 1; i < ps->performance_level_count; i++) {
3609 if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
3610 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
3611 if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
3612 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
3613 }
3614 }
3615
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3616 for (i = 0; i < ps->performance_level_count; i++)
3617 btc_adjust_clock_combinations(adev, max_limits,
3618 &ps->performance_levels[i]);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3619
3620 for (i = 0; i < ps->performance_level_count; i++) {
3621 if (ps->performance_levels[i].vddc < min_vce_voltage)
3622 ps->performance_levels[i].vddc = min_vce_voltage;
3623 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
3624 ps->performance_levels[i].sclk,
3625 max_limits->vddc, &ps->performance_levels[i].vddc);
3626 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
3627 ps->performance_levels[i].mclk,
3628 max_limits->vddci, &ps->performance_levels[i].vddci);
3629 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
3630 ps->performance_levels[i].mclk,
3631 max_limits->vddc, &ps->performance_levels[i].vddc);
3632 btc_apply_voltage_dependency_rules(&adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
3633 adev->clock.current_dispclk,
3634 max_limits->vddc, &ps->performance_levels[i].vddc);
3635 }
3636
3637 for (i = 0; i < ps->performance_level_count; i++) {
3638 btc_apply_voltage_delta_rules(adev,
3639 max_limits->vddc, max_limits->vddci,
3640 &ps->performance_levels[i].vddc,
3641 &ps->performance_levels[i].vddci);
3642 }
3643
3644 ps->dc_compatible = true;
3645 for (i = 0; i < ps->performance_level_count; i++) {
3646 if (ps->performance_levels[i].vddc > adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3647 ps->dc_compatible = false;
3648 }
3649}
3650
3651#if 0
3652static int si_read_smc_soft_register(struct amdgpu_device *adev,
3653 u16 reg_offset, u32 *value)
3654{
3655 struct si_power_info *si_pi = si_get_pi(adev);
3656
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3657 return amdgpu_si_read_smc_sram_dword(adev,
3658 si_pi->soft_regs_start + reg_offset, value,
3659 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3660}
3661#endif
3662
3663static int si_write_smc_soft_register(struct amdgpu_device *adev,
3664 u16 reg_offset, u32 value)
3665{
3666 struct si_power_info *si_pi = si_get_pi(adev);
3667
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3668 return amdgpu_si_write_smc_sram_dword(adev,
3669 si_pi->soft_regs_start + reg_offset,
3670 value, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3671}
3672
3673static bool si_is_special_1gb_platform(struct amdgpu_device *adev)
3674{
3675 bool ret = false;
3676 u32 tmp, width, row, column, bank, density;
3677 bool is_memory_gddr5, is_special;
3678
3679 tmp = RREG32(MC_SEQ_MISC0);
3680 is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3681 is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3682 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3683
3684 WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3685 width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3686
3687 tmp = RREG32(MC_ARB_RAMCFG);
3688 row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3689 column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3690 bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3691
3692 density = (1 << (row + column - 20 + bank)) * width;
3693
3694 if ((adev->pdev->device == 0x6819) &&
3695 is_memory_gddr5 && is_special && (density == 0x400))
3696 ret = true;
3697
3698 return ret;
3699}
3700
3701static void si_get_leakage_vddc(struct amdgpu_device *adev)
3702{
3703 struct si_power_info *si_pi = si_get_pi(adev);
3704 u16 vddc, count = 0;
3705 int i, ret;
3706
3707 for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3708 ret = amdgpu_atombios_get_leakage_vddc_based_on_leakage_idx(adev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3709
3710 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3711 si_pi->leakage_voltage.entries[count].voltage = vddc;
3712 si_pi->leakage_voltage.entries[count].leakage_index =
3713 SISLANDS_LEAKAGE_INDEX0 + i;
3714 count++;
3715 }
3716 }
3717 si_pi->leakage_voltage.count = count;
3718}
3719
3720static int si_get_leakage_voltage_from_leakage_index(struct amdgpu_device *adev,
3721 u32 index, u16 *leakage_voltage)
3722{
3723 struct si_power_info *si_pi = si_get_pi(adev);
3724 int i;
3725
3726 if (leakage_voltage == NULL)
3727 return -EINVAL;
3728
3729 if ((index & 0xff00) != 0xff00)
3730 return -EINVAL;
3731
3732 if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3733 return -EINVAL;
3734
3735 if (index < SISLANDS_LEAKAGE_INDEX0)
3736 return -EINVAL;
3737
3738 for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3739 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3740 *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3741 return 0;
3742 }
3743 }
3744 return -EAGAIN;
3745}
3746
3747static void si_set_dpm_event_sources(struct amdgpu_device *adev, u32 sources)
3748{
3749 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3750 bool want_thermal_protection;
3751 enum amdgpu_dpm_event_src dpm_event_src;
3752
3753 switch (sources) {
3754 case 0:
3755 default:
3756 want_thermal_protection = false;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3757 break;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3758 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL):
3759 want_thermal_protection = true;
3760 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGITAL;
3761 break;
3762 case (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3763 want_thermal_protection = true;
3764 dpm_event_src = AMDGPU_DPM_EVENT_SRC_EXTERNAL;
3765 break;
3766 case ((1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3767 (1 << AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3768 want_thermal_protection = true;
3769 dpm_event_src = AMDGPU_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3770 break;
3771 }
3772
3773 if (want_thermal_protection) {
3774 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3775 if (pi->thermal_protection)
3776 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3777 } else {
3778 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3779 }
3780}
3781
3782static void si_enable_auto_throttle_source(struct amdgpu_device *adev,
3783 enum amdgpu_dpm_auto_throttle_src source,
3784 bool enable)
3785{
3786 struct rv7xx_power_info *pi = rv770_get_pi(adev);
3787
3788 if (enable) {
3789 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3790 pi->active_auto_throttle_sources |= 1 << source;
3791 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3792 }
3793 } else {
3794 if (pi->active_auto_throttle_sources & (1 << source)) {
3795 pi->active_auto_throttle_sources &= ~(1 << source);
3796 si_set_dpm_event_sources(adev, pi->active_auto_throttle_sources);
3797 }
3798 }
3799}
3800
3801static void si_start_dpm(struct amdgpu_device *adev)
3802{
3803 WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3804}
3805
3806static void si_stop_dpm(struct amdgpu_device *adev)
3807{
3808 WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3809}
3810
3811static void si_enable_sclk_control(struct amdgpu_device *adev, bool enable)
3812{
3813 if (enable)
3814 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3815 else
3816 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3817
3818}
3819
3820#if 0
3821static int si_notify_hardware_of_thermal_state(struct amdgpu_device *adev,
3822 u32 thermal_level)
3823{
3824 PPSMC_Result ret;
3825
3826 if (thermal_level == 0) {
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3827 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3828 if (ret == PPSMC_Result_OK)
3829 return 0;
3830 else
3831 return -EINVAL;
3832 }
3833 return 0;
3834}
3835
3836static void si_notify_hardware_vpu_recovery_event(struct amdgpu_device *adev)
3837{
3838 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3839}
3840#endif
3841
3842#if 0
3843static int si_notify_hw_of_powersource(struct amdgpu_device *adev, bool ac_power)
3844{
3845 if (ac_power)
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3846 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3847 0 : -EINVAL;
3848
3849 return 0;
3850}
3851#endif
3852
3853static PPSMC_Result si_send_msg_to_smc_with_parameter(struct amdgpu_device *adev,
3854 PPSMC_Msg msg, u32 parameter)
3855{
3856 WREG32(SMC_SCRATCH0, parameter);
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3857 return amdgpu_si_send_msg_to_smc(adev, msg);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3858}
3859
3860static int si_restrict_performance_levels_before_switch(struct amdgpu_device *adev)
3861{
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3862 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3863 return -EINVAL;
3864
3865 return (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3866 0 : -EINVAL;
3867}
3868
3869static int si_dpm_force_performance_level(struct amdgpu_device *adev,
Rex Zhue5d03ac2016-12-23 14:39:41 +0800[diff] [blame]3870 enum amd_dpm_forced_level level)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3871{
3872 struct amdgpu_ps *rps = adev->pm.dpm.current_ps;
3873 struct si_ps *ps = si_get_ps(rps);
3874 u32 levels = ps->performance_level_count;
3875
Rex Zhue5d03ac2016-12-23 14:39:41 +0800[diff] [blame]3876 if (level == AMD_DPM_FORCED_LEVEL_HIGH) {
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3877 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3878 return -EINVAL;
3879
3880 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3881 return -EINVAL;
Rex Zhue5d03ac2016-12-23 14:39:41 +0800[diff] [blame]3882 } else if (level == AMD_DPM_FORCED_LEVEL_LOW) {
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3883 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3884 return -EINVAL;
3885
3886 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, 1) != PPSMC_Result_OK)
3887 return -EINVAL;
Rex Zhue5d03ac2016-12-23 14:39:41 +0800[diff] [blame]3888 } else if (level == AMD_DPM_FORCED_LEVEL_AUTO) {
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3889 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3890 return -EINVAL;
3891
3892 if (si_send_msg_to_smc_with_parameter(adev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3893 return -EINVAL;
3894 }
3895
3896 adev->pm.dpm.forced_level = level;
3897
3898 return 0;
3899}
3900
3901#if 0
3902static int si_set_boot_state(struct amdgpu_device *adev)
3903{
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3904 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3905 0 : -EINVAL;
3906}
3907#endif
3908
3909static int si_set_sw_state(struct amdgpu_device *adev)
3910{
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3911 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3912 0 : -EINVAL;
3913}
3914
3915static int si_halt_smc(struct amdgpu_device *adev)
3916{
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3917 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3918 return -EINVAL;
3919
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3920 return (amdgpu_si_wait_for_smc_inactive(adev) == PPSMC_Result_OK) ?
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3921 0 : -EINVAL;
3922}
3923
3924static int si_resume_smc(struct amdgpu_device *adev)
3925{
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3926 if (amdgpu_si_send_msg_to_smc(adev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3927 return -EINVAL;
3928
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3929 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3930 0 : -EINVAL;
3931}
3932
3933static void si_dpm_start_smc(struct amdgpu_device *adev)
3934{
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3935 amdgpu_si_program_jump_on_start(adev);
3936 amdgpu_si_start_smc(adev);
3937 amdgpu_si_smc_clock(adev, true);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3938}
3939
3940static void si_dpm_stop_smc(struct amdgpu_device *adev)
3941{
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3942 amdgpu_si_reset_smc(adev);
3943 amdgpu_si_smc_clock(adev, false);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3944}
3945
3946static int si_process_firmware_header(struct amdgpu_device *adev)
3947{
3948 struct si_power_info *si_pi = si_get_pi(adev);
3949 u32 tmp;
3950 int ret;
3951
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3952 ret = amdgpu_si_read_smc_sram_dword(adev,
3953 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3954 SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3955 &tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3956 if (ret)
3957 return ret;
3958
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]3959 si_pi->state_table_start = tmp;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3960
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3961 ret = amdgpu_si_read_smc_sram_dword(adev,
3962 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3963 SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3964 &tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3965 if (ret)
3966 return ret;
3967
3968 si_pi->soft_regs_start = tmp;
3969
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3970 ret = amdgpu_si_read_smc_sram_dword(adev,
3971 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3972 SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3973 &tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3974 if (ret)
3975 return ret;
3976
3977 si_pi->mc_reg_table_start = tmp;
3978
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3979 ret = amdgpu_si_read_smc_sram_dword(adev,
3980 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3981 SISLANDS_SMC_FIRMWARE_HEADER_fanTable,
3982 &tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3983 if (ret)
3984 return ret;
3985
3986 si_pi->fan_table_start = tmp;
3987
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3988 ret = amdgpu_si_read_smc_sram_dword(adev,
3989 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3990 SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3991 &tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]3992 if (ret)
3993 return ret;
3994
3995 si_pi->arb_table_start = tmp;
3996
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]3997 ret = amdgpu_si_read_smc_sram_dword(adev,
3998 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3999 SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
4000 &tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4001 if (ret)
4002 return ret;
4003
4004 si_pi->cac_table_start = tmp;
4005
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]4006 ret = amdgpu_si_read_smc_sram_dword(adev,
4007 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4008 SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
4009 &tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4010 if (ret)
4011 return ret;
4012
4013 si_pi->dte_table_start = tmp;
4014
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]4015 ret = amdgpu_si_read_smc_sram_dword(adev,
4016 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4017 SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
4018 &tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4019 if (ret)
4020 return ret;
4021
4022 si_pi->spll_table_start = tmp;
4023
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]4024 ret = amdgpu_si_read_smc_sram_dword(adev,
4025 SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
4026 SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
4027 &tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4028 if (ret)
4029 return ret;
4030
4031 si_pi->papm_cfg_table_start = tmp;
4032
4033 return ret;
4034}
4035
4036static void si_read_clock_registers(struct amdgpu_device *adev)
4037{
4038 struct si_power_info *si_pi = si_get_pi(adev);
4039
4040 si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
4041 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
4042 si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
4043 si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
4044 si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
4045 si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
4046 si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
4047 si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
4048 si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
4049 si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
4050 si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
4051 si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
4052 si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
4053 si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
4054 si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
4055}
4056
4057static void si_enable_thermal_protection(struct amdgpu_device *adev,
4058 bool enable)
4059{
4060 if (enable)
4061 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
4062 else
4063 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
4064}
4065
4066static void si_enable_acpi_power_management(struct amdgpu_device *adev)
4067{
4068 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
4069}
4070
4071#if 0
4072static int si_enter_ulp_state(struct amdgpu_device *adev)
4073{
4074 WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
4075
4076 udelay(25000);
4077
4078 return 0;
4079}
4080
4081static int si_exit_ulp_state(struct amdgpu_device *adev)
4082{
4083 int i;
4084
4085 WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
4086
4087 udelay(7000);
4088
4089 for (i = 0; i < adev->usec_timeout; i++) {
4090 if (RREG32(SMC_RESP_0) == 1)
4091 break;
4092 udelay(1000);
4093 }
4094
4095 return 0;
4096}
4097#endif
4098
4099static int si_notify_smc_display_change(struct amdgpu_device *adev,
4100 bool has_display)
4101{
4102 PPSMC_Msg msg = has_display ?
4103 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
4104
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]4105 return (amdgpu_si_send_msg_to_smc(adev, msg) == PPSMC_Result_OK) ?
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4106 0 : -EINVAL;
4107}
4108
4109static void si_program_response_times(struct amdgpu_device *adev)
4110{
4111 u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
4112 u32 vddc_dly, acpi_dly, vbi_dly;
4113 u32 reference_clock;
4114
4115 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
4116
4117 voltage_response_time = (u32)adev->pm.dpm.voltage_response_time;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]4118 backbias_response_time = (u32)adev->pm.dpm.backbias_response_time;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4119
4120 if (voltage_response_time == 0)
4121 voltage_response_time = 1000;
4122
4123 acpi_delay_time = 15000;
4124 vbi_time_out = 100000;
4125
4126 reference_clock = amdgpu_asic_get_xclk(adev);
4127
4128 vddc_dly = (voltage_response_time * reference_clock) / 100;
4129 acpi_dly = (acpi_delay_time * reference_clock) / 100;
4130 vbi_dly = (vbi_time_out * reference_clock) / 100;
4131
4132 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_vreg, vddc_dly);
4133 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_delay_acpi, acpi_dly);
4134 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
4135 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
4136}
4137
4138static void si_program_ds_registers(struct amdgpu_device *adev)
4139{
4140 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4141 u32 tmp;
4142
4143 /* DEEP_SLEEP_CLK_SEL field should be 0x10 on tahiti A0 */
4144 if (adev->asic_type == CHIP_TAHITI && adev->rev_id == 0x0)
4145 tmp = 0x10;
4146 else
4147 tmp = 0x1;
4148
4149 if (eg_pi->sclk_deep_sleep) {
4150 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
4151 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
4152 ~AUTOSCALE_ON_SS_CLEAR);
4153 }
4154}
4155
4156static void si_program_display_gap(struct amdgpu_device *adev)
4157{
4158 u32 tmp, pipe;
4159 int i;
4160
4161 tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4162 if (adev->pm.dpm.new_active_crtc_count > 0)
4163 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4164 else
4165 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4166
4167 if (adev->pm.dpm.new_active_crtc_count > 1)
4168 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
4169 else
4170 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
4171
4172 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4173
4174 tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
4175 pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
4176
4177 if ((adev->pm.dpm.new_active_crtc_count > 0) &&
4178 (!(adev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
4179 /* find the first active crtc */
4180 for (i = 0; i < adev->mode_info.num_crtc; i++) {
4181 if (adev->pm.dpm.new_active_crtcs & (1 << i))
4182 break;
4183 }
4184 if (i == adev->mode_info.num_crtc)
4185 pipe = 0;
4186 else
4187 pipe = i;
4188
4189 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
4190 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
4191 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
4192 }
4193
4194 /* Setting this to false forces the performance state to low if the crtcs are disabled.
4195 * This can be a problem on PowerXpress systems or if you want to use the card
4196 * for offscreen rendering or compute if there are no crtcs enabled.
4197 */
4198 si_notify_smc_display_change(adev, adev->pm.dpm.new_active_crtc_count > 0);
4199}
4200
4201static void si_enable_spread_spectrum(struct amdgpu_device *adev, bool enable)
4202{
4203 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4204
4205 if (enable) {
4206 if (pi->sclk_ss)
4207 WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
4208 } else {
4209 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
4210 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
4211 }
4212}
4213
4214static void si_setup_bsp(struct amdgpu_device *adev)
4215{
4216 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4217 u32 xclk = amdgpu_asic_get_xclk(adev);
4218
4219 r600_calculate_u_and_p(pi->asi,
4220 xclk,
4221 16,
4222 &pi->bsp,
4223 &pi->bsu);
4224
4225 r600_calculate_u_and_p(pi->pasi,
4226 xclk,
4227 16,
4228 &pi->pbsp,
4229 &pi->pbsu);
4230
4231
4232 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
4233 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
4234
4235 WREG32(CG_BSP, pi->dsp);
4236}
4237
4238static void si_program_git(struct amdgpu_device *adev)
4239{
4240 WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
4241}
4242
4243static void si_program_tp(struct amdgpu_device *adev)
4244{
4245 int i;
4246 enum r600_td td = R600_TD_DFLT;
4247
4248 for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
4249 WREG32(CG_FFCT_0 + i, (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
4250
4251 if (td == R600_TD_AUTO)
4252 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
4253 else
4254 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
4255
4256 if (td == R600_TD_UP)
4257 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
4258
4259 if (td == R600_TD_DOWN)
4260 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
4261}
4262
4263static void si_program_tpp(struct amdgpu_device *adev)
4264{
4265 WREG32(CG_TPC, R600_TPC_DFLT);
4266}
4267
4268static void si_program_sstp(struct amdgpu_device *adev)
4269{
4270 WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
4271}
4272
4273static void si_enable_display_gap(struct amdgpu_device *adev)
4274{
4275 u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
4276
4277 tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
4278 tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
4279 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
4280
4281 tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
4282 tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
4283 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
4284 WREG32(CG_DISPLAY_GAP_CNTL, tmp);
4285}
4286
4287static void si_program_vc(struct amdgpu_device *adev)
4288{
4289 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4290
4291 WREG32(CG_FTV, pi->vrc);
4292}
4293
4294static void si_clear_vc(struct amdgpu_device *adev)
4295{
4296 WREG32(CG_FTV, 0);
4297}
4298
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]4299static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4300{
4301 u8 mc_para_index;
4302
4303 if (memory_clock < 10000)
4304 mc_para_index = 0;
4305 else if (memory_clock >= 80000)
4306 mc_para_index = 0x0f;
4307 else
4308 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
4309 return mc_para_index;
4310}
4311
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]4312static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4313{
4314 u8 mc_para_index;
4315
4316 if (strobe_mode) {
4317 if (memory_clock < 12500)
4318 mc_para_index = 0x00;
4319 else if (memory_clock > 47500)
4320 mc_para_index = 0x0f;
4321 else
4322 mc_para_index = (u8)((memory_clock - 10000) / 2500);
4323 } else {
4324 if (memory_clock < 65000)
4325 mc_para_index = 0x00;
4326 else if (memory_clock > 135000)
4327 mc_para_index = 0x0f;
4328 else
4329 mc_para_index = (u8)((memory_clock - 60000) / 5000);
4330 }
4331 return mc_para_index;
4332}
4333
4334static u8 si_get_strobe_mode_settings(struct amdgpu_device *adev, u32 mclk)
4335{
4336 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4337 bool strobe_mode = false;
4338 u8 result = 0;
4339
4340 if (mclk <= pi->mclk_strobe_mode_threshold)
4341 strobe_mode = true;
4342
4343 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
4344 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
4345 else
4346 result = si_get_ddr3_mclk_frequency_ratio(mclk);
4347
4348 if (strobe_mode)
4349 result |= SISLANDS_SMC_STROBE_ENABLE;
4350
4351 return result;
4352}
4353
4354static int si_upload_firmware(struct amdgpu_device *adev)
4355{
4356 struct si_power_info *si_pi = si_get_pi(adev);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4357
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]4358 amdgpu_si_reset_smc(adev);
4359 amdgpu_si_smc_clock(adev, false);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4360
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]4361 return amdgpu_si_load_smc_ucode(adev, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4362}
4363
4364static bool si_validate_phase_shedding_tables(struct amdgpu_device *adev,
4365 const struct atom_voltage_table *table,
4366 const struct amdgpu_phase_shedding_limits_table *limits)
4367{
4368 u32 data, num_bits, num_levels;
4369
4370 if ((table == NULL) || (limits == NULL))
4371 return false;
4372
4373 data = table->mask_low;
4374
4375 num_bits = hweight32(data);
4376
4377 if (num_bits == 0)
4378 return false;
4379
4380 num_levels = (1 << num_bits);
4381
4382 if (table->count != num_levels)
4383 return false;
4384
4385 if (limits->count != (num_levels - 1))
4386 return false;
4387
4388 return true;
4389}
4390
4391static void si_trim_voltage_table_to_fit_state_table(struct amdgpu_device *adev,
4392 u32 max_voltage_steps,
4393 struct atom_voltage_table *voltage_table)
4394{
4395 unsigned int i, diff;
4396
4397 if (voltage_table->count <= max_voltage_steps)
4398 return;
4399
4400 diff = voltage_table->count - max_voltage_steps;
4401
4402 for (i= 0; i < max_voltage_steps; i++)
4403 voltage_table->entries[i] = voltage_table->entries[i + diff];
4404
4405 voltage_table->count = max_voltage_steps;
4406}
4407
4408static int si_get_svi2_voltage_table(struct amdgpu_device *adev,
4409 struct amdgpu_clock_voltage_dependency_table *voltage_dependency_table,
4410 struct atom_voltage_table *voltage_table)
4411{
4412 u32 i;
4413
4414 if (voltage_dependency_table == NULL)
4415 return -EINVAL;
4416
4417 voltage_table->mask_low = 0;
4418 voltage_table->phase_delay = 0;
4419
4420 voltage_table->count = voltage_dependency_table->count;
4421 for (i = 0; i < voltage_table->count; i++) {
4422 voltage_table->entries[i].value = voltage_dependency_table->entries[i].v;
4423 voltage_table->entries[i].smio_low = 0;
4424 }
4425
4426 return 0;
4427}
4428
4429static int si_construct_voltage_tables(struct amdgpu_device *adev)
4430{
4431 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4432 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4433 struct si_power_info *si_pi = si_get_pi(adev);
4434 int ret;
4435
4436 if (pi->voltage_control) {
4437 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4438 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
4439 if (ret)
4440 return ret;
4441
4442 if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4443 si_trim_voltage_table_to_fit_state_table(adev,
4444 SISLANDS_MAX_NO_VREG_STEPS,
4445 &eg_pi->vddc_voltage_table);
4446 } else if (si_pi->voltage_control_svi2) {
4447 ret = si_get_svi2_voltage_table(adev,
4448 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
4449 &eg_pi->vddc_voltage_table);
4450 if (ret)
4451 return ret;
4452 } else {
4453 return -EINVAL;
4454 }
4455
4456 if (eg_pi->vddci_control) {
4457 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDCI,
4458 VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
4459 if (ret)
4460 return ret;
4461
4462 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4463 si_trim_voltage_table_to_fit_state_table(adev,
4464 SISLANDS_MAX_NO_VREG_STEPS,
4465 &eg_pi->vddci_voltage_table);
4466 }
4467 if (si_pi->vddci_control_svi2) {
4468 ret = si_get_svi2_voltage_table(adev,
4469 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
4470 &eg_pi->vddci_voltage_table);
4471 if (ret)
4472 return ret;
4473 }
4474
4475 if (pi->mvdd_control) {
4476 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_MVDDC,
4477 VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
4478
4479 if (ret) {
4480 pi->mvdd_control = false;
4481 return ret;
4482 }
4483
4484 if (si_pi->mvdd_voltage_table.count == 0) {
4485 pi->mvdd_control = false;
4486 return -EINVAL;
4487 }
4488
4489 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
4490 si_trim_voltage_table_to_fit_state_table(adev,
4491 SISLANDS_MAX_NO_VREG_STEPS,
4492 &si_pi->mvdd_voltage_table);
4493 }
4494
4495 if (si_pi->vddc_phase_shed_control) {
4496 ret = amdgpu_atombios_get_voltage_table(adev, VOLTAGE_TYPE_VDDC,
4497 VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
4498 if (ret)
4499 si_pi->vddc_phase_shed_control = false;
4500
4501 if ((si_pi->vddc_phase_shed_table.count == 0) ||
4502 (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
4503 si_pi->vddc_phase_shed_control = false;
4504 }
4505
4506 return 0;
4507}
4508
4509static void si_populate_smc_voltage_table(struct amdgpu_device *adev,
4510 const struct atom_voltage_table *voltage_table,
4511 SISLANDS_SMC_STATETABLE *table)
4512{
4513 unsigned int i;
4514
4515 for (i = 0; i < voltage_table->count; i++)
4516 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
4517}
4518
4519static int si_populate_smc_voltage_tables(struct amdgpu_device *adev,
4520 SISLANDS_SMC_STATETABLE *table)
4521{
4522 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4523 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4524 struct si_power_info *si_pi = si_get_pi(adev);
4525 u8 i;
4526
4527 if (si_pi->voltage_control_svi2) {
4528 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svc,
4529 si_pi->svc_gpio_id);
4530 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_gpio_id_svd,
4531 si_pi->svd_gpio_id);
4532 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_svi_rework_plat_type,
4533 2);
4534 } else {
4535 if (eg_pi->vddc_voltage_table.count) {
4536 si_populate_smc_voltage_table(adev, &eg_pi->vddc_voltage_table, table);
4537 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
4538 cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
4539
4540 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
4541 if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
4542 table->maxVDDCIndexInPPTable = i;
4543 break;
4544 }
4545 }
4546 }
4547
4548 if (eg_pi->vddci_voltage_table.count) {
4549 si_populate_smc_voltage_table(adev, &eg_pi->vddci_voltage_table, table);
4550
4551 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
4552 cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
4553 }
4554
4555
4556 if (si_pi->mvdd_voltage_table.count) {
4557 si_populate_smc_voltage_table(adev, &si_pi->mvdd_voltage_table, table);
4558
4559 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
4560 cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
4561 }
4562
4563 if (si_pi->vddc_phase_shed_control) {
4564 if (si_validate_phase_shedding_tables(adev, &si_pi->vddc_phase_shed_table,
4565 &adev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
4566 si_populate_smc_voltage_table(adev, &si_pi->vddc_phase_shed_table, table);
4567
Alex Deucherbdbdb572016-09-27 14:57:35 -0400[diff] [blame]4568 table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC_PHASE_SHEDDING] =
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4569 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
4570
4571 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
4572 (u32)si_pi->vddc_phase_shed_table.phase_delay);
4573 } else {
4574 si_pi->vddc_phase_shed_control = false;
4575 }
4576 }
4577 }
4578
4579 return 0;
4580}
4581
4582static int si_populate_voltage_value(struct amdgpu_device *adev,
4583 const struct atom_voltage_table *table,
4584 u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4585{
4586 unsigned int i;
4587
4588 for (i = 0; i < table->count; i++) {
4589 if (value <= table->entries[i].value) {
4590 voltage->index = (u8)i;
4591 voltage->value = cpu_to_be16(table->entries[i].value);
4592 break;
4593 }
4594 }
4595
4596 if (i >= table->count)
4597 return -EINVAL;
4598
4599 return 0;
4600}
4601
4602static int si_populate_mvdd_value(struct amdgpu_device *adev, u32 mclk,
4603 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4604{
4605 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4606 struct si_power_info *si_pi = si_get_pi(adev);
4607
4608 if (pi->mvdd_control) {
4609 if (mclk <= pi->mvdd_split_frequency)
4610 voltage->index = 0;
4611 else
4612 voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
4613
4614 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
4615 }
4616 return 0;
4617}
4618
4619static int si_get_std_voltage_value(struct amdgpu_device *adev,
4620 SISLANDS_SMC_VOLTAGE_VALUE *voltage,
4621 u16 *std_voltage)
4622{
4623 u16 v_index;
4624 bool voltage_found = false;
4625 *std_voltage = be16_to_cpu(voltage->value);
4626
4627 if (adev->pm.dpm.dyn_state.cac_leakage_table.entries) {
4628 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
4629 if (adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
4630 return -EINVAL;
4631
4632 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4633 if (be16_to_cpu(voltage->value) ==
4634 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4635 voltage_found = true;
4636 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4637 *std_voltage =
4638 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4639 else
4640 *std_voltage =
4641 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4642 break;
4643 }
4644 }
4645
4646 if (!voltage_found) {
4647 for (v_index = 0; (u32)v_index < adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
4648 if (be16_to_cpu(voltage->value) <=
4649 (u16)adev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
4650 voltage_found = true;
4651 if ((u32)v_index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4652 *std_voltage =
4653 adev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
4654 else
4655 *std_voltage =
4656 adev->pm.dpm.dyn_state.cac_leakage_table.entries[adev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
4657 break;
4658 }
4659 }
4660 }
4661 } else {
4662 if ((u32)voltage->index < adev->pm.dpm.dyn_state.cac_leakage_table.count)
4663 *std_voltage = adev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
4664 }
4665 }
4666
4667 return 0;
4668}
4669
4670static int si_populate_std_voltage_value(struct amdgpu_device *adev,
4671 u16 value, u8 index,
4672 SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4673{
4674 voltage->index = index;
4675 voltage->value = cpu_to_be16(value);
4676
4677 return 0;
4678}
4679
4680static int si_populate_phase_shedding_value(struct amdgpu_device *adev,
4681 const struct amdgpu_phase_shedding_limits_table *limits,
4682 u16 voltage, u32 sclk, u32 mclk,
4683 SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
4684{
4685 unsigned int i;
4686
4687 for (i = 0; i < limits->count; i++) {
4688 if ((voltage <= limits->entries[i].voltage) &&
4689 (sclk <= limits->entries[i].sclk) &&
4690 (mclk <= limits->entries[i].mclk))
4691 break;
4692 }
4693
4694 smc_voltage->phase_settings = (u8)i;
4695
4696 return 0;
4697}
4698
4699static int si_init_arb_table_index(struct amdgpu_device *adev)
4700{
4701 struct si_power_info *si_pi = si_get_pi(adev);
4702 u32 tmp;
4703 int ret;
4704
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]4705 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4706 &tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4707 if (ret)
4708 return ret;
4709
4710 tmp &= 0x00FFFFFF;
4711 tmp |= MC_CG_ARB_FREQ_F1 << 24;
4712
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]4713 return amdgpu_si_write_smc_sram_dword(adev, si_pi->arb_table_start,
4714 tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4715}
4716
4717static int si_initial_switch_from_arb_f0_to_f1(struct amdgpu_device *adev)
4718{
4719 return ni_copy_and_switch_arb_sets(adev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4720}
4721
4722static int si_reset_to_default(struct amdgpu_device *adev)
4723{
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]4724 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4725 0 : -EINVAL;
4726}
4727
4728static int si_force_switch_to_arb_f0(struct amdgpu_device *adev)
4729{
4730 struct si_power_info *si_pi = si_get_pi(adev);
4731 u32 tmp;
4732 int ret;
4733
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]4734 ret = amdgpu_si_read_smc_sram_dword(adev, si_pi->arb_table_start,
4735 &tmp, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4736 if (ret)
4737 return ret;
4738
4739 tmp = (tmp >> 24) & 0xff;
4740
4741 if (tmp == MC_CG_ARB_FREQ_F0)
4742 return 0;
4743
4744 return ni_copy_and_switch_arb_sets(adev, tmp, MC_CG_ARB_FREQ_F0);
4745}
4746
4747static u32 si_calculate_memory_refresh_rate(struct amdgpu_device *adev,
4748 u32 engine_clock)
4749{
4750 u32 dram_rows;
4751 u32 dram_refresh_rate;
4752 u32 mc_arb_rfsh_rate;
4753 u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4754
4755 if (tmp >= 4)
4756 dram_rows = 16384;
4757 else
4758 dram_rows = 1 << (tmp + 10);
4759
4760 dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4761 mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4762
4763 return mc_arb_rfsh_rate;
4764}
4765
4766static int si_populate_memory_timing_parameters(struct amdgpu_device *adev,
4767 struct rv7xx_pl *pl,
4768 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4769{
4770 u32 dram_timing;
4771 u32 dram_timing2;
4772 u32 burst_time;
4773
4774 arb_regs->mc_arb_rfsh_rate =
4775 (u8)si_calculate_memory_refresh_rate(adev, pl->sclk);
4776
4777 amdgpu_atombios_set_engine_dram_timings(adev,
4778 pl->sclk,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]4779 pl->mclk);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4780
4781 dram_timing = RREG32(MC_ARB_DRAM_TIMING);
4782 dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4783 burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4784
4785 arb_regs->mc_arb_dram_timing = cpu_to_be32(dram_timing);
4786 arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4787 arb_regs->mc_arb_burst_time = (u8)burst_time;
4788
4789 return 0;
4790}
4791
4792static int si_do_program_memory_timing_parameters(struct amdgpu_device *adev,
4793 struct amdgpu_ps *amdgpu_state,
4794 unsigned int first_arb_set)
4795{
4796 struct si_power_info *si_pi = si_get_pi(adev);
4797 struct si_ps *state = si_get_ps(amdgpu_state);
4798 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4799 int i, ret = 0;
4800
4801 for (i = 0; i < state->performance_level_count; i++) {
4802 ret = si_populate_memory_timing_parameters(adev, &state->performance_levels[i], &arb_regs);
4803 if (ret)
4804 break;
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]4805 ret = amdgpu_si_copy_bytes_to_smc(adev,
4806 si_pi->arb_table_start +
4807 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4808 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4809 (u8 *)&arb_regs,
4810 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4811 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4812 if (ret)
4813 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]4814 }
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4815
4816 return ret;
4817}
4818
4819static int si_program_memory_timing_parameters(struct amdgpu_device *adev,
4820 struct amdgpu_ps *amdgpu_new_state)
4821{
4822 return si_do_program_memory_timing_parameters(adev, amdgpu_new_state,
4823 SISLANDS_DRIVER_STATE_ARB_INDEX);
4824}
4825
4826static int si_populate_initial_mvdd_value(struct amdgpu_device *adev,
4827 struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4828{
4829 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4830 struct si_power_info *si_pi = si_get_pi(adev);
4831
4832 if (pi->mvdd_control)
4833 return si_populate_voltage_value(adev, &si_pi->mvdd_voltage_table,
4834 si_pi->mvdd_bootup_value, voltage);
4835
4836 return 0;
4837}
4838
4839static int si_populate_smc_initial_state(struct amdgpu_device *adev,
4840 struct amdgpu_ps *amdgpu_initial_state,
4841 SISLANDS_SMC_STATETABLE *table)
4842{
4843 struct si_ps *initial_state = si_get_ps(amdgpu_initial_state);
4844 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4845 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4846 struct si_power_info *si_pi = si_get_pi(adev);
4847 u32 reg;
4848 int ret;
4849
4850 table->initialState.levels[0].mclk.vDLL_CNTL =
4851 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4852 table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4853 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4854 table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4855 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4856 table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4857 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4858 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4859 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4860 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4861 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4862 table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4863 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4864 table->initialState.levels[0].mclk.vMPLL_SS =
4865 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4866 table->initialState.levels[0].mclk.vMPLL_SS2 =
4867 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4868
4869 table->initialState.levels[0].mclk.mclk_value =
4870 cpu_to_be32(initial_state->performance_levels[0].mclk);
4871
4872 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4873 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4874 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4875 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4876 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4877 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4878 table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4879 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4880 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4881 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4882 table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 =
4883 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4884
4885 table->initialState.levels[0].sclk.sclk_value =
4886 cpu_to_be32(initial_state->performance_levels[0].sclk);
4887
4888 table->initialState.levels[0].arbRefreshState =
4889 SISLANDS_INITIAL_STATE_ARB_INDEX;
4890
4891 table->initialState.levels[0].ACIndex = 0;
4892
4893 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4894 initial_state->performance_levels[0].vddc,
4895 &table->initialState.levels[0].vddc);
4896
4897 if (!ret) {
4898 u16 std_vddc;
4899
4900 ret = si_get_std_voltage_value(adev,
4901 &table->initialState.levels[0].vddc,
4902 &std_vddc);
4903 if (!ret)
4904 si_populate_std_voltage_value(adev, std_vddc,
4905 table->initialState.levels[0].vddc.index,
4906 &table->initialState.levels[0].std_vddc);
4907 }
4908
4909 if (eg_pi->vddci_control)
4910 si_populate_voltage_value(adev,
4911 &eg_pi->vddci_voltage_table,
4912 initial_state->performance_levels[0].vddci,
4913 &table->initialState.levels[0].vddci);
4914
4915 if (si_pi->vddc_phase_shed_control)
4916 si_populate_phase_shedding_value(adev,
4917 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
4918 initial_state->performance_levels[0].vddc,
4919 initial_state->performance_levels[0].sclk,
4920 initial_state->performance_levels[0].mclk,
4921 &table->initialState.levels[0].vddc);
4922
4923 si_populate_initial_mvdd_value(adev, &table->initialState.levels[0].mvdd);
4924
4925 reg = CG_R(0xffff) | CG_L(0);
4926 table->initialState.levels[0].aT = cpu_to_be32(reg);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4927 table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]4928 table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4929
4930 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
4931 table->initialState.levels[0].strobeMode =
4932 si_get_strobe_mode_settings(adev,
4933 initial_state->performance_levels[0].mclk);
4934
4935 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4936 table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4937 else
4938 table->initialState.levels[0].mcFlags = 0;
4939 }
4940
4941 table->initialState.levelCount = 1;
4942
4943 table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4944
4945 table->initialState.levels[0].dpm2.MaxPS = 0;
4946 table->initialState.levels[0].dpm2.NearTDPDec = 0;
4947 table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4948 table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4949 table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4950
4951 reg = MIN_POWER_MASK | MAX_POWER_MASK;
4952 table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4953
4954 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4955 table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4956
4957 return 0;
4958}
4959
4960static int si_populate_smc_acpi_state(struct amdgpu_device *adev,
4961 SISLANDS_SMC_STATETABLE *table)
4962{
4963 struct rv7xx_power_info *pi = rv770_get_pi(adev);
4964 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
4965 struct si_power_info *si_pi = si_get_pi(adev);
4966 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4967 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4968 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4969 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4970 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4971 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4972 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4973 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4974 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4975 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4976 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4977 u32 reg;
4978 int ret;
4979
4980 table->ACPIState = table->initialState;
4981
4982 table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4983
4984 if (pi->acpi_vddc) {
4985 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
4986 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4987 if (!ret) {
4988 u16 std_vddc;
4989
4990 ret = si_get_std_voltage_value(adev,
4991 &table->ACPIState.levels[0].vddc, &std_vddc);
4992 if (!ret)
4993 si_populate_std_voltage_value(adev, std_vddc,
4994 table->ACPIState.levels[0].vddc.index,
4995 &table->ACPIState.levels[0].std_vddc);
4996 }
4997 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4998
4999 if (si_pi->vddc_phase_shed_control) {
5000 si_populate_phase_shedding_value(adev,
5001 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5002 pi->acpi_vddc,
5003 0,
5004 0,
5005 &table->ACPIState.levels[0].vddc);
5006 }
5007 } else {
5008 ret = si_populate_voltage_value(adev, &eg_pi->vddc_voltage_table,
5009 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
5010 if (!ret) {
5011 u16 std_vddc;
5012
5013 ret = si_get_std_voltage_value(adev,
5014 &table->ACPIState.levels[0].vddc, &std_vddc);
5015
5016 if (!ret)
5017 si_populate_std_voltage_value(adev, std_vddc,
5018 table->ACPIState.levels[0].vddc.index,
5019 &table->ACPIState.levels[0].std_vddc);
5020 }
5021 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(adev,
5022 si_pi->sys_pcie_mask,
5023 si_pi->boot_pcie_gen,
5024 AMDGPU_PCIE_GEN1);
5025
5026 if (si_pi->vddc_phase_shed_control)
5027 si_populate_phase_shedding_value(adev,
5028 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5029 pi->min_vddc_in_table,
5030 0,
5031 0,
5032 &table->ACPIState.levels[0].vddc);
5033 }
5034
5035 if (pi->acpi_vddc) {
5036 if (eg_pi->acpi_vddci)
5037 si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5038 eg_pi->acpi_vddci,
5039 &table->ACPIState.levels[0].vddci);
5040 }
5041
5042 mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
5043 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5044
5045 dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
5046
5047 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5048 spll_func_cntl_2 |= SCLK_MUX_SEL(4);
5049
5050 table->ACPIState.levels[0].mclk.vDLL_CNTL =
5051 cpu_to_be32(dll_cntl);
5052 table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
5053 cpu_to_be32(mclk_pwrmgt_cntl);
5054 table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
5055 cpu_to_be32(mpll_ad_func_cntl);
5056 table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
5057 cpu_to_be32(mpll_dq_func_cntl);
5058 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
5059 cpu_to_be32(mpll_func_cntl);
5060 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
5061 cpu_to_be32(mpll_func_cntl_1);
5062 table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
5063 cpu_to_be32(mpll_func_cntl_2);
5064 table->ACPIState.levels[0].mclk.vMPLL_SS =
5065 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
5066 table->ACPIState.levels[0].mclk.vMPLL_SS2 =
5067 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
5068
5069 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
5070 cpu_to_be32(spll_func_cntl);
5071 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
5072 cpu_to_be32(spll_func_cntl_2);
5073 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
5074 cpu_to_be32(spll_func_cntl_3);
5075 table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
5076 cpu_to_be32(spll_func_cntl_4);
5077
5078 table->ACPIState.levels[0].mclk.mclk_value = 0;
5079 table->ACPIState.levels[0].sclk.sclk_value = 0;
5080
5081 si_populate_mvdd_value(adev, 0, &table->ACPIState.levels[0].mvdd);
5082
5083 if (eg_pi->dynamic_ac_timing)
5084 table->ACPIState.levels[0].ACIndex = 0;
5085
5086 table->ACPIState.levels[0].dpm2.MaxPS = 0;
5087 table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
5088 table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
5089 table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
5090 table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
5091
5092 reg = MIN_POWER_MASK | MAX_POWER_MASK;
5093 table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
5094
5095 reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
5096 table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
5097
5098 return 0;
5099}
5100
5101static int si_populate_ulv_state(struct amdgpu_device *adev,
5102 SISLANDS_SMC_SWSTATE *state)
5103{
5104 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5105 struct si_power_info *si_pi = si_get_pi(adev);
5106 struct si_ulv_param *ulv = &si_pi->ulv;
5107 u32 sclk_in_sr = 1350; /* ??? */
5108 int ret;
5109
5110 ret = si_convert_power_level_to_smc(adev, &ulv->pl,
5111 &state->levels[0]);
5112 if (!ret) {
5113 if (eg_pi->sclk_deep_sleep) {
5114 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5115 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5116 else
5117 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5118 }
5119 if (ulv->one_pcie_lane_in_ulv)
5120 state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
5121 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
5122 state->levels[0].ACIndex = 1;
5123 state->levels[0].std_vddc = state->levels[0].vddc;
5124 state->levelCount = 1;
5125
5126 state->flags |= PPSMC_SWSTATE_FLAG_DC;
5127 }
5128
5129 return ret;
5130}
5131
5132static int si_program_ulv_memory_timing_parameters(struct amdgpu_device *adev)
5133{
5134 struct si_power_info *si_pi = si_get_pi(adev);
5135 struct si_ulv_param *ulv = &si_pi->ulv;
5136 SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
5137 int ret;
5138
5139 ret = si_populate_memory_timing_parameters(adev, &ulv->pl,
5140 &arb_regs);
5141 if (ret)
5142 return ret;
5143
5144 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
5145 ulv->volt_change_delay);
5146
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]5147 ret = amdgpu_si_copy_bytes_to_smc(adev,
5148 si_pi->arb_table_start +
5149 offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
5150 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
5151 (u8 *)&arb_regs,
5152 sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
5153 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5154
5155 return ret;
5156}
5157
5158static void si_get_mvdd_configuration(struct amdgpu_device *adev)
5159{
5160 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5161
5162 pi->mvdd_split_frequency = 30000;
5163}
5164
5165static int si_init_smc_table(struct amdgpu_device *adev)
5166{
5167 struct si_power_info *si_pi = si_get_pi(adev);
5168 struct amdgpu_ps *amdgpu_boot_state = adev->pm.dpm.boot_ps;
5169 const struct si_ulv_param *ulv = &si_pi->ulv;
5170 SISLANDS_SMC_STATETABLE *table = &si_pi->smc_statetable;
5171 int ret;
5172 u32 lane_width;
5173 u32 vr_hot_gpio;
5174
5175 si_populate_smc_voltage_tables(adev, table);
5176
5177 switch (adev->pm.int_thermal_type) {
5178 case THERMAL_TYPE_SI:
5179 case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
5180 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
5181 break;
5182 case THERMAL_TYPE_NONE:
5183 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
5184 break;
5185 default:
5186 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
5187 break;
5188 }
5189
5190 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
5191 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
5192
5193 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
5194 if ((adev->pdev->device != 0x6818) && (adev->pdev->device != 0x6819))
5195 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
5196 }
5197
5198 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
5199 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
5200
5201 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5202 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
5203
5204 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
5205 table->extraFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
5206
5207 if (adev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
5208 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
5209 vr_hot_gpio = adev->pm.dpm.backbias_response_time;
5210 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
5211 vr_hot_gpio);
5212 }
5213
5214 ret = si_populate_smc_initial_state(adev, amdgpu_boot_state, table);
5215 if (ret)
5216 return ret;
5217
5218 ret = si_populate_smc_acpi_state(adev, table);
5219 if (ret)
5220 return ret;
5221
5222 table->driverState = table->initialState;
5223
5224 ret = si_do_program_memory_timing_parameters(adev, amdgpu_boot_state,
5225 SISLANDS_INITIAL_STATE_ARB_INDEX);
5226 if (ret)
5227 return ret;
5228
5229 if (ulv->supported && ulv->pl.vddc) {
5230 ret = si_populate_ulv_state(adev, &table->ULVState);
5231 if (ret)
5232 return ret;
5233
5234 ret = si_program_ulv_memory_timing_parameters(adev);
5235 if (ret)
5236 return ret;
5237
5238 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
5239 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
5240
5241 lane_width = amdgpu_get_pcie_lanes(adev);
5242 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5243 } else {
5244 table->ULVState = table->initialState;
5245 }
5246
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]5247 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->state_table_start,
5248 (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
5249 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5250}
5251
5252static int si_calculate_sclk_params(struct amdgpu_device *adev,
5253 u32 engine_clock,
5254 SISLANDS_SMC_SCLK_VALUE *sclk)
5255{
5256 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5257 struct si_power_info *si_pi = si_get_pi(adev);
5258 struct atom_clock_dividers dividers;
5259 u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
5260 u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
5261 u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
5262 u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
5263 u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
5264 u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
5265 u64 tmp;
5266 u32 reference_clock = adev->clock.spll.reference_freq;
5267 u32 reference_divider;
5268 u32 fbdiv;
5269 int ret;
5270
5271 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
5272 engine_clock, false, &dividers);
5273 if (ret)
5274 return ret;
5275
5276 reference_divider = 1 + dividers.ref_div;
5277
5278 tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
5279 do_div(tmp, reference_clock);
5280 fbdiv = (u32) tmp;
5281
5282 spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
5283 spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
5284 spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
5285
5286 spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
5287 spll_func_cntl_2 |= SCLK_MUX_SEL(2);
5288
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5289 spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
5290 spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
5291 spll_func_cntl_3 |= SPLL_DITHEN;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5292
5293 if (pi->sclk_ss) {
5294 struct amdgpu_atom_ss ss;
5295 u32 vco_freq = engine_clock * dividers.post_div;
5296
5297 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
5298 ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
5299 u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
5300 u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
5301
5302 cg_spll_spread_spectrum &= ~CLK_S_MASK;
5303 cg_spll_spread_spectrum |= CLK_S(clk_s);
5304 cg_spll_spread_spectrum |= SSEN;
5305
5306 cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
5307 cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
5308 }
5309 }
5310
5311 sclk->sclk_value = engine_clock;
5312 sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
5313 sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
5314 sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
5315 sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
5316 sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
5317 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
5318
5319 return 0;
5320}
5321
5322static int si_populate_sclk_value(struct amdgpu_device *adev,
5323 u32 engine_clock,
5324 SISLANDS_SMC_SCLK_VALUE *sclk)
5325{
5326 SISLANDS_SMC_SCLK_VALUE sclk_tmp;
5327 int ret;
5328
5329 ret = si_calculate_sclk_params(adev, engine_clock, &sclk_tmp);
5330 if (!ret) {
5331 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
5332 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
5333 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
5334 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
5335 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
5336 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
5337 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
5338 }
5339
5340 return ret;
5341}
5342
5343static int si_populate_mclk_value(struct amdgpu_device *adev,
5344 u32 engine_clock,
5345 u32 memory_clock,
5346 SISLANDS_SMC_MCLK_VALUE *mclk,
5347 bool strobe_mode,
5348 bool dll_state_on)
5349{
5350 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5351 struct si_power_info *si_pi = si_get_pi(adev);
5352 u32 dll_cntl = si_pi->clock_registers.dll_cntl;
5353 u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
5354 u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
5355 u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
5356 u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
5357 u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
5358 u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
5359 u32 mpll_ss1 = si_pi->clock_registers.mpll_ss1;
5360 u32 mpll_ss2 = si_pi->clock_registers.mpll_ss2;
5361 struct atom_mpll_param mpll_param;
5362 int ret;
5363
5364 ret = amdgpu_atombios_get_memory_pll_dividers(adev, memory_clock, strobe_mode, &mpll_param);
5365 if (ret)
5366 return ret;
5367
5368 mpll_func_cntl &= ~BWCTRL_MASK;
5369 mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
5370
5371 mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
5372 mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
5373 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
5374
5375 mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
5376 mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
5377
5378 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5379 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
5380 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
5381 YCLK_POST_DIV(mpll_param.post_div);
5382 }
5383
5384 if (pi->mclk_ss) {
5385 struct amdgpu_atom_ss ss;
5386 u32 freq_nom;
5387 u32 tmp;
5388 u32 reference_clock = adev->clock.mpll.reference_freq;
5389
5390 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5)
5391 freq_nom = memory_clock * 4;
5392 else
5393 freq_nom = memory_clock * 2;
5394
5395 tmp = freq_nom / reference_clock;
5396 tmp = tmp * tmp;
5397 if (amdgpu_atombios_get_asic_ss_info(adev, &ss,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5398 ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5399 u32 clks = reference_clock * 5 / ss.rate;
5400 u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
5401
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5402 mpll_ss1 &= ~CLKV_MASK;
5403 mpll_ss1 |= CLKV(clkv);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5404
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5405 mpll_ss2 &= ~CLKS_MASK;
5406 mpll_ss2 |= CLKS(clks);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5407 }
5408 }
5409
5410 mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
5411 mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
5412
5413 if (dll_state_on)
5414 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
5415 else
5416 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
5417
5418 mclk->mclk_value = cpu_to_be32(memory_clock);
5419 mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
5420 mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
5421 mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
5422 mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
5423 mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
5424 mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
5425 mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
5426 mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
5427 mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
5428
5429 return 0;
5430}
5431
5432static void si_populate_smc_sp(struct amdgpu_device *adev,
5433 struct amdgpu_ps *amdgpu_state,
5434 SISLANDS_SMC_SWSTATE *smc_state)
5435{
5436 struct si_ps *ps = si_get_ps(amdgpu_state);
5437 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5438 int i;
5439
5440 for (i = 0; i < ps->performance_level_count - 1; i++)
5441 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
5442
5443 smc_state->levels[ps->performance_level_count - 1].bSP =
5444 cpu_to_be32(pi->psp);
5445}
5446
5447static int si_convert_power_level_to_smc(struct amdgpu_device *adev,
5448 struct rv7xx_pl *pl,
5449 SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
5450{
5451 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5452 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5453 struct si_power_info *si_pi = si_get_pi(adev);
5454 int ret;
5455 bool dll_state_on;
5456 u16 std_vddc;
5457 bool gmc_pg = false;
5458
5459 if (eg_pi->pcie_performance_request &&
5460 (si_pi->force_pcie_gen != AMDGPU_PCIE_GEN_INVALID))
5461 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
5462 else
5463 level->gen2PCIE = (u8)pl->pcie_gen;
5464
5465 ret = si_populate_sclk_value(adev, pl->sclk, &level->sclk);
5466 if (ret)
5467 return ret;
5468
5469 level->mcFlags = 0;
5470
5471 if (pi->mclk_stutter_mode_threshold &&
5472 (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
5473 !eg_pi->uvd_enabled &&
5474 (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
5475 (adev->pm.dpm.new_active_crtc_count <= 2)) {
5476 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
5477
5478 if (gmc_pg)
5479 level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
5480 }
5481
5482 if (adev->mc.vram_type == AMDGPU_VRAM_TYPE_GDDR5) {
5483 if (pl->mclk > pi->mclk_edc_enable_threshold)
5484 level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
5485
5486 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
5487 level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
5488
5489 level->strobeMode = si_get_strobe_mode_settings(adev, pl->mclk);
5490
5491 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
5492 if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
5493 ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
5494 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5495 else
5496 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
5497 } else {
5498 dll_state_on = false;
5499 }
5500 } else {
5501 level->strobeMode = si_get_strobe_mode_settings(adev,
5502 pl->mclk);
5503
5504 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
5505 }
5506
5507 ret = si_populate_mclk_value(adev,
5508 pl->sclk,
5509 pl->mclk,
5510 &level->mclk,
5511 (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
5512 if (ret)
5513 return ret;
5514
5515 ret = si_populate_voltage_value(adev,
5516 &eg_pi->vddc_voltage_table,
5517 pl->vddc, &level->vddc);
5518 if (ret)
5519 return ret;
5520
5521
5522 ret = si_get_std_voltage_value(adev, &level->vddc, &std_vddc);
5523 if (ret)
5524 return ret;
5525
5526 ret = si_populate_std_voltage_value(adev, std_vddc,
5527 level->vddc.index, &level->std_vddc);
5528 if (ret)
5529 return ret;
5530
5531 if (eg_pi->vddci_control) {
5532 ret = si_populate_voltage_value(adev, &eg_pi->vddci_voltage_table,
5533 pl->vddci, &level->vddci);
5534 if (ret)
5535 return ret;
5536 }
5537
5538 if (si_pi->vddc_phase_shed_control) {
5539 ret = si_populate_phase_shedding_value(adev,
5540 &adev->pm.dpm.dyn_state.phase_shedding_limits_table,
5541 pl->vddc,
5542 pl->sclk,
5543 pl->mclk,
5544 &level->vddc);
5545 if (ret)
5546 return ret;
5547 }
5548
5549 level->MaxPoweredUpCU = si_pi->max_cu;
5550
5551 ret = si_populate_mvdd_value(adev, pl->mclk, &level->mvdd);
5552
5553 return ret;
5554}
5555
5556static int si_populate_smc_t(struct amdgpu_device *adev,
5557 struct amdgpu_ps *amdgpu_state,
5558 SISLANDS_SMC_SWSTATE *smc_state)
5559{
5560 struct rv7xx_power_info *pi = rv770_get_pi(adev);
5561 struct si_ps *state = si_get_ps(amdgpu_state);
5562 u32 a_t;
5563 u32 t_l, t_h;
5564 u32 high_bsp;
5565 int i, ret;
5566
5567 if (state->performance_level_count >= 9)
5568 return -EINVAL;
5569
5570 if (state->performance_level_count < 2) {
5571 a_t = CG_R(0xffff) | CG_L(0);
5572 smc_state->levels[0].aT = cpu_to_be32(a_t);
5573 return 0;
5574 }
5575
5576 smc_state->levels[0].aT = cpu_to_be32(0);
5577
5578 for (i = 0; i <= state->performance_level_count - 2; i++) {
5579 ret = r600_calculate_at(
5580 (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
5581 100 * R600_AH_DFLT,
5582 state->performance_levels[i + 1].sclk,
5583 state->performance_levels[i].sclk,
5584 &t_l,
5585 &t_h);
5586
5587 if (ret) {
5588 t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
5589 t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
5590 }
5591
5592 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
5593 a_t |= CG_R(t_l * pi->bsp / 20000);
5594 smc_state->levels[i].aT = cpu_to_be32(a_t);
5595
5596 high_bsp = (i == state->performance_level_count - 2) ?
5597 pi->pbsp : pi->bsp;
5598 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
5599 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
5600 }
5601
5602 return 0;
5603}
5604
5605static int si_disable_ulv(struct amdgpu_device *adev)
5606{
5607 struct si_power_info *si_pi = si_get_pi(adev);
5608 struct si_ulv_param *ulv = &si_pi->ulv;
5609
5610 if (ulv->supported)
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]5611 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5612 0 : -EINVAL;
5613
5614 return 0;
5615}
5616
5617static bool si_is_state_ulv_compatible(struct amdgpu_device *adev,
5618 struct amdgpu_ps *amdgpu_state)
5619{
5620 const struct si_power_info *si_pi = si_get_pi(adev);
5621 const struct si_ulv_param *ulv = &si_pi->ulv;
5622 const struct si_ps *state = si_get_ps(amdgpu_state);
5623 int i;
5624
5625 if (state->performance_levels[0].mclk != ulv->pl.mclk)
5626 return false;
5627
5628 /* XXX validate against display requirements! */
5629
5630 for (i = 0; i < adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
5631 if (adev->clock.current_dispclk <=
5632 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
5633 if (ulv->pl.vddc <
5634 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
5635 return false;
5636 }
5637 }
5638
5639 if ((amdgpu_state->vclk != 0) || (amdgpu_state->dclk != 0))
5640 return false;
5641
5642 return true;
5643}
5644
5645static int si_set_power_state_conditionally_enable_ulv(struct amdgpu_device *adev,
5646 struct amdgpu_ps *amdgpu_new_state)
5647{
5648 const struct si_power_info *si_pi = si_get_pi(adev);
5649 const struct si_ulv_param *ulv = &si_pi->ulv;
5650
5651 if (ulv->supported) {
5652 if (si_is_state_ulv_compatible(adev, amdgpu_new_state))
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]5653 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5654 0 : -EINVAL;
5655 }
5656 return 0;
5657}
5658
5659static int si_convert_power_state_to_smc(struct amdgpu_device *adev,
5660 struct amdgpu_ps *amdgpu_state,
5661 SISLANDS_SMC_SWSTATE *smc_state)
5662{
5663 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
5664 struct ni_power_info *ni_pi = ni_get_pi(adev);
5665 struct si_power_info *si_pi = si_get_pi(adev);
5666 struct si_ps *state = si_get_ps(amdgpu_state);
5667 int i, ret;
5668 u32 threshold;
5669 u32 sclk_in_sr = 1350; /* ??? */
5670
5671 if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
5672 return -EINVAL;
5673
5674 threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
5675
5676 if (amdgpu_state->vclk && amdgpu_state->dclk) {
5677 eg_pi->uvd_enabled = true;
5678 if (eg_pi->smu_uvd_hs)
5679 smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
5680 } else {
5681 eg_pi->uvd_enabled = false;
5682 }
5683
5684 if (state->dc_compatible)
5685 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
5686
5687 smc_state->levelCount = 0;
5688 for (i = 0; i < state->performance_level_count; i++) {
5689 if (eg_pi->sclk_deep_sleep) {
5690 if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
5691 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
5692 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
5693 else
5694 smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
5695 }
5696 }
5697
5698 ret = si_convert_power_level_to_smc(adev, &state->performance_levels[i],
5699 &smc_state->levels[i]);
5700 smc_state->levels[i].arbRefreshState =
5701 (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
5702
5703 if (ret)
5704 return ret;
5705
5706 if (ni_pi->enable_power_containment)
5707 smc_state->levels[i].displayWatermark =
5708 (state->performance_levels[i].sclk < threshold) ?
5709 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5710 else
5711 smc_state->levels[i].displayWatermark = (i < 2) ?
5712 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5713
5714 if (eg_pi->dynamic_ac_timing)
5715 smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5716 else
5717 smc_state->levels[i].ACIndex = 0;
5718
5719 smc_state->levelCount++;
5720 }
5721
5722 si_write_smc_soft_register(adev,
5723 SI_SMC_SOFT_REGISTER_watermark_threshold,
5724 threshold / 512);
5725
5726 si_populate_smc_sp(adev, amdgpu_state, smc_state);
5727
5728 ret = si_populate_power_containment_values(adev, amdgpu_state, smc_state);
5729 if (ret)
5730 ni_pi->enable_power_containment = false;
5731
5732 ret = si_populate_sq_ramping_values(adev, amdgpu_state, smc_state);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5733 if (ret)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5734 ni_pi->enable_sq_ramping = false;
5735
5736 return si_populate_smc_t(adev, amdgpu_state, smc_state);
5737}
5738
5739static int si_upload_sw_state(struct amdgpu_device *adev,
5740 struct amdgpu_ps *amdgpu_new_state)
5741{
5742 struct si_power_info *si_pi = si_get_pi(adev);
5743 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
5744 int ret;
5745 u32 address = si_pi->state_table_start +
5746 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5747 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5748 ((new_state->performance_level_count - 1) *
5749 sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5750 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5751
5752 memset(smc_state, 0, state_size);
5753
5754 ret = si_convert_power_state_to_smc(adev, amdgpu_new_state, smc_state);
5755 if (ret)
5756 return ret;
5757
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]5758 return amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5759 state_size, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5760}
5761
5762static int si_upload_ulv_state(struct amdgpu_device *adev)
5763{
5764 struct si_power_info *si_pi = si_get_pi(adev);
5765 struct si_ulv_param *ulv = &si_pi->ulv;
5766 int ret = 0;
5767
5768 if (ulv->supported && ulv->pl.vddc) {
5769 u32 address = si_pi->state_table_start +
5770 offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5771 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5772 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5773
5774 memset(smc_state, 0, state_size);
5775
5776 ret = si_populate_ulv_state(adev, smc_state);
5777 if (!ret)
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]5778 ret = amdgpu_si_copy_bytes_to_smc(adev, address, (u8 *)smc_state,
5779 state_size, si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5780 }
5781
5782 return ret;
5783}
5784
5785static int si_upload_smc_data(struct amdgpu_device *adev)
5786{
5787 struct amdgpu_crtc *amdgpu_crtc = NULL;
5788 int i;
5789
5790 if (adev->pm.dpm.new_active_crtc_count == 0)
5791 return 0;
5792
5793 for (i = 0; i < adev->mode_info.num_crtc; i++) {
5794 if (adev->pm.dpm.new_active_crtcs & (1 << i)) {
5795 amdgpu_crtc = adev->mode_info.crtcs[i];
5796 break;
5797 }
5798 }
5799
5800 if (amdgpu_crtc == NULL)
5801 return 0;
5802
5803 if (amdgpu_crtc->line_time <= 0)
5804 return 0;
5805
5806 if (si_write_smc_soft_register(adev,
5807 SI_SMC_SOFT_REGISTER_crtc_index,
5808 amdgpu_crtc->crtc_id) != PPSMC_Result_OK)
5809 return 0;
5810
5811 if (si_write_smc_soft_register(adev,
5812 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5813 amdgpu_crtc->wm_high / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5814 return 0;
5815
5816 if (si_write_smc_soft_register(adev,
5817 SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5818 amdgpu_crtc->wm_low / amdgpu_crtc->line_time) != PPSMC_Result_OK)
5819 return 0;
5820
5821 return 0;
5822}
5823
5824static int si_set_mc_special_registers(struct amdgpu_device *adev,
5825 struct si_mc_reg_table *table)
5826{
5827 u8 i, j, k;
5828 u32 temp_reg;
5829
5830 for (i = 0, j = table->last; i < table->last; i++) {
5831 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5832 return -EINVAL;
5833 switch (table->mc_reg_address[i].s1) {
5834 case MC_SEQ_MISC1:
5835 temp_reg = RREG32(MC_PMG_CMD_EMRS);
5836 table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS;
5837 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP;
5838 for (k = 0; k < table->num_entries; k++)
5839 table->mc_reg_table_entry[k].mc_data[j] =
5840 ((temp_reg & 0xffff0000)) |
5841 ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5842 j++;
5843 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5844 return -EINVAL;
5845
5846 temp_reg = RREG32(MC_PMG_CMD_MRS);
5847 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS;
5848 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP;
5849 for (k = 0; k < table->num_entries; k++) {
5850 table->mc_reg_table_entry[k].mc_data[j] =
5851 (temp_reg & 0xffff0000) |
5852 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5853 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5)
5854 table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5855 }
5856 j++;
5857 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5858 return -EINVAL;
5859
5860 if (adev->mc.vram_type != AMDGPU_VRAM_TYPE_GDDR5) {
5861 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD;
5862 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD;
5863 for (k = 0; k < table->num_entries; k++)
5864 table->mc_reg_table_entry[k].mc_data[j] =
5865 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5866 j++;
5867 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5868 return -EINVAL;
5869 }
5870 break;
5871 case MC_SEQ_RESERVE_M:
5872 temp_reg = RREG32(MC_PMG_CMD_MRS1);
5873 table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1;
5874 table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP;
5875 for(k = 0; k < table->num_entries; k++)
5876 table->mc_reg_table_entry[k].mc_data[j] =
5877 (temp_reg & 0xffff0000) |
5878 (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5879 j++;
5880 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5881 return -EINVAL;
5882 break;
5883 default:
5884 break;
5885 }
5886 }
5887
5888 table->last = j;
5889
5890 return 0;
5891}
5892
5893static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5894{
5895 bool result = true;
5896 switch (in_reg) {
5897 case MC_SEQ_RAS_TIMING:
5898 *out_reg = MC_SEQ_RAS_TIMING_LP;
5899 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5900 case MC_SEQ_CAS_TIMING:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5901 *out_reg = MC_SEQ_CAS_TIMING_LP;
5902 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5903 case MC_SEQ_MISC_TIMING:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5904 *out_reg = MC_SEQ_MISC_TIMING_LP;
5905 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5906 case MC_SEQ_MISC_TIMING2:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5907 *out_reg = MC_SEQ_MISC_TIMING2_LP;
5908 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5909 case MC_SEQ_RD_CTL_D0:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5910 *out_reg = MC_SEQ_RD_CTL_D0_LP;
5911 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5912 case MC_SEQ_RD_CTL_D1:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5913 *out_reg = MC_SEQ_RD_CTL_D1_LP;
5914 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5915 case MC_SEQ_WR_CTL_D0:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5916 *out_reg = MC_SEQ_WR_CTL_D0_LP;
5917 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5918 case MC_SEQ_WR_CTL_D1:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5919 *out_reg = MC_SEQ_WR_CTL_D1_LP;
5920 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5921 case MC_PMG_CMD_EMRS:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5922 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP;
5923 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5924 case MC_PMG_CMD_MRS:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5925 *out_reg = MC_SEQ_PMG_CMD_MRS_LP;
5926 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5927 case MC_PMG_CMD_MRS1:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5928 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP;
5929 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5930 case MC_SEQ_PMG_TIMING:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5931 *out_reg = MC_SEQ_PMG_TIMING_LP;
5932 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5933 case MC_PMG_CMD_MRS2:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5934 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP;
5935 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5936 case MC_SEQ_WR_CTL_2:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5937 *out_reg = MC_SEQ_WR_CTL_2_LP;
5938 break;
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]5939 default:
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]5940 result = false;
5941 break;
5942 }
5943
5944 return result;
5945}
5946
5947static void si_set_valid_flag(struct si_mc_reg_table *table)
5948{
5949 u8 i, j;
5950
5951 for (i = 0; i < table->last; i++) {
5952 for (j = 1; j < table->num_entries; j++) {
5953 if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5954 table->valid_flag |= 1 << i;
5955 break;
5956 }
5957 }
5958 }
5959}
5960
5961static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5962{
5963 u32 i;
5964 u16 address;
5965
5966 for (i = 0; i < table->last; i++)
5967 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5968 address : table->mc_reg_address[i].s1;
5969
5970}
5971
5972static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5973 struct si_mc_reg_table *si_table)
5974{
5975 u8 i, j;
5976
5977 if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5978 return -EINVAL;
5979 if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5980 return -EINVAL;
5981
5982 for (i = 0; i < table->last; i++)
5983 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5984 si_table->last = table->last;
5985
5986 for (i = 0; i < table->num_entries; i++) {
5987 si_table->mc_reg_table_entry[i].mclk_max =
5988 table->mc_reg_table_entry[i].mclk_max;
5989 for (j = 0; j < table->last; j++) {
5990 si_table->mc_reg_table_entry[i].mc_data[j] =
5991 table->mc_reg_table_entry[i].mc_data[j];
5992 }
5993 }
5994 si_table->num_entries = table->num_entries;
5995
5996 return 0;
5997}
5998
5999static int si_initialize_mc_reg_table(struct amdgpu_device *adev)
6000{
6001 struct si_power_info *si_pi = si_get_pi(adev);
6002 struct atom_mc_reg_table *table;
6003 struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
6004 u8 module_index = rv770_get_memory_module_index(adev);
6005 int ret;
6006
6007 table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
6008 if (!table)
6009 return -ENOMEM;
6010
6011 WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
6012 WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
6013 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
6014 WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
6015 WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
6016 WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
6017 WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
6018 WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
6019 WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
6020 WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
6021 WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
6022 WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
6023 WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
6024 WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
6025
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6026 ret = amdgpu_atombios_init_mc_reg_table(adev, module_index, table);
6027 if (ret)
6028 goto init_mc_done;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6029
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6030 ret = si_copy_vbios_mc_reg_table(table, si_table);
6031 if (ret)
6032 goto init_mc_done;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6033
6034 si_set_s0_mc_reg_index(si_table);
6035
6036 ret = si_set_mc_special_registers(adev, si_table);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6037 if (ret)
6038 goto init_mc_done;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6039
6040 si_set_valid_flag(si_table);
6041
6042init_mc_done:
6043 kfree(table);
6044
6045 return ret;
6046
6047}
6048
6049static void si_populate_mc_reg_addresses(struct amdgpu_device *adev,
6050 SMC_SIslands_MCRegisters *mc_reg_table)
6051{
6052 struct si_power_info *si_pi = si_get_pi(adev);
6053 u32 i, j;
6054
6055 for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
6056 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
6057 if (i >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
6058 break;
6059 mc_reg_table->address[i].s0 =
6060 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
6061 mc_reg_table->address[i].s1 =
6062 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
6063 i++;
6064 }
6065 }
6066 mc_reg_table->last = (u8)i;
6067}
6068
6069static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
6070 SMC_SIslands_MCRegisterSet *data,
6071 u32 num_entries, u32 valid_flag)
6072{
6073 u32 i, j;
6074
6075 for(i = 0, j = 0; j < num_entries; j++) {
6076 if (valid_flag & (1 << j)) {
6077 data->value[i] = cpu_to_be32(entry->mc_data[j]);
6078 i++;
6079 }
6080 }
6081}
6082
6083static void si_convert_mc_reg_table_entry_to_smc(struct amdgpu_device *adev,
6084 struct rv7xx_pl *pl,
6085 SMC_SIslands_MCRegisterSet *mc_reg_table_data)
6086{
6087 struct si_power_info *si_pi = si_get_pi(adev);
6088 u32 i = 0;
6089
6090 for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
6091 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
6092 break;
6093 }
6094
6095 if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
6096 --i;
6097
6098 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
6099 mc_reg_table_data, si_pi->mc_reg_table.last,
6100 si_pi->mc_reg_table.valid_flag);
6101}
6102
6103static void si_convert_mc_reg_table_to_smc(struct amdgpu_device *adev,
6104 struct amdgpu_ps *amdgpu_state,
6105 SMC_SIslands_MCRegisters *mc_reg_table)
6106{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6107 struct si_ps *state = si_get_ps(amdgpu_state);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6108 int i;
6109
6110 for (i = 0; i < state->performance_level_count; i++) {
6111 si_convert_mc_reg_table_entry_to_smc(adev,
6112 &state->performance_levels[i],
6113 &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
6114 }
6115}
6116
6117static int si_populate_mc_reg_table(struct amdgpu_device *adev,
6118 struct amdgpu_ps *amdgpu_boot_state)
6119{
6120 struct si_ps *boot_state = si_get_ps(amdgpu_boot_state);
6121 struct si_power_info *si_pi = si_get_pi(adev);
6122 struct si_ulv_param *ulv = &si_pi->ulv;
6123 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6124
6125 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6126
6127 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_seq_index, 1);
6128
6129 si_populate_mc_reg_addresses(adev, smc_mc_reg_table);
6130
6131 si_convert_mc_reg_table_entry_to_smc(adev, &boot_state->performance_levels[0],
6132 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
6133
6134 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6135 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
6136 si_pi->mc_reg_table.last,
6137 si_pi->mc_reg_table.valid_flag);
6138
6139 if (ulv->supported && ulv->pl.vddc != 0)
6140 si_convert_mc_reg_table_entry_to_smc(adev, &ulv->pl,
6141 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
6142 else
6143 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
6144 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
6145 si_pi->mc_reg_table.last,
6146 si_pi->mc_reg_table.valid_flag);
6147
6148 si_convert_mc_reg_table_to_smc(adev, amdgpu_boot_state, smc_mc_reg_table);
6149
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]6150 return amdgpu_si_copy_bytes_to_smc(adev, si_pi->mc_reg_table_start,
6151 (u8 *)smc_mc_reg_table,
6152 sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6153}
6154
6155static int si_upload_mc_reg_table(struct amdgpu_device *adev,
6156 struct amdgpu_ps *amdgpu_new_state)
6157{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6158 struct si_ps *new_state = si_get_ps(amdgpu_new_state);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6159 struct si_power_info *si_pi = si_get_pi(adev);
6160 u32 address = si_pi->mc_reg_table_start +
6161 offsetof(SMC_SIslands_MCRegisters,
6162 data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
6163 SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
6164
6165 memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
6166
6167 si_convert_mc_reg_table_to_smc(adev, amdgpu_new_state, smc_mc_reg_table);
6168
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]6169 return amdgpu_si_copy_bytes_to_smc(adev, address,
6170 (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
6171 sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
6172 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6173}
6174
6175static void si_enable_voltage_control(struct amdgpu_device *adev, bool enable)
6176{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6177 if (enable)
6178 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
6179 else
6180 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6181}
6182
6183static enum amdgpu_pcie_gen si_get_maximum_link_speed(struct amdgpu_device *adev,
6184 struct amdgpu_ps *amdgpu_state)
6185{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]6186 struct si_ps *state = si_get_ps(amdgpu_state);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6187 int i;
6188 u16 pcie_speed, max_speed = 0;
6189
6190 for (i = 0; i < state->performance_level_count; i++) {
6191 pcie_speed = state->performance_levels[i].pcie_gen;
6192 if (max_speed < pcie_speed)
6193 max_speed = pcie_speed;
6194 }
6195 return max_speed;
6196}
6197
6198static u16 si_get_current_pcie_speed(struct amdgpu_device *adev)
6199{
6200 u32 speed_cntl;
6201
6202 speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
6203 speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
6204
6205 return (u16)speed_cntl;
6206}
6207
6208static void si_request_link_speed_change_before_state_change(struct amdgpu_device *adev,
6209 struct amdgpu_ps *amdgpu_new_state,
6210 struct amdgpu_ps *amdgpu_current_state)
6211{
6212 struct si_power_info *si_pi = si_get_pi(adev);
6213 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6214 enum amdgpu_pcie_gen current_link_speed;
6215
6216 if (si_pi->force_pcie_gen == AMDGPU_PCIE_GEN_INVALID)
6217 current_link_speed = si_get_maximum_link_speed(adev, amdgpu_current_state);
6218 else
6219 current_link_speed = si_pi->force_pcie_gen;
6220
6221 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
6222 si_pi->pspp_notify_required = false;
6223 if (target_link_speed > current_link_speed) {
6224 switch (target_link_speed) {
6225#if defined(CONFIG_ACPI)
6226 case AMDGPU_PCIE_GEN3:
6227 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
6228 break;
6229 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN2;
6230 if (current_link_speed == AMDGPU_PCIE_GEN2)
6231 break;
6232 case AMDGPU_PCIE_GEN2:
6233 if (amdgpu_acpi_pcie_performance_request(adev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
6234 break;
6235#endif
6236 default:
6237 si_pi->force_pcie_gen = si_get_current_pcie_speed(adev);
6238 break;
6239 }
6240 } else {
6241 if (target_link_speed < current_link_speed)
6242 si_pi->pspp_notify_required = true;
6243 }
6244}
6245
6246static void si_notify_link_speed_change_after_state_change(struct amdgpu_device *adev,
6247 struct amdgpu_ps *amdgpu_new_state,
6248 struct amdgpu_ps *amdgpu_current_state)
6249{
6250 struct si_power_info *si_pi = si_get_pi(adev);
6251 enum amdgpu_pcie_gen target_link_speed = si_get_maximum_link_speed(adev, amdgpu_new_state);
6252 u8 request;
6253
6254 if (si_pi->pspp_notify_required) {
6255 if (target_link_speed == AMDGPU_PCIE_GEN3)
6256 request = PCIE_PERF_REQ_PECI_GEN3;
6257 else if (target_link_speed == AMDGPU_PCIE_GEN2)
6258 request = PCIE_PERF_REQ_PECI_GEN2;
6259 else
6260 request = PCIE_PERF_REQ_PECI_GEN1;
6261
6262 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
6263 (si_get_current_pcie_speed(adev) > 0))
6264 return;
6265
6266#if defined(CONFIG_ACPI)
6267 amdgpu_acpi_pcie_performance_request(adev, request, false);
6268#endif
6269 }
6270}
6271
6272#if 0
6273static int si_ds_request(struct amdgpu_device *adev,
6274 bool ds_status_on, u32 count_write)
6275{
6276 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6277
6278 if (eg_pi->sclk_deep_sleep) {
6279 if (ds_status_on)
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]6280 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6281 PPSMC_Result_OK) ?
6282 0 : -EINVAL;
6283 else
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]6284 return (amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6285 PPSMC_Result_OK) ? 0 : -EINVAL;
6286 }
6287 return 0;
6288}
6289#endif
6290
6291static void si_set_max_cu_value(struct amdgpu_device *adev)
6292{
6293 struct si_power_info *si_pi = si_get_pi(adev);
6294
6295 if (adev->asic_type == CHIP_VERDE) {
6296 switch (adev->pdev->device) {
6297 case 0x6820:
6298 case 0x6825:
6299 case 0x6821:
6300 case 0x6823:
6301 case 0x6827:
6302 si_pi->max_cu = 10;
6303 break;
6304 case 0x682D:
6305 case 0x6824:
6306 case 0x682F:
6307 case 0x6826:
6308 si_pi->max_cu = 8;
6309 break;
6310 case 0x6828:
6311 case 0x6830:
6312 case 0x6831:
6313 case 0x6838:
6314 case 0x6839:
6315 case 0x683D:
6316 si_pi->max_cu = 10;
6317 break;
6318 case 0x683B:
6319 case 0x683F:
6320 case 0x6829:
6321 si_pi->max_cu = 8;
6322 break;
6323 default:
6324 si_pi->max_cu = 0;
6325 break;
6326 }
6327 } else {
6328 si_pi->max_cu = 0;
6329 }
6330}
6331
6332static int si_patch_single_dependency_table_based_on_leakage(struct amdgpu_device *adev,
6333 struct amdgpu_clock_voltage_dependency_table *table)
6334{
6335 u32 i;
6336 int j;
6337 u16 leakage_voltage;
6338
6339 if (table) {
6340 for (i = 0; i < table->count; i++) {
6341 switch (si_get_leakage_voltage_from_leakage_index(adev,
6342 table->entries[i].v,
6343 &leakage_voltage)) {
6344 case 0:
6345 table->entries[i].v = leakage_voltage;
6346 break;
6347 case -EAGAIN:
6348 return -EINVAL;
6349 case -EINVAL:
6350 default:
6351 break;
6352 }
6353 }
6354
6355 for (j = (table->count - 2); j >= 0; j--) {
6356 table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
6357 table->entries[j].v : table->entries[j + 1].v;
6358 }
6359 }
6360 return 0;
6361}
6362
6363static int si_patch_dependency_tables_based_on_leakage(struct amdgpu_device *adev)
6364{
6365 int ret = 0;
6366
6367 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6368 &adev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
Tom St Denisad2473a2016-09-07 08:42:41 -0400[diff] [blame]6369 if (ret)
6370 DRM_ERROR("Could not patch vddc_on_sclk leakage table\n");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6371 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6372 &adev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
Tom St Denisad2473a2016-09-07 08:42:41 -0400[diff] [blame]6373 if (ret)
6374 DRM_ERROR("Could not patch vddc_on_mclk leakage table\n");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6375 ret = si_patch_single_dependency_table_based_on_leakage(adev,
6376 &adev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
Tom St Denisad2473a2016-09-07 08:42:41 -0400[diff] [blame]6377 if (ret)
6378 DRM_ERROR("Could not patch vddci_on_mclk leakage table\n");
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6379 return ret;
6380}
6381
6382static void si_set_pcie_lane_width_in_smc(struct amdgpu_device *adev,
6383 struct amdgpu_ps *amdgpu_new_state,
6384 struct amdgpu_ps *amdgpu_current_state)
6385{
6386 u32 lane_width;
6387 u32 new_lane_width =
6388 (amdgpu_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6389 u32 current_lane_width =
6390 (amdgpu_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
6391
6392 if (new_lane_width != current_lane_width) {
6393 amdgpu_set_pcie_lanes(adev, new_lane_width);
6394 lane_width = amdgpu_get_pcie_lanes(adev);
6395 si_write_smc_soft_register(adev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
6396 }
6397}
6398
6399static void si_dpm_setup_asic(struct amdgpu_device *adev)
6400{
6401 si_read_clock_registers(adev);
6402 si_enable_acpi_power_management(adev);
6403}
6404
6405static int si_thermal_enable_alert(struct amdgpu_device *adev,
6406 bool enable)
6407{
6408 u32 thermal_int = RREG32(CG_THERMAL_INT);
6409
6410 if (enable) {
6411 PPSMC_Result result;
6412
6413 thermal_int &= ~(THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW);
6414 WREG32(CG_THERMAL_INT, thermal_int);
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]6415 result = amdgpu_si_send_msg_to_smc(adev, PPSMC_MSG_EnableThermalInterrupt);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6416 if (result != PPSMC_Result_OK) {
6417 DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
6418 return -EINVAL;
6419 }
6420 } else {
6421 thermal_int |= THERM_INT_MASK_HIGH | THERM_INT_MASK_LOW;
6422 WREG32(CG_THERMAL_INT, thermal_int);
6423 }
6424
6425 return 0;
6426}
6427
6428static int si_thermal_set_temperature_range(struct amdgpu_device *adev,
6429 int min_temp, int max_temp)
6430{
6431 int low_temp = 0 * 1000;
6432 int high_temp = 255 * 1000;
6433
6434 if (low_temp < min_temp)
6435 low_temp = min_temp;
6436 if (high_temp > max_temp)
6437 high_temp = max_temp;
6438 if (high_temp < low_temp) {
6439 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
6440 return -EINVAL;
6441 }
6442
6443 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
6444 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
6445 WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
6446
6447 adev->pm.dpm.thermal.min_temp = low_temp;
6448 adev->pm.dpm.thermal.max_temp = high_temp;
6449
6450 return 0;
6451}
6452
6453static void si_fan_ctrl_set_static_mode(struct amdgpu_device *adev, u32 mode)
6454{
6455 struct si_power_info *si_pi = si_get_pi(adev);
6456 u32 tmp;
6457
6458 if (si_pi->fan_ctrl_is_in_default_mode) {
6459 tmp = (RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK) >> FDO_PWM_MODE_SHIFT;
6460 si_pi->fan_ctrl_default_mode = tmp;
6461 tmp = (RREG32(CG_FDO_CTRL2) & TMIN_MASK) >> TMIN_SHIFT;
6462 si_pi->t_min = tmp;
6463 si_pi->fan_ctrl_is_in_default_mode = false;
6464 }
6465
6466 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6467 tmp |= TMIN(0);
6468 WREG32(CG_FDO_CTRL2, tmp);
6469
6470 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6471 tmp |= FDO_PWM_MODE(mode);
6472 WREG32(CG_FDO_CTRL2, tmp);
6473}
6474
6475static int si_thermal_setup_fan_table(struct amdgpu_device *adev)
6476{
6477 struct si_power_info *si_pi = si_get_pi(adev);
6478 PP_SIslands_FanTable fan_table = { FDO_MODE_HARDWARE };
6479 u32 duty100;
6480 u32 t_diff1, t_diff2, pwm_diff1, pwm_diff2;
6481 u16 fdo_min, slope1, slope2;
6482 u32 reference_clock, tmp;
6483 int ret;
6484 u64 tmp64;
6485
6486 if (!si_pi->fan_table_start) {
6487 adev->pm.dpm.fan.ucode_fan_control = false;
6488 return 0;
6489 }
6490
6491 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6492
6493 if (duty100 == 0) {
6494 adev->pm.dpm.fan.ucode_fan_control = false;
6495 return 0;
6496 }
6497
6498 tmp64 = (u64)adev->pm.dpm.fan.pwm_min * duty100;
6499 do_div(tmp64, 10000);
6500 fdo_min = (u16)tmp64;
6501
6502 t_diff1 = adev->pm.dpm.fan.t_med - adev->pm.dpm.fan.t_min;
6503 t_diff2 = adev->pm.dpm.fan.t_high - adev->pm.dpm.fan.t_med;
6504
6505 pwm_diff1 = adev->pm.dpm.fan.pwm_med - adev->pm.dpm.fan.pwm_min;
6506 pwm_diff2 = adev->pm.dpm.fan.pwm_high - adev->pm.dpm.fan.pwm_med;
6507
6508 slope1 = (u16)((50 + ((16 * duty100 * pwm_diff1) / t_diff1)) / 100);
6509 slope2 = (u16)((50 + ((16 * duty100 * pwm_diff2) / t_diff2)) / 100);
6510
6511 fan_table.temp_min = cpu_to_be16((50 + adev->pm.dpm.fan.t_min) / 100);
6512 fan_table.temp_med = cpu_to_be16((50 + adev->pm.dpm.fan.t_med) / 100);
6513 fan_table.temp_max = cpu_to_be16((50 + adev->pm.dpm.fan.t_max) / 100);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6514 fan_table.slope1 = cpu_to_be16(slope1);
6515 fan_table.slope2 = cpu_to_be16(slope2);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6516 fan_table.fdo_min = cpu_to_be16(fdo_min);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6517 fan_table.hys_down = cpu_to_be16(adev->pm.dpm.fan.t_hyst);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6518 fan_table.hys_up = cpu_to_be16(1);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6519 fan_table.hys_slope = cpu_to_be16(1);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6520 fan_table.temp_resp_lim = cpu_to_be16(5);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6521 reference_clock = amdgpu_asic_get_xclk(adev);
6522
6523 fan_table.refresh_period = cpu_to_be32((adev->pm.dpm.fan.cycle_delay *
6524 reference_clock) / 1600);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6525 fan_table.fdo_max = cpu_to_be16((u16)duty100);
6526
6527 tmp = (RREG32(CG_MULT_THERMAL_CTRL) & TEMP_SEL_MASK) >> TEMP_SEL_SHIFT;
6528 fan_table.temp_src = (uint8_t)tmp;
6529
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]6530 ret = amdgpu_si_copy_bytes_to_smc(adev,
6531 si_pi->fan_table_start,
6532 (u8 *)(&fan_table),
6533 sizeof(fan_table),
6534 si_pi->sram_end);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6535
6536 if (ret) {
6537 DRM_ERROR("Failed to load fan table to the SMC.");
6538 adev->pm.dpm.fan.ucode_fan_control = false;
6539 }
6540
Tom St Denisad2473a2016-09-07 08:42:41 -0400[diff] [blame]6541 return ret;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6542}
6543
6544static int si_fan_ctrl_start_smc_fan_control(struct amdgpu_device *adev)
6545{
6546 struct si_power_info *si_pi = si_get_pi(adev);
6547 PPSMC_Result ret;
6548
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]6549 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StartFanControl);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6550 if (ret == PPSMC_Result_OK) {
6551 si_pi->fan_is_controlled_by_smc = true;
6552 return 0;
6553 } else {
6554 return -EINVAL;
6555 }
6556}
6557
6558static int si_fan_ctrl_stop_smc_fan_control(struct amdgpu_device *adev)
6559{
6560 struct si_power_info *si_pi = si_get_pi(adev);
6561 PPSMC_Result ret;
6562
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]6563 ret = amdgpu_si_send_msg_to_smc(adev, PPSMC_StopFanControl);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6564
6565 if (ret == PPSMC_Result_OK) {
6566 si_pi->fan_is_controlled_by_smc = false;
6567 return 0;
6568 } else {
6569 return -EINVAL;
6570 }
6571}
6572
6573static int si_dpm_get_fan_speed_percent(struct amdgpu_device *adev,
6574 u32 *speed)
6575{
6576 u32 duty, duty100;
6577 u64 tmp64;
6578
6579 if (adev->pm.no_fan)
6580 return -ENOENT;
6581
6582 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6583 duty = (RREG32(CG_THERMAL_STATUS) & FDO_PWM_DUTY_MASK) >> FDO_PWM_DUTY_SHIFT;
6584
6585 if (duty100 == 0)
6586 return -EINVAL;
6587
6588 tmp64 = (u64)duty * 100;
6589 do_div(tmp64, duty100);
6590 *speed = (u32)tmp64;
6591
6592 if (*speed > 100)
6593 *speed = 100;
6594
6595 return 0;
6596}
6597
6598static int si_dpm_set_fan_speed_percent(struct amdgpu_device *adev,
6599 u32 speed)
6600{
6601 struct si_power_info *si_pi = si_get_pi(adev);
6602 u32 tmp;
6603 u32 duty, duty100;
6604 u64 tmp64;
6605
6606 if (adev->pm.no_fan)
6607 return -ENOENT;
6608
6609 if (si_pi->fan_is_controlled_by_smc)
6610 return -EINVAL;
6611
6612 if (speed > 100)
6613 return -EINVAL;
6614
6615 duty100 = (RREG32(CG_FDO_CTRL1) & FMAX_DUTY100_MASK) >> FMAX_DUTY100_SHIFT;
6616
6617 if (duty100 == 0)
6618 return -EINVAL;
6619
6620 tmp64 = (u64)speed * duty100;
6621 do_div(tmp64, 100);
6622 duty = (u32)tmp64;
6623
6624 tmp = RREG32(CG_FDO_CTRL0) & ~FDO_STATIC_DUTY_MASK;
6625 tmp |= FDO_STATIC_DUTY(duty);
6626 WREG32(CG_FDO_CTRL0, tmp);
6627
6628 return 0;
6629}
6630
6631static void si_dpm_set_fan_control_mode(struct amdgpu_device *adev, u32 mode)
6632{
6633 if (mode) {
6634 /* stop auto-manage */
6635 if (adev->pm.dpm.fan.ucode_fan_control)
6636 si_fan_ctrl_stop_smc_fan_control(adev);
6637 si_fan_ctrl_set_static_mode(adev, mode);
6638 } else {
6639 /* restart auto-manage */
6640 if (adev->pm.dpm.fan.ucode_fan_control)
6641 si_thermal_start_smc_fan_control(adev);
6642 else
6643 si_fan_ctrl_set_default_mode(adev);
6644 }
6645}
6646
6647static u32 si_dpm_get_fan_control_mode(struct amdgpu_device *adev)
6648{
6649 struct si_power_info *si_pi = si_get_pi(adev);
6650 u32 tmp;
6651
6652 if (si_pi->fan_is_controlled_by_smc)
6653 return 0;
6654
6655 tmp = RREG32(CG_FDO_CTRL2) & FDO_PWM_MODE_MASK;
6656 return (tmp >> FDO_PWM_MODE_SHIFT);
6657}
6658
6659#if 0
6660static int si_fan_ctrl_get_fan_speed_rpm(struct amdgpu_device *adev,
6661 u32 *speed)
6662{
6663 u32 tach_period;
6664 u32 xclk = amdgpu_asic_get_xclk(adev);
6665
6666 if (adev->pm.no_fan)
6667 return -ENOENT;
6668
6669 if (adev->pm.fan_pulses_per_revolution == 0)
6670 return -ENOENT;
6671
6672 tach_period = (RREG32(CG_TACH_STATUS) & TACH_PERIOD_MASK) >> TACH_PERIOD_SHIFT;
6673 if (tach_period == 0)
6674 return -ENOENT;
6675
6676 *speed = 60 * xclk * 10000 / tach_period;
6677
6678 return 0;
6679}
6680
6681static int si_fan_ctrl_set_fan_speed_rpm(struct amdgpu_device *adev,
6682 u32 speed)
6683{
6684 u32 tach_period, tmp;
6685 u32 xclk = amdgpu_asic_get_xclk(adev);
6686
6687 if (adev->pm.no_fan)
6688 return -ENOENT;
6689
6690 if (adev->pm.fan_pulses_per_revolution == 0)
6691 return -ENOENT;
6692
6693 if ((speed < adev->pm.fan_min_rpm) ||
6694 (speed > adev->pm.fan_max_rpm))
6695 return -EINVAL;
6696
6697 if (adev->pm.dpm.fan.ucode_fan_control)
6698 si_fan_ctrl_stop_smc_fan_control(adev);
6699
6700 tach_period = 60 * xclk * 10000 / (8 * speed);
6701 tmp = RREG32(CG_TACH_CTRL) & ~TARGET_PERIOD_MASK;
6702 tmp |= TARGET_PERIOD(tach_period);
6703 WREG32(CG_TACH_CTRL, tmp);
6704
6705 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC_RPM);
6706
6707 return 0;
6708}
6709#endif
6710
6711static void si_fan_ctrl_set_default_mode(struct amdgpu_device *adev)
6712{
6713 struct si_power_info *si_pi = si_get_pi(adev);
6714 u32 tmp;
6715
6716 if (!si_pi->fan_ctrl_is_in_default_mode) {
6717 tmp = RREG32(CG_FDO_CTRL2) & ~FDO_PWM_MODE_MASK;
6718 tmp |= FDO_PWM_MODE(si_pi->fan_ctrl_default_mode);
6719 WREG32(CG_FDO_CTRL2, tmp);
6720
6721 tmp = RREG32(CG_FDO_CTRL2) & ~TMIN_MASK;
6722 tmp |= TMIN(si_pi->t_min);
6723 WREG32(CG_FDO_CTRL2, tmp);
6724 si_pi->fan_ctrl_is_in_default_mode = true;
6725 }
6726}
6727
6728static void si_thermal_start_smc_fan_control(struct amdgpu_device *adev)
6729{
6730 if (adev->pm.dpm.fan.ucode_fan_control) {
6731 si_fan_ctrl_start_smc_fan_control(adev);
6732 si_fan_ctrl_set_static_mode(adev, FDO_PWM_MODE_STATIC);
6733 }
6734}
6735
6736static void si_thermal_initialize(struct amdgpu_device *adev)
6737{
6738 u32 tmp;
6739
6740 if (adev->pm.fan_pulses_per_revolution) {
6741 tmp = RREG32(CG_TACH_CTRL) & ~EDGE_PER_REV_MASK;
6742 tmp |= EDGE_PER_REV(adev->pm.fan_pulses_per_revolution -1);
6743 WREG32(CG_TACH_CTRL, tmp);
6744 }
6745
6746 tmp = RREG32(CG_FDO_CTRL2) & ~TACH_PWM_RESP_RATE_MASK;
6747 tmp |= TACH_PWM_RESP_RATE(0x28);
6748 WREG32(CG_FDO_CTRL2, tmp);
6749}
6750
6751static int si_thermal_start_thermal_controller(struct amdgpu_device *adev)
6752{
6753 int ret;
6754
6755 si_thermal_initialize(adev);
6756 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6757 if (ret)
6758 return ret;
6759 ret = si_thermal_enable_alert(adev, true);
6760 if (ret)
6761 return ret;
6762 if (adev->pm.dpm.fan.ucode_fan_control) {
6763 ret = si_halt_smc(adev);
6764 if (ret)
6765 return ret;
6766 ret = si_thermal_setup_fan_table(adev);
6767 if (ret)
6768 return ret;
6769 ret = si_resume_smc(adev);
6770 if (ret)
6771 return ret;
6772 si_thermal_start_smc_fan_control(adev);
6773 }
6774
6775 return 0;
6776}
6777
6778static void si_thermal_stop_thermal_controller(struct amdgpu_device *adev)
6779{
6780 if (!adev->pm.no_fan) {
6781 si_fan_ctrl_set_default_mode(adev);
6782 si_fan_ctrl_stop_smc_fan_control(adev);
6783 }
6784}
6785
6786static int si_dpm_enable(struct amdgpu_device *adev)
6787{
6788 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6789 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6790 struct si_power_info *si_pi = si_get_pi(adev);
6791 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6792 int ret;
6793
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]6794 if (amdgpu_si_is_smc_running(adev))
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6795 return -EINVAL;
6796 if (pi->voltage_control || si_pi->voltage_control_svi2)
6797 si_enable_voltage_control(adev, true);
6798 if (pi->mvdd_control)
6799 si_get_mvdd_configuration(adev);
6800 if (pi->voltage_control || si_pi->voltage_control_svi2) {
6801 ret = si_construct_voltage_tables(adev);
6802 if (ret) {
6803 DRM_ERROR("si_construct_voltage_tables failed\n");
6804 return ret;
6805 }
6806 }
6807 if (eg_pi->dynamic_ac_timing) {
6808 ret = si_initialize_mc_reg_table(adev);
6809 if (ret)
6810 eg_pi->dynamic_ac_timing = false;
6811 }
6812 if (pi->dynamic_ss)
6813 si_enable_spread_spectrum(adev, true);
6814 if (pi->thermal_protection)
6815 si_enable_thermal_protection(adev, true);
6816 si_setup_bsp(adev);
6817 si_program_git(adev);
6818 si_program_tp(adev);
6819 si_program_tpp(adev);
6820 si_program_sstp(adev);
6821 si_enable_display_gap(adev);
6822 si_program_vc(adev);
6823 ret = si_upload_firmware(adev);
6824 if (ret) {
6825 DRM_ERROR("si_upload_firmware failed\n");
6826 return ret;
6827 }
6828 ret = si_process_firmware_header(adev);
6829 if (ret) {
6830 DRM_ERROR("si_process_firmware_header failed\n");
6831 return ret;
6832 }
6833 ret = si_initial_switch_from_arb_f0_to_f1(adev);
6834 if (ret) {
6835 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
6836 return ret;
6837 }
6838 ret = si_init_smc_table(adev);
6839 if (ret) {
6840 DRM_ERROR("si_init_smc_table failed\n");
6841 return ret;
6842 }
6843 ret = si_init_smc_spll_table(adev);
6844 if (ret) {
6845 DRM_ERROR("si_init_smc_spll_table failed\n");
6846 return ret;
6847 }
6848 ret = si_init_arb_table_index(adev);
6849 if (ret) {
6850 DRM_ERROR("si_init_arb_table_index failed\n");
6851 return ret;
6852 }
6853 if (eg_pi->dynamic_ac_timing) {
6854 ret = si_populate_mc_reg_table(adev, boot_ps);
6855 if (ret) {
6856 DRM_ERROR("si_populate_mc_reg_table failed\n");
6857 return ret;
6858 }
6859 }
6860 ret = si_initialize_smc_cac_tables(adev);
6861 if (ret) {
6862 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
6863 return ret;
6864 }
6865 ret = si_initialize_hardware_cac_manager(adev);
6866 if (ret) {
6867 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
6868 return ret;
6869 }
6870 ret = si_initialize_smc_dte_tables(adev);
6871 if (ret) {
6872 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
6873 return ret;
6874 }
6875 ret = si_populate_smc_tdp_limits(adev, boot_ps);
6876 if (ret) {
6877 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
6878 return ret;
6879 }
6880 ret = si_populate_smc_tdp_limits_2(adev, boot_ps);
6881 if (ret) {
6882 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
6883 return ret;
6884 }
6885 si_program_response_times(adev);
6886 si_program_ds_registers(adev);
6887 si_dpm_start_smc(adev);
6888 ret = si_notify_smc_display_change(adev, false);
6889 if (ret) {
6890 DRM_ERROR("si_notify_smc_display_change failed\n");
6891 return ret;
6892 }
6893 si_enable_sclk_control(adev, true);
6894 si_start_dpm(adev);
6895
6896 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6897 si_thermal_start_thermal_controller(adev);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6898 ni_update_current_ps(adev, boot_ps);
6899
6900 return 0;
6901}
6902
6903static int si_set_temperature_range(struct amdgpu_device *adev)
6904{
6905 int ret;
6906
6907 ret = si_thermal_enable_alert(adev, false);
6908 if (ret)
6909 return ret;
6910 ret = si_thermal_set_temperature_range(adev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
6911 if (ret)
6912 return ret;
6913 ret = si_thermal_enable_alert(adev, true);
6914 if (ret)
6915 return ret;
6916
6917 return ret;
6918}
6919
6920static void si_dpm_disable(struct amdgpu_device *adev)
6921{
6922 struct rv7xx_power_info *pi = rv770_get_pi(adev);
6923 struct amdgpu_ps *boot_ps = adev->pm.dpm.boot_ps;
6924
Alex Deucher6861c832016-09-13 00:06:07 -0400[diff] [blame]6925 if (!amdgpu_si_is_smc_running(adev))
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6926 return;
6927 si_thermal_stop_thermal_controller(adev);
6928 si_disable_ulv(adev);
6929 si_clear_vc(adev);
6930 if (pi->thermal_protection)
6931 si_enable_thermal_protection(adev, false);
6932 si_enable_power_containment(adev, boot_ps, false);
6933 si_enable_smc_cac(adev, boot_ps, false);
6934 si_enable_spread_spectrum(adev, false);
6935 si_enable_auto_throttle_source(adev, AMDGPU_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
6936 si_stop_dpm(adev);
6937 si_reset_to_default(adev);
6938 si_dpm_stop_smc(adev);
6939 si_force_switch_to_arb_f0(adev);
6940
6941 ni_update_current_ps(adev, boot_ps);
6942}
6943
6944static int si_dpm_pre_set_power_state(struct amdgpu_device *adev)
6945{
6946 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6947 struct amdgpu_ps requested_ps = *adev->pm.dpm.requested_ps;
6948 struct amdgpu_ps *new_ps = &requested_ps;
6949
6950 ni_update_requested_ps(adev, new_ps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]6951 si_apply_state_adjust_rules(adev, &eg_pi->requested_rps);
6952
6953 return 0;
6954}
6955
6956static int si_power_control_set_level(struct amdgpu_device *adev)
6957{
6958 struct amdgpu_ps *new_ps = adev->pm.dpm.requested_ps;
6959 int ret;
6960
6961 ret = si_restrict_performance_levels_before_switch(adev);
6962 if (ret)
6963 return ret;
6964 ret = si_halt_smc(adev);
6965 if (ret)
6966 return ret;
6967 ret = si_populate_smc_tdp_limits(adev, new_ps);
6968 if (ret)
6969 return ret;
6970 ret = si_populate_smc_tdp_limits_2(adev, new_ps);
6971 if (ret)
6972 return ret;
6973 ret = si_resume_smc(adev);
6974 if (ret)
6975 return ret;
6976 ret = si_set_sw_state(adev);
6977 if (ret)
6978 return ret;
6979 return 0;
6980}
6981
6982static int si_dpm_set_power_state(struct amdgpu_device *adev)
6983{
6984 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
6985 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
6986 struct amdgpu_ps *old_ps = &eg_pi->current_rps;
6987 int ret;
6988
6989 ret = si_disable_ulv(adev);
6990 if (ret) {
6991 DRM_ERROR("si_disable_ulv failed\n");
6992 return ret;
6993 }
6994 ret = si_restrict_performance_levels_before_switch(adev);
6995 if (ret) {
6996 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
6997 return ret;
6998 }
6999 if (eg_pi->pcie_performance_request)
7000 si_request_link_speed_change_before_state_change(adev, new_ps, old_ps);
7001 ni_set_uvd_clock_before_set_eng_clock(adev, new_ps, old_ps);
7002 ret = si_enable_power_containment(adev, new_ps, false);
7003 if (ret) {
7004 DRM_ERROR("si_enable_power_containment failed\n");
7005 return ret;
7006 }
7007 ret = si_enable_smc_cac(adev, new_ps, false);
7008 if (ret) {
7009 DRM_ERROR("si_enable_smc_cac failed\n");
7010 return ret;
7011 }
7012 ret = si_halt_smc(adev);
7013 if (ret) {
7014 DRM_ERROR("si_halt_smc failed\n");
7015 return ret;
7016 }
7017 ret = si_upload_sw_state(adev, new_ps);
7018 if (ret) {
7019 DRM_ERROR("si_upload_sw_state failed\n");
7020 return ret;
7021 }
7022 ret = si_upload_smc_data(adev);
7023 if (ret) {
7024 DRM_ERROR("si_upload_smc_data failed\n");
7025 return ret;
7026 }
7027 ret = si_upload_ulv_state(adev);
7028 if (ret) {
7029 DRM_ERROR("si_upload_ulv_state failed\n");
7030 return ret;
7031 }
7032 if (eg_pi->dynamic_ac_timing) {
7033 ret = si_upload_mc_reg_table(adev, new_ps);
7034 if (ret) {
7035 DRM_ERROR("si_upload_mc_reg_table failed\n");
7036 return ret;
7037 }
7038 }
7039 ret = si_program_memory_timing_parameters(adev, new_ps);
7040 if (ret) {
7041 DRM_ERROR("si_program_memory_timing_parameters failed\n");
7042 return ret;
7043 }
7044 si_set_pcie_lane_width_in_smc(adev, new_ps, old_ps);
7045
7046 ret = si_resume_smc(adev);
7047 if (ret) {
7048 DRM_ERROR("si_resume_smc failed\n");
7049 return ret;
7050 }
7051 ret = si_set_sw_state(adev);
7052 if (ret) {
7053 DRM_ERROR("si_set_sw_state failed\n");
7054 return ret;
7055 }
7056 ni_set_uvd_clock_after_set_eng_clock(adev, new_ps, old_ps);
7057 if (eg_pi->pcie_performance_request)
7058 si_notify_link_speed_change_after_state_change(adev, new_ps, old_ps);
7059 ret = si_set_power_state_conditionally_enable_ulv(adev, new_ps);
7060 if (ret) {
7061 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
7062 return ret;
7063 }
7064 ret = si_enable_smc_cac(adev, new_ps, true);
7065 if (ret) {
7066 DRM_ERROR("si_enable_smc_cac failed\n");
7067 return ret;
7068 }
7069 ret = si_enable_power_containment(adev, new_ps, true);
7070 if (ret) {
7071 DRM_ERROR("si_enable_power_containment failed\n");
7072 return ret;
7073 }
7074
7075 ret = si_power_control_set_level(adev);
7076 if (ret) {
7077 DRM_ERROR("si_power_control_set_level failed\n");
7078 return ret;
7079 }
7080
7081 return 0;
7082}
7083
7084static void si_dpm_post_set_power_state(struct amdgpu_device *adev)
7085{
7086 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7087 struct amdgpu_ps *new_ps = &eg_pi->requested_rps;
7088
7089 ni_update_current_ps(adev, new_ps);
7090}
7091
7092#if 0
7093void si_dpm_reset_asic(struct amdgpu_device *adev)
7094{
7095 si_restrict_performance_levels_before_switch(adev);
7096 si_disable_ulv(adev);
7097 si_set_boot_state(adev);
7098}
7099#endif
7100
7101static void si_dpm_display_configuration_changed(struct amdgpu_device *adev)
7102{
7103 si_program_display_gap(adev);
7104}
7105
7106
7107static void si_parse_pplib_non_clock_info(struct amdgpu_device *adev,
7108 struct amdgpu_ps *rps,
7109 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
7110 u8 table_rev)
7111{
7112 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
7113 rps->class = le16_to_cpu(non_clock_info->usClassification);
7114 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
7115
7116 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
7117 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
7118 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
7119 } else if (r600_is_uvd_state(rps->class, rps->class2)) {
7120 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
7121 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
7122 } else {
7123 rps->vclk = 0;
7124 rps->dclk = 0;
7125 }
7126
7127 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
7128 adev->pm.dpm.boot_ps = rps;
7129 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
7130 adev->pm.dpm.uvd_ps = rps;
7131}
7132
7133static void si_parse_pplib_clock_info(struct amdgpu_device *adev,
7134 struct amdgpu_ps *rps, int index,
7135 union pplib_clock_info *clock_info)
7136{
7137 struct rv7xx_power_info *pi = rv770_get_pi(adev);
7138 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7139 struct si_power_info *si_pi = si_get_pi(adev);
7140 struct si_ps *ps = si_get_ps(rps);
7141 u16 leakage_voltage;
7142 struct rv7xx_pl *pl = &ps->performance_levels[index];
7143 int ret;
7144
7145 ps->performance_level_count = index + 1;
7146
7147 pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7148 pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
7149 pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7150 pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
7151
7152 pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
7153 pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
7154 pl->flags = le32_to_cpu(clock_info->si.ulFlags);
7155 pl->pcie_gen = r600_get_pcie_gen_support(adev,
7156 si_pi->sys_pcie_mask,
7157 si_pi->boot_pcie_gen,
7158 clock_info->si.ucPCIEGen);
7159
7160 /* patch up vddc if necessary */
7161 ret = si_get_leakage_voltage_from_leakage_index(adev, pl->vddc,
7162 &leakage_voltage);
7163 if (ret == 0)
7164 pl->vddc = leakage_voltage;
7165
7166 if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
7167 pi->acpi_vddc = pl->vddc;
7168 eg_pi->acpi_vddci = pl->vddci;
7169 si_pi->acpi_pcie_gen = pl->pcie_gen;
7170 }
7171
7172 if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
7173 index == 0) {
7174 /* XXX disable for A0 tahiti */
7175 si_pi->ulv.supported = false;
7176 si_pi->ulv.pl = *pl;
7177 si_pi->ulv.one_pcie_lane_in_ulv = false;
7178 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
7179 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
7180 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
7181 }
7182
7183 if (pi->min_vddc_in_table > pl->vddc)
7184 pi->min_vddc_in_table = pl->vddc;
7185
7186 if (pi->max_vddc_in_table < pl->vddc)
7187 pi->max_vddc_in_table = pl->vddc;
7188
7189 /* patch up boot state */
7190 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
7191 u16 vddc, vddci, mvdd;
7192 amdgpu_atombios_get_default_voltages(adev, &vddc, &vddci, &mvdd);
7193 pl->mclk = adev->clock.default_mclk;
7194 pl->sclk = adev->clock.default_sclk;
7195 pl->vddc = vddc;
7196 pl->vddci = vddci;
7197 si_pi->mvdd_bootup_value = mvdd;
7198 }
7199
7200 if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
7201 ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
7202 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
7203 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
7204 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
7205 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
7206 }
7207}
7208
7209union pplib_power_state {
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7210 struct _ATOM_PPLIB_STATE v1;
7211 struct _ATOM_PPLIB_STATE_V2 v2;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7212};
7213
7214static int si_parse_power_table(struct amdgpu_device *adev)
7215{
7216 struct amdgpu_mode_info *mode_info = &adev->mode_info;
7217 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
7218 union pplib_power_state *power_state;
7219 int i, j, k, non_clock_array_index, clock_array_index;
7220 union pplib_clock_info *clock_info;
7221 struct _StateArray *state_array;
7222 struct _ClockInfoArray *clock_info_array;
7223 struct _NonClockInfoArray *non_clock_info_array;
7224 union power_info *power_info;
7225 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7226 u16 data_offset;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7227 u8 frev, crev;
7228 u8 *power_state_offset;
7229 struct si_ps *ps;
7230
7231 if (!amdgpu_atom_parse_data_header(mode_info->atom_context, index, NULL,
7232 &frev, &crev, &data_offset))
7233 return -EINVAL;
7234 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
7235
7236 amdgpu_add_thermal_controller(adev);
7237
7238 state_array = (struct _StateArray *)
7239 (mode_info->atom_context->bios + data_offset +
7240 le16_to_cpu(power_info->pplib.usStateArrayOffset));
7241 clock_info_array = (struct _ClockInfoArray *)
7242 (mode_info->atom_context->bios + data_offset +
7243 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
7244 non_clock_info_array = (struct _NonClockInfoArray *)
7245 (mode_info->atom_context->bios + data_offset +
7246 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
7247
7248 adev->pm.dpm.ps = kzalloc(sizeof(struct amdgpu_ps) *
7249 state_array->ucNumEntries, GFP_KERNEL);
7250 if (!adev->pm.dpm.ps)
7251 return -ENOMEM;
7252 power_state_offset = (u8 *)state_array->states;
7253 for (i = 0; i < state_array->ucNumEntries; i++) {
7254 u8 *idx;
7255 power_state = (union pplib_power_state *)power_state_offset;
7256 non_clock_array_index = power_state->v2.nonClockInfoIndex;
7257 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
7258 &non_clock_info_array->nonClockInfo[non_clock_array_index];
7259 ps = kzalloc(sizeof(struct si_ps), GFP_KERNEL);
7260 if (ps == NULL) {
7261 kfree(adev->pm.dpm.ps);
7262 return -ENOMEM;
7263 }
7264 adev->pm.dpm.ps[i].ps_priv = ps;
7265 si_parse_pplib_non_clock_info(adev, &adev->pm.dpm.ps[i],
7266 non_clock_info,
7267 non_clock_info_array->ucEntrySize);
7268 k = 0;
7269 idx = (u8 *)&power_state->v2.clockInfoIndex[0];
7270 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
7271 clock_array_index = idx[j];
7272 if (clock_array_index >= clock_info_array->ucNumEntries)
7273 continue;
7274 if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
7275 break;
7276 clock_info = (union pplib_clock_info *)
7277 ((u8 *)&clock_info_array->clockInfo[0] +
7278 (clock_array_index * clock_info_array->ucEntrySize));
7279 si_parse_pplib_clock_info(adev,
7280 &adev->pm.dpm.ps[i], k,
7281 clock_info);
7282 k++;
7283 }
7284 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
7285 }
7286 adev->pm.dpm.num_ps = state_array->ucNumEntries;
7287
7288 /* fill in the vce power states */
Rex Zhu66ba1af2016-10-12 15:38:56 +0800[diff] [blame]7289 for (i = 0; i < adev->pm.dpm.num_of_vce_states; i++) {
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7290 u32 sclk, mclk;
7291 clock_array_index = adev->pm.dpm.vce_states[i].clk_idx;
7292 clock_info = (union pplib_clock_info *)
7293 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
7294 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
7295 sclk |= clock_info->si.ucEngineClockHigh << 16;
7296 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
7297 mclk |= clock_info->si.ucMemoryClockHigh << 16;
7298 adev->pm.dpm.vce_states[i].sclk = sclk;
7299 adev->pm.dpm.vce_states[i].mclk = mclk;
7300 }
7301
7302 return 0;
7303}
7304
7305static int si_dpm_init(struct amdgpu_device *adev)
7306{
7307 struct rv7xx_power_info *pi;
7308 struct evergreen_power_info *eg_pi;
7309 struct ni_power_info *ni_pi;
7310 struct si_power_info *si_pi;
7311 struct atom_clock_dividers dividers;
7312 int ret;
7313 u32 mask;
7314
7315 si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
7316 if (si_pi == NULL)
7317 return -ENOMEM;
7318 adev->pm.dpm.priv = si_pi;
7319 ni_pi = &si_pi->ni;
7320 eg_pi = &ni_pi->eg;
7321 pi = &eg_pi->rv7xx;
7322
7323 ret = drm_pcie_get_speed_cap_mask(adev->ddev, &mask);
7324 if (ret)
7325 si_pi->sys_pcie_mask = 0;
7326 else
7327 si_pi->sys_pcie_mask = mask;
7328 si_pi->force_pcie_gen = AMDGPU_PCIE_GEN_INVALID;
7329 si_pi->boot_pcie_gen = si_get_current_pcie_speed(adev);
7330
7331 si_set_max_cu_value(adev);
7332
7333 rv770_get_max_vddc(adev);
7334 si_get_leakage_vddc(adev);
7335 si_patch_dependency_tables_based_on_leakage(adev);
7336
7337 pi->acpi_vddc = 0;
7338 eg_pi->acpi_vddci = 0;
7339 pi->min_vddc_in_table = 0;
7340 pi->max_vddc_in_table = 0;
7341
7342 ret = amdgpu_get_platform_caps(adev);
7343 if (ret)
7344 return ret;
7345
7346 ret = amdgpu_parse_extended_power_table(adev);
7347 if (ret)
7348 return ret;
7349
7350 ret = si_parse_power_table(adev);
7351 if (ret)
7352 return ret;
7353
7354 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
7355 kzalloc(4 * sizeof(struct amdgpu_clock_voltage_dependency_entry), GFP_KERNEL);
7356 if (!adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
7357 amdgpu_free_extended_power_table(adev);
7358 return -ENOMEM;
7359 }
7360 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
7361 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
7362 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
7363 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
7364 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
7365 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
7366 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
7367 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
7368 adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
7369
7370 if (adev->pm.dpm.voltage_response_time == 0)
7371 adev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
7372 if (adev->pm.dpm.backbias_response_time == 0)
7373 adev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
7374
7375 ret = amdgpu_atombios_get_clock_dividers(adev, COMPUTE_ENGINE_PLL_PARAM,
7376 0, false, &dividers);
7377 if (ret)
7378 pi->ref_div = dividers.ref_div + 1;
7379 else
7380 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
7381
7382 eg_pi->smu_uvd_hs = false;
7383
7384 pi->mclk_strobe_mode_threshold = 40000;
7385 if (si_is_special_1gb_platform(adev))
7386 pi->mclk_stutter_mode_threshold = 0;
7387 else
7388 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
7389 pi->mclk_edc_enable_threshold = 40000;
7390 eg_pi->mclk_edc_wr_enable_threshold = 40000;
7391
7392 ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
7393
7394 pi->voltage_control =
7395 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7396 VOLTAGE_OBJ_GPIO_LUT);
7397 if (!pi->voltage_control) {
7398 si_pi->voltage_control_svi2 =
7399 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7400 VOLTAGE_OBJ_SVID2);
7401 if (si_pi->voltage_control_svi2)
7402 amdgpu_atombios_get_svi2_info(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7403 &si_pi->svd_gpio_id, &si_pi->svc_gpio_id);
7404 }
7405
7406 pi->mvdd_control =
7407 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_MVDDC,
7408 VOLTAGE_OBJ_GPIO_LUT);
7409
7410 eg_pi->vddci_control =
7411 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7412 VOLTAGE_OBJ_GPIO_LUT);
7413 if (!eg_pi->vddci_control)
7414 si_pi->vddci_control_svi2 =
7415 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDCI,
7416 VOLTAGE_OBJ_SVID2);
7417
7418 si_pi->vddc_phase_shed_control =
7419 amdgpu_atombios_is_voltage_gpio(adev, SET_VOLTAGE_TYPE_ASIC_VDDC,
7420 VOLTAGE_OBJ_PHASE_LUT);
7421
7422 rv770_get_engine_memory_ss(adev);
7423
7424 pi->asi = RV770_ASI_DFLT;
7425 pi->pasi = CYPRESS_HASI_DFLT;
7426 pi->vrc = SISLANDS_VRC_DFLT;
7427
7428 pi->gfx_clock_gating = true;
7429
7430 eg_pi->sclk_deep_sleep = true;
7431 si_pi->sclk_deep_sleep_above_low = false;
7432
7433 if (adev->pm.int_thermal_type != THERMAL_TYPE_NONE)
7434 pi->thermal_protection = true;
7435 else
7436 pi->thermal_protection = false;
7437
7438 eg_pi->dynamic_ac_timing = true;
7439
7440 eg_pi->light_sleep = true;
7441#if defined(CONFIG_ACPI)
7442 eg_pi->pcie_performance_request =
7443 amdgpu_acpi_is_pcie_performance_request_supported(adev);
7444#else
7445 eg_pi->pcie_performance_request = false;
7446#endif
7447
7448 si_pi->sram_end = SMC_RAM_END;
7449
7450 adev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
7451 adev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
7452 adev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
7453 adev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
7454 adev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
7455 adev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
7456 adev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
7457
7458 si_initialize_powertune_defaults(adev);
7459
7460 /* make sure dc limits are valid */
7461 if ((adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.sclk == 0) ||
7462 (adev->pm.dpm.dyn_state.max_clock_voltage_on_dc.mclk == 0))
7463 adev->pm.dpm.dyn_state.max_clock_voltage_on_dc =
7464 adev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
7465
7466 si_pi->fan_ctrl_is_in_default_mode = true;
7467
7468 return 0;
7469}
7470
7471static void si_dpm_fini(struct amdgpu_device *adev)
7472{
7473 int i;
7474
Tom St Denis9623e4b2016-09-06 09:42:55 -0400[diff] [blame]7475 if (adev->pm.dpm.ps)
7476 for (i = 0; i < adev->pm.dpm.num_ps; i++)
7477 kfree(adev->pm.dpm.ps[i].ps_priv);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7478 kfree(adev->pm.dpm.ps);
7479 kfree(adev->pm.dpm.priv);
7480 kfree(adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
7481 amdgpu_free_extended_power_table(adev);
7482}
7483
7484static void si_dpm_debugfs_print_current_performance_level(struct amdgpu_device *adev,
7485 struct seq_file *m)
7486{
7487 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7488 struct amdgpu_ps *rps = &eg_pi->current_rps;
7489 struct si_ps *ps = si_get_ps(rps);
7490 struct rv7xx_pl *pl;
7491 u32 current_index =
7492 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
7493 CURRENT_STATE_INDEX_SHIFT;
7494
7495 if (current_index >= ps->performance_level_count) {
7496 seq_printf(m, "invalid dpm profile %d\n", current_index);
7497 } else {
7498 pl = &ps->performance_levels[current_index];
7499 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7500 seq_printf(m, "power level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
7501 current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
7502 }
7503}
7504
7505static int si_dpm_set_interrupt_state(struct amdgpu_device *adev,
7506 struct amdgpu_irq_src *source,
7507 unsigned type,
7508 enum amdgpu_interrupt_state state)
7509{
7510 u32 cg_thermal_int;
7511
7512 switch (type) {
7513 case AMDGPU_THERMAL_IRQ_LOW_TO_HIGH:
7514 switch (state) {
7515 case AMDGPU_IRQ_STATE_DISABLE:
7516 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7517 cg_thermal_int |= THERM_INT_MASK_HIGH;
7518 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7519 break;
7520 case AMDGPU_IRQ_STATE_ENABLE:
7521 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7522 cg_thermal_int &= ~THERM_INT_MASK_HIGH;
7523 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7524 break;
7525 default:
7526 break;
7527 }
7528 break;
7529
7530 case AMDGPU_THERMAL_IRQ_HIGH_TO_LOW:
7531 switch (state) {
7532 case AMDGPU_IRQ_STATE_DISABLE:
7533 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7534 cg_thermal_int |= THERM_INT_MASK_LOW;
7535 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7536 break;
7537 case AMDGPU_IRQ_STATE_ENABLE:
7538 cg_thermal_int = RREG32_SMC(CG_THERMAL_INT);
7539 cg_thermal_int &= ~THERM_INT_MASK_LOW;
7540 WREG32_SMC(CG_THERMAL_INT, cg_thermal_int);
7541 break;
7542 default:
7543 break;
7544 }
7545 break;
7546
7547 default:
7548 break;
7549 }
7550 return 0;
7551}
7552
7553static int si_dpm_process_interrupt(struct amdgpu_device *adev,
Alex Deuchera1047772016-09-12 23:46:06 -0400[diff] [blame]7554 struct amdgpu_irq_src *source,
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7555 struct amdgpu_iv_entry *entry)
7556{
7557 bool queue_thermal = false;
7558
7559 if (entry == NULL)
7560 return -EINVAL;
7561
7562 switch (entry->src_id) {
7563 case 230: /* thermal low to high */
7564 DRM_DEBUG("IH: thermal low to high\n");
7565 adev->pm.dpm.thermal.high_to_low = false;
7566 queue_thermal = true;
7567 break;
7568 case 231: /* thermal high to low */
7569 DRM_DEBUG("IH: thermal high to low\n");
7570 adev->pm.dpm.thermal.high_to_low = true;
7571 queue_thermal = true;
7572 break;
7573 default:
7574 break;
7575 }
7576
7577 if (queue_thermal)
7578 schedule_work(&adev->pm.dpm.thermal.work);
7579
7580 return 0;
7581}
7582
7583static int si_dpm_late_init(void *handle)
7584{
7585 int ret;
7586 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7587
7588 if (!amdgpu_dpm)
7589 return 0;
7590
7591 /* init the sysfs and debugfs files late */
7592 ret = amdgpu_pm_sysfs_init(adev);
7593 if (ret)
7594 return ret;
7595
7596 ret = si_set_temperature_range(adev);
7597 if (ret)
7598 return ret;
7599#if 0 //TODO ?
7600 si_dpm_powergate_uvd(adev, true);
7601#endif
7602 return 0;
7603}
7604
7605/**
7606 * si_dpm_init_microcode - load ucode images from disk
7607 *
7608 * @adev: amdgpu_device pointer
7609 *
7610 * Use the firmware interface to load the ucode images into
7611 * the driver (not loaded into hw).
7612 * Returns 0 on success, error on failure.
7613 */
7614static int si_dpm_init_microcode(struct amdgpu_device *adev)
7615{
7616 const char *chip_name;
7617 char fw_name[30];
7618 int err;
7619
7620 DRM_DEBUG("\n");
7621 switch (adev->asic_type) {
7622 case CHIP_TAHITI:
7623 chip_name = "tahiti";
7624 break;
7625 case CHIP_PITCAIRN:
Flora Cui51654842016-12-15 13:43:59 +0800[diff] [blame]7626 if ((adev->pdev->revision == 0x81) &&
7627 ((adev->pdev->device == 0x6810) ||
7628 (adev->pdev->device == 0x6811)))
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]7629 chip_name = "pitcairn_k";
7630 else
7631 chip_name = "pitcairn";
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7632 break;
7633 case CHIP_VERDE:
Flora Cui51654842016-12-15 13:43:59 +0800[diff] [blame]7634 if (((adev->pdev->device == 0x6820) &&
7635 ((adev->pdev->revision == 0x81) ||
7636 (adev->pdev->revision == 0x83))) ||
7637 ((adev->pdev->device == 0x6821) &&
7638 ((adev->pdev->revision == 0x83) ||
7639 (adev->pdev->revision == 0x87))) ||
7640 ((adev->pdev->revision == 0x87) &&
7641 ((adev->pdev->device == 0x6823) ||
7642 (adev->pdev->device == 0x682b))))
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]7643 chip_name = "verde_k";
7644 else
7645 chip_name = "verde";
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7646 break;
7647 case CHIP_OLAND:
Flora Cui51654842016-12-15 13:43:59 +0800[diff] [blame]7648 if (((adev->pdev->revision == 0x81) &&
7649 ((adev->pdev->device == 0x6600) ||
7650 (adev->pdev->device == 0x6604) ||
7651 (adev->pdev->device == 0x6605) ||
7652 (adev->pdev->device == 0x6610))) ||
7653 ((adev->pdev->revision == 0x83) &&
7654 (adev->pdev->device == 0x6610)))
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]7655 chip_name = "oland_k";
7656 else
7657 chip_name = "oland";
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7658 break;
7659 case CHIP_HAINAN:
Flora Cui51654842016-12-15 13:43:59 +0800[diff] [blame]7660 if (((adev->pdev->revision == 0x81) &&
7661 (adev->pdev->device == 0x6660)) ||
7662 ((adev->pdev->revision == 0x83) &&
7663 ((adev->pdev->device == 0x6660) ||
7664 (adev->pdev->device == 0x6663) ||
7665 (adev->pdev->device == 0x6665) ||
Alex Deucher17324b62017-01-17 15:06:58 -0500[diff] [blame]7666 (adev->pdev->device == 0x6667))))
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]7667 chip_name = "hainan_k";
Alex Deucher17324b62017-01-17 15:06:58 -0500[diff] [blame]7668 else if ((adev->pdev->revision == 0xc3) &&
7669 (adev->pdev->device == 0x6665))
7670 chip_name = "banks_k_2";
Alex Deuchera8c65c12016-08-01 16:05:47 -0400[diff] [blame]7671 else
7672 chip_name = "hainan";
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7673 break;
7674 default: BUG();
7675 }
7676
7677 snprintf(fw_name, sizeof(fw_name), "radeon/%s_smc.bin", chip_name);
7678 err = request_firmware(&adev->pm.fw, fw_name, adev->dev);
7679 if (err)
7680 goto out;
7681 err = amdgpu_ucode_validate(adev->pm.fw);
7682
7683out:
7684 if (err) {
Huang Rui84b77332016-08-31 13:23:18 +0800[diff] [blame]7685 DRM_ERROR("si_smc: Failed to load firmware. err = %d\"%s\"\n",
7686 err, fw_name);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7687 release_firmware(adev->pm.fw);
7688 adev->pm.fw = NULL;
7689 }
7690 return err;
7691
7692}
7693
7694static int si_dpm_sw_init(void *handle)
7695{
7696 int ret;
7697 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7698
7699 ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
7700 if (ret)
7701 return ret;
7702
7703 ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
7704 if (ret)
7705 return ret;
7706
7707 /* default to balanced state */
7708 adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
7709 adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
Rex Zhue5d03ac2016-12-23 14:39:41 +0800[diff] [blame]7710 adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7711 adev->pm.default_sclk = adev->clock.default_sclk;
7712 adev->pm.default_mclk = adev->clock.default_mclk;
7713 adev->pm.current_sclk = adev->clock.default_sclk;
7714 adev->pm.current_mclk = adev->clock.default_mclk;
7715 adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
7716
7717 if (amdgpu_dpm == 0)
7718 return 0;
7719
7720 ret = si_dpm_init_microcode(adev);
7721 if (ret)
7722 return ret;
7723
7724 INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
7725 mutex_lock(&adev->pm.mutex);
7726 ret = si_dpm_init(adev);
7727 if (ret)
7728 goto dpm_failed;
7729 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7730 if (amdgpu_dpm == 1)
7731 amdgpu_pm_print_power_states(adev);
7732 mutex_unlock(&adev->pm.mutex);
7733 DRM_INFO("amdgpu: dpm initialized\n");
7734
7735 return 0;
7736
7737dpm_failed:
7738 si_dpm_fini(adev);
7739 mutex_unlock(&adev->pm.mutex);
7740 DRM_ERROR("amdgpu: dpm initialization failed\n");
7741 return ret;
7742}
7743
7744static int si_dpm_sw_fini(void *handle)
7745{
7746 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7747
Alex Deucher45607382016-10-21 16:30:10 -0400[diff] [blame]7748 flush_work(&adev->pm.dpm.thermal.work);
7749
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7750 mutex_lock(&adev->pm.mutex);
7751 amdgpu_pm_sysfs_fini(adev);
7752 si_dpm_fini(adev);
7753 mutex_unlock(&adev->pm.mutex);
7754
7755 return 0;
7756}
7757
7758static int si_dpm_hw_init(void *handle)
7759{
7760 int ret;
7761
7762 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7763
7764 if (!amdgpu_dpm)
7765 return 0;
7766
7767 mutex_lock(&adev->pm.mutex);
7768 si_dpm_setup_asic(adev);
7769 ret = si_dpm_enable(adev);
7770 if (ret)
7771 adev->pm.dpm_enabled = false;
7772 else
7773 adev->pm.dpm_enabled = true;
7774 mutex_unlock(&adev->pm.mutex);
7775
7776 return ret;
7777}
7778
7779static int si_dpm_hw_fini(void *handle)
7780{
7781 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7782
7783 if (adev->pm.dpm_enabled) {
7784 mutex_lock(&adev->pm.mutex);
7785 si_dpm_disable(adev);
7786 mutex_unlock(&adev->pm.mutex);
7787 }
7788
7789 return 0;
7790}
7791
7792static int si_dpm_suspend(void *handle)
7793{
7794 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7795
7796 if (adev->pm.dpm_enabled) {
7797 mutex_lock(&adev->pm.mutex);
7798 /* disable dpm */
7799 si_dpm_disable(adev);
7800 /* reset the power state */
7801 adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
7802 mutex_unlock(&adev->pm.mutex);
7803 }
7804 return 0;
7805}
7806
7807static int si_dpm_resume(void *handle)
7808{
7809 int ret;
7810 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7811
7812 if (adev->pm.dpm_enabled) {
7813 /* asic init will reset to the boot state */
7814 mutex_lock(&adev->pm.mutex);
7815 si_dpm_setup_asic(adev);
7816 ret = si_dpm_enable(adev);
7817 if (ret)
7818 adev->pm.dpm_enabled = false;
7819 else
7820 adev->pm.dpm_enabled = true;
7821 mutex_unlock(&adev->pm.mutex);
7822 if (adev->pm.dpm_enabled)
7823 amdgpu_pm_compute_clocks(adev);
7824 }
7825 return 0;
7826}
7827
7828static bool si_dpm_is_idle(void *handle)
7829{
7830 /* XXX */
7831 return true;
7832}
7833
7834static int si_dpm_wait_for_idle(void *handle)
7835{
7836 /* XXX */
7837 return 0;
7838}
7839
7840static int si_dpm_soft_reset(void *handle)
7841{
7842 return 0;
7843}
7844
7845static int si_dpm_set_clockgating_state(void *handle,
7846 enum amd_clockgating_state state)
7847{
7848 return 0;
7849}
7850
7851static int si_dpm_set_powergating_state(void *handle,
7852 enum amd_powergating_state state)
7853{
7854 return 0;
7855}
7856
7857/* get temperature in millidegrees */
7858static int si_dpm_get_temp(struct amdgpu_device *adev)
7859{
7860 u32 temp;
7861 int actual_temp = 0;
7862
7863 temp = (RREG32(CG_MULT_THERMAL_STATUS) & CTF_TEMP_MASK) >>
7864 CTF_TEMP_SHIFT;
7865
7866 if (temp & 0x200)
7867 actual_temp = 255;
7868 else
7869 actual_temp = temp & 0x1ff;
7870
7871 actual_temp = (actual_temp * 1000);
7872
7873 return actual_temp;
7874}
7875
7876static u32 si_dpm_get_sclk(struct amdgpu_device *adev, bool low)
7877{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7878 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7879 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7880
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7881 if (low)
7882 return requested_state->performance_levels[0].sclk;
7883 else
7884 return requested_state->performance_levels[requested_state->performance_level_count - 1].sclk;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7885}
7886
7887static u32 si_dpm_get_mclk(struct amdgpu_device *adev, bool low)
7888{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7889 struct evergreen_power_info *eg_pi = evergreen_get_pi(adev);
7890 struct si_ps *requested_state = si_get_ps(&eg_pi->requested_rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7891
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7892 if (low)
7893 return requested_state->performance_levels[0].mclk;
7894 else
7895 return requested_state->performance_levels[requested_state->performance_level_count - 1].mclk;
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7896}
7897
7898static void si_dpm_print_power_state(struct amdgpu_device *adev,
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7899 struct amdgpu_ps *rps)
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7900{
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7901 struct si_ps *ps = si_get_ps(rps);
7902 struct rv7xx_pl *pl;
7903 int i;
7904
7905 amdgpu_dpm_print_class_info(rps->class, rps->class2);
7906 amdgpu_dpm_print_cap_info(rps->caps);
7907 DRM_INFO("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
7908 for (i = 0; i < ps->performance_level_count; i++) {
7909 pl = &ps->performance_levels[i];
7910 if (adev->asic_type >= CHIP_TAHITI)
7911 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
Huang Rui84b77332016-08-31 13:23:18 +0800[diff] [blame]7912 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7913 else
7914 DRM_INFO("\t\tpower level %d sclk: %u mclk: %u vddc: %u vddci: %u\n",
Huang Rui84b77332016-08-31 13:23:18 +0800[diff] [blame]7915 i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
Tom St Denis77d318a2016-09-06 09:45:43 -0400[diff] [blame]7916 }
7917 amdgpu_dpm_print_ps_status(adev, rps);
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7918}
7919
7920static int si_dpm_early_init(void *handle)
7921{
7922
7923 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7924
7925 si_dpm_set_dpm_funcs(adev);
7926 si_dpm_set_irq_funcs(adev);
7927 return 0;
7928}
7929
Rex Zhu34117172016-10-14 19:39:52 +0800[diff] [blame]7930static inline bool si_are_power_levels_equal(const struct rv7xx_pl *si_cpl1,
7931 const struct rv7xx_pl *si_cpl2)
7932{
7933 return ((si_cpl1->mclk == si_cpl2->mclk) &&
7934 (si_cpl1->sclk == si_cpl2->sclk) &&
7935 (si_cpl1->pcie_gen == si_cpl2->pcie_gen) &&
7936 (si_cpl1->vddc == si_cpl2->vddc) &&
7937 (si_cpl1->vddci == si_cpl2->vddci));
7938}
7939
7940static int si_check_state_equal(struct amdgpu_device *adev,
7941 struct amdgpu_ps *cps,
7942 struct amdgpu_ps *rps,
7943 bool *equal)
7944{
7945 struct si_ps *si_cps;
7946 struct si_ps *si_rps;
7947 int i;
7948
7949 if (adev == NULL || cps == NULL || rps == NULL || equal == NULL)
7950 return -EINVAL;
7951
7952 si_cps = si_get_ps(cps);
7953 si_rps = si_get_ps(rps);
7954
7955 if (si_cps == NULL) {
7956 printk("si_cps is NULL\n");
7957 *equal = false;
7958 return 0;
7959 }
7960
7961 if (si_cps->performance_level_count != si_rps->performance_level_count) {
7962 *equal = false;
7963 return 0;
7964 }
7965
7966 for (i = 0; i < si_cps->performance_level_count; i++) {
7967 if (!si_are_power_levels_equal(&(si_cps->performance_levels[i]),
7968 &(si_rps->performance_levels[i]))) {
7969 *equal = false;
7970 return 0;
7971 }
7972 }
7973
7974 /* If all performance levels are the same try to use the UVD clocks to break the tie.*/
7975 *equal = ((cps->vclk == rps->vclk) && (cps->dclk == rps->dclk));
7976 *equal &= ((cps->evclk == rps->evclk) && (cps->ecclk == rps->ecclk));
7977
7978 return 0;
7979}
7980
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]7981
7982const struct amd_ip_funcs si_dpm_ip_funcs = {
7983 .name = "si_dpm",
7984 .early_init = si_dpm_early_init,
7985 .late_init = si_dpm_late_init,
7986 .sw_init = si_dpm_sw_init,
7987 .sw_fini = si_dpm_sw_fini,
7988 .hw_init = si_dpm_hw_init,
7989 .hw_fini = si_dpm_hw_fini,
7990 .suspend = si_dpm_suspend,
7991 .resume = si_dpm_resume,
7992 .is_idle = si_dpm_is_idle,
7993 .wait_for_idle = si_dpm_wait_for_idle,
7994 .soft_reset = si_dpm_soft_reset,
7995 .set_clockgating_state = si_dpm_set_clockgating_state,
7996 .set_powergating_state = si_dpm_set_powergating_state,
7997};
7998
7999static const struct amdgpu_dpm_funcs si_dpm_funcs = {
8000 .get_temperature = &si_dpm_get_temp,
8001 .pre_set_power_state = &si_dpm_pre_set_power_state,
8002 .set_power_state = &si_dpm_set_power_state,
8003 .post_set_power_state = &si_dpm_post_set_power_state,
8004 .display_configuration_changed = &si_dpm_display_configuration_changed,
8005 .get_sclk = &si_dpm_get_sclk,
8006 .get_mclk = &si_dpm_get_mclk,
8007 .print_power_state = &si_dpm_print_power_state,
8008 .debugfs_print_current_performance_level = &si_dpm_debugfs_print_current_performance_level,
8009 .force_performance_level = &si_dpm_force_performance_level,
8010 .vblank_too_short = &si_dpm_vblank_too_short,
8011 .set_fan_control_mode = &si_dpm_set_fan_control_mode,
8012 .get_fan_control_mode = &si_dpm_get_fan_control_mode,
8013 .set_fan_speed_percent = &si_dpm_set_fan_speed_percent,
8014 .get_fan_speed_percent = &si_dpm_get_fan_speed_percent,
Rex Zhu34117172016-10-14 19:39:52 +0800[diff] [blame]8015 .check_state_equal = &si_check_state_equal,
Alex Deucher825cc992016-10-07 12:38:04 -0400[diff] [blame]8016 .get_vce_clock_state = amdgpu_get_vce_clock_state,
Maruthi Bayyavarapu841686d2016-08-01 12:42:32 -0400[diff] [blame]8017};
8018
8019static void si_dpm_set_dpm_funcs(struct amdgpu_device *adev)
8020{
8021 if (adev->pm.funcs == NULL)
8022 adev->pm.funcs = &si_dpm_funcs;
8023}
8024
8025static const struct amdgpu_irq_src_funcs si_dpm_irq_funcs = {
8026 .set = si_dpm_set_interrupt_state,
8027 .process = si_dpm_process_interrupt,
8028};
8029
8030static void si_dpm_set_irq_funcs(struct amdgpu_device *adev)
8031{
8032 adev->pm.dpm.thermal.irq.num_types = AMDGPU_THERMAL_IRQ_LAST;
8033 adev->pm.dpm.thermal.irq.funcs = &si_dpm_irq_funcs;
8034}
8035