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Tony Lindgrenad1b6662012-05-08 17:23:33 -06001/*
2 * MSDI IP block reset
3 *
4 * Copyright (C) 2012 Texas Instruments, Inc.
5 * Paul Walmsley
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * version 2 as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19 * 02110-1301 USA
20 *
21 * XXX What about pad muxing?
22 */
23
24#include <linux/kernel.h>
Tony Lindgrenb955eef2012-06-26 03:14:20 -070025#include <linux/err.h>
Tony Lindgrenad1b6662012-05-08 17:23:33 -060026
Paul Walmsleyb13159a2012-10-29 20:57:44 -060027#include "prm.h"
Tony Lindgrenad1b6662012-05-08 17:23:33 -060028#include "common.h"
Tony Lindgrenb955eef2012-06-26 03:14:20 -070029#include "control.h"
Tony Lindgren2a296c82012-10-02 17:41:35 -070030#include "omap_hwmod.h"
Tony Lindgren25c7d492012-10-02 17:25:48 -070031#include "omap_device.h"
Tony Lindgren68f39e72012-10-15 12:09:43 -070032#include "mmc.h"
Tony Lindgrenad1b6662012-05-08 17:23:33 -060033
34/*
35 * MSDI_CON_OFFSET: offset in bytes of the MSDI IP block's CON register
36 * from the IP block's base address
37 */
38#define MSDI_CON_OFFSET 0x0c
39
40/* Register bitfields in the CON register */
41#define MSDI_CON_POW_MASK BIT(11)
42#define MSDI_CON_CLKD_MASK (0x3f << 0)
43#define MSDI_CON_CLKD_SHIFT 0
44
Tony Lindgrenad1b6662012-05-08 17:23:33 -060045/* MSDI_TARGET_RESET_CLKD: clock divisor to use throughout the reset */
46#define MSDI_TARGET_RESET_CLKD 0x3ff
47
48/**
49 * omap_msdi_reset - reset the MSDI IP block
50 * @oh: struct omap_hwmod *
51 *
52 * The MSDI IP block on OMAP2420 has to have both the POW and CLKD
53 * fields set inside its CON register for a reset to complete
54 * successfully. This is not documented in the TRM. For CLKD, we use
55 * the value that results in the lowest possible clock rate, to attempt
56 * to avoid disturbing any cards.
57 */
58int omap_msdi_reset(struct omap_hwmod *oh)
59{
60 u16 v = 0;
61 int c = 0;
62
63 /* Write to the SOFTRESET bit */
64 omap_hwmod_softreset(oh);
65
66 /* Enable the MSDI core and internal clock */
67 v |= MSDI_CON_POW_MASK;
68 v |= MSDI_TARGET_RESET_CLKD << MSDI_CON_CLKD_SHIFT;
69 omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
70
71 /* Poll on RESETDONE bit */
72 omap_test_timeout((omap_hwmod_read(oh, oh->class->sysc->syss_offs)
73 & SYSS_RESETDONE_MASK),
74 MAX_MODULE_SOFTRESET_WAIT, c);
75
76 if (c == MAX_MODULE_SOFTRESET_WAIT)
Joe Perches3d0cb732014-09-13 11:31:16 -070077 pr_warn("%s: %s: softreset failed (waited %d usec)\n",
78 __func__, oh->name, MAX_MODULE_SOFTRESET_WAIT);
Tony Lindgrenad1b6662012-05-08 17:23:33 -060079 else
80 pr_debug("%s: %s: softreset in %d usec\n", __func__,
81 oh->name, c);
82
83 /* Disable the MSDI internal clock */
84 v &= ~MSDI_CON_CLKD_MASK;
85 omap_hwmod_write(v, oh, MSDI_CON_OFFSET);
86
87 return 0;
88}