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gerrit-public.fairphone.software / kernel / msm-5.4 / 1f58af304cce9e4a25b62b3619e69c586203c8ca / . / drivers / gpu / drm / i915 / gvt / handlers.c
blob: 548aedfbd40272d65b3ccd511a47a7c6a85c4aa2 [file] [log] [blame]
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]1/*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39#include "i915_drv.h"
Zhenyu Wangfeddf6e2016-10-20 17:15:03 +0800[diff] [blame]40#include "gvt.h"
41#include "i915_pvinfo.h"
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]42
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]43/* XXX FIXME i915 has changed PP_XXX definition */
44#define PCH_PP_STATUS _MMIO(0xc7200)
45#define PCH_PP_CONTROL _MMIO(0xc7204)
46#define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47#define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48#define PCH_PP_DIVISOR _MMIO(0xc7210)
49
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]50/* Register contains RO bits */
51#define F_RO (1 << 0)
52/* Register contains graphics address */
53#define F_GMADR (1 << 1)
54/* Mode mask registers with high 16 bits as the mask bits */
55#define F_MODE_MASK (1 << 2)
56/* This reg can be accessed by GPU commands */
57#define F_CMD_ACCESS (1 << 3)
58/* This reg has been accessed by a VM */
59#define F_ACCESSED (1 << 4)
60/* This reg has been accessed through GPU commands */
61#define F_CMD_ACCESSED (1 << 5)
62/* This reg could be accessed by unaligned address */
63#define F_UNALIGN (1 << 6)
64
65unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
66{
67 if (IS_BROADWELL(gvt->dev_priv))
68 return D_BDW;
69 else if (IS_SKYLAKE(gvt->dev_priv))
70 return D_SKL;
71
72 return 0;
73}
74
75bool intel_gvt_match_device(struct intel_gvt *gvt,
76 unsigned long device)
77{
78 return intel_gvt_get_device_type(gvt) & device;
79}
80
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]81static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
82 void *p_data, unsigned int bytes)
83{
84 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
85}
86
87static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
88 void *p_data, unsigned int bytes)
89{
90 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
91}
92
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]93static int new_mmio_info(struct intel_gvt *gvt,
94 u32 offset, u32 flags, u32 size,
95 u32 addr_mask, u32 ro_mask, u32 device,
Nicolas Iooss3e70c5d2016-12-26 14:52:23 +0100[diff] [blame]96 int (*read)(struct intel_vgpu *, unsigned int, void *, unsigned int),
97 int (*write)(struct intel_vgpu *, unsigned int, void *, unsigned int))
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]98{
99 struct intel_gvt_mmio_info *info, *p;
100 u32 start, end, i;
101
102 if (!intel_gvt_match_device(gvt, device))
103 return 0;
104
105 if (WARN_ON(!IS_ALIGNED(offset, 4)))
106 return -EINVAL;
107
108 start = offset;
109 end = offset + size;
110
111 for (i = start; i < end; i += 4) {
112 info = kzalloc(sizeof(*info), GFP_KERNEL);
113 if (!info)
114 return -ENOMEM;
115
116 info->offset = i;
117 p = intel_gvt_find_mmio_info(gvt, info->offset);
118 if (p)
119 gvt_err("dup mmio definition offset %x\n",
120 info->offset);
121 info->size = size;
122 info->length = (i + 4) < end ? 4 : (end - i);
123 info->addr_mask = addr_mask;
124 info->device = device;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]125 info->read = read ? read : intel_vgpu_default_mmio_read;
126 info->write = write ? write : intel_vgpu_default_mmio_write;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]127 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
128 INIT_HLIST_NODE(&info->node);
129 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
130 }
131 return 0;
132}
133
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]134static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg)
135{
Zhenyu Wang0fac21e2016-10-20 13:30:33 +0800[diff] [blame]136 enum intel_engine_id id;
137 struct intel_engine_cs *engine;
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]138
139 reg &= ~GENMASK(11, 0);
Zhenyu Wang0fac21e2016-10-20 13:30:33 +0800[diff] [blame]140 for_each_engine(engine, gvt->dev_priv, id) {
141 if (engine->mmio_base == reg)
142 return id;
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]143 }
144 return -1;
145}
146
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]147#define offset_to_fence_num(offset) \
148 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
149
150#define fence_num_to_offset(num) \
151 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
152
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]153
154static void enter_failsafe_mode(struct intel_vgpu *vgpu, int reason)
155{
156 switch (reason) {
157 case GVT_FAILSAFE_UNSUPPORTED_GUEST:
158 pr_err("Detected your guest driver doesn't support GVT-g.\n");
159 break;
Min Hea33fc7a2017-02-17 16:42:38 +0800[diff] [blame]160 case GVT_FAILSAFE_INSUFFICIENT_RESOURCE:
161 pr_err("Graphics resource is not enough for the guest\n");
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]162 default:
163 break;
164 }
165 pr_err("Now vgpu %d will enter failsafe mode.\n", vgpu->id);
166 vgpu->failsafe = true;
167}
168
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]169static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
170 unsigned int fence_num, void *p_data, unsigned int bytes)
171{
172 if (fence_num >= vgpu_fence_sz(vgpu)) {
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]173
174 /* When guest access oob fence regs without access
175 * pv_info first, we treat guest not supporting GVT,
176 * and we will let vgpu enter failsafe mode.
177 */
Zhao, Xindad1be3712017-02-17 14:38:33 +0800[diff] [blame]178 if (!vgpu->pv_notified)
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]179 enter_failsafe_mode(vgpu,
180 GVT_FAILSAFE_UNSUPPORTED_GUEST);
Zhao, Xindad1be3712017-02-17 14:38:33 +0800[diff] [blame]181
182 if (!vgpu->mmio.disable_warn_untrack) {
183 gvt_err("vgpu%d: found oob fence register access\n",
184 vgpu->id);
185 gvt_err("vgpu%d: total fence %d, access fence %d\n",
186 vgpu->id, vgpu_fence_sz(vgpu),
187 fence_num);
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]188 }
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]189 memset(p_data, 0, bytes);
Zhao, Xindad1be3712017-02-17 14:38:33 +0800[diff] [blame]190 return -EINVAL;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]191 }
192 return 0;
193}
194
195static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
196 void *p_data, unsigned int bytes)
197{
198 int ret;
199
200 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
201 p_data, bytes);
202 if (ret)
203 return ret;
204 read_vreg(vgpu, off, p_data, bytes);
205 return 0;
206}
207
208static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
209 void *p_data, unsigned int bytes)
210{
211 unsigned int fence_num = offset_to_fence_num(off);
212 int ret;
213
214 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
215 if (ret)
216 return ret;
217 write_vreg(vgpu, off, p_data, bytes);
218
219 intel_vgpu_write_fence(vgpu, fence_num,
220 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
221 return 0;
222}
223
224#define CALC_MODE_MASK_REG(old, new) \
225 (((new) & GENMASK(31, 16)) \
226 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
227 | ((new) & ((new) >> 16))))
228
229static int mul_force_wake_write(struct intel_vgpu *vgpu,
230 unsigned int offset, void *p_data, unsigned int bytes)
231{
232 u32 old, new;
233 uint32_t ack_reg_offset;
234
235 old = vgpu_vreg(vgpu, offset);
236 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
237
238 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
239 switch (offset) {
240 case FORCEWAKE_RENDER_GEN9_REG:
241 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
242 break;
243 case FORCEWAKE_BLITTER_GEN9_REG:
244 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
245 break;
246 case FORCEWAKE_MEDIA_GEN9_REG:
247 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
248 break;
249 default:
250 /*should not hit here*/
251 gvt_err("invalid forcewake offset 0x%x\n", offset);
Changbin Du39762ad2016-12-27 13:25:06 +0800[diff] [blame]252 return -EINVAL;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]253 }
254 } else {
255 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
256 }
257
258 vgpu_vreg(vgpu, offset) = new;
259 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
260 return 0;
261}
262
263static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
Changbin Duc34eaa82017-01-13 11:16:03 +0800[diff] [blame]264 void *p_data, unsigned int bytes)
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]265{
Changbin Duc34eaa82017-01-13 11:16:03 +0800[diff] [blame]266 unsigned int engine_mask = 0;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]267 u32 data;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]268
Ping Gao40d24282016-10-26 09:38:50 +0800[diff] [blame]269 write_vreg(vgpu, offset, p_data, bytes);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]270 data = vgpu_vreg(vgpu, offset);
271
272 if (data & GEN6_GRDOM_FULL) {
273 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
Changbin Duc34eaa82017-01-13 11:16:03 +0800[diff] [blame]274 engine_mask = ALL_ENGINES;
275 } else {
276 if (data & GEN6_GRDOM_RENDER) {
277 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
278 engine_mask |= (1 << RCS);
279 }
280 if (data & GEN6_GRDOM_MEDIA) {
281 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
282 engine_mask |= (1 << VCS);
283 }
284 if (data & GEN6_GRDOM_BLT) {
285 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
286 engine_mask |= (1 << BCS);
287 }
288 if (data & GEN6_GRDOM_VECS) {
289 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
290 engine_mask |= (1 << VECS);
291 }
292 if (data & GEN8_GRDOM_MEDIA2) {
293 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
294 if (HAS_BSD2(vgpu->gvt->dev_priv))
295 engine_mask |= (1 << VCS2);
296 }
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]297 }
Changbin Duc34eaa82017-01-13 11:16:03 +0800[diff] [blame]298
299 intel_gvt_reset_vgpu_locked(vgpu, false, engine_mask);
300
301 return 0;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]302}
303
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]304static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
305 void *p_data, unsigned int bytes)
306{
307 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
308}
309
310static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
311 void *p_data, unsigned int bytes)
312{
313 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
314}
315
316static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
317 unsigned int offset, void *p_data, unsigned int bytes)
318{
319 write_vreg(vgpu, offset, p_data, bytes);
320
321 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
322 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON;
323 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
324 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
325 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
326
327 } else
328 vgpu_vreg(vgpu, PCH_PP_STATUS) &=
329 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
330 | PP_CYCLE_DELAY_ACTIVE);
331 return 0;
332}
333
334static int transconf_mmio_write(struct intel_vgpu *vgpu,
335 unsigned int offset, void *p_data, unsigned int bytes)
336{
337 write_vreg(vgpu, offset, p_data, bytes);
338
339 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
340 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
341 else
342 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
343 return 0;
344}
345
346static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
347 void *p_data, unsigned int bytes)
348{
349 write_vreg(vgpu, offset, p_data, bytes);
350
351 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
352 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
353 else
354 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
355
356 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
357 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
358 else
359 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
360
361 return 0;
362}
363
364static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
365 void *p_data, unsigned int bytes)
366{
367 *(u32 *)p_data = (1 << 17);
368 return 0;
369}
370
371static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset,
372 void *p_data, unsigned int bytes)
373{
374 *(u32 *)p_data = 3;
375 return 0;
376}
377
378static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset,
379 void *p_data, unsigned int bytes)
380{
381 *(u32 *)p_data = (0x2f << 16);
382 return 0;
383}
384
385static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
386 void *p_data, unsigned int bytes)
387{
388 u32 data;
389
390 write_vreg(vgpu, offset, p_data, bytes);
391 data = vgpu_vreg(vgpu, offset);
392
393 if (data & PIPECONF_ENABLE)
394 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
395 else
396 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
397 intel_gvt_check_vblank_emulation(vgpu->gvt);
398 return 0;
399}
400
Zhao Yane6cedfe2017-02-21 10:38:53 +0800[diff] [blame]401/* ascendingly sorted */
402static i915_reg_t force_nonpriv_white_list[] = {
403 GEN9_CS_DEBUG_MODE1, //_MMIO(0x20ec)
404 GEN9_CTX_PREEMPT_REG,//_MMIO(0x2248)
405 GEN8_CS_CHICKEN1,//_MMIO(0x2580)
406 _MMIO(0x2690),
407 _MMIO(0x2694),
408 _MMIO(0x2698),
409 _MMIO(0x4de0),
410 _MMIO(0x4de4),
411 _MMIO(0x4dfc),
412 GEN7_COMMON_SLICE_CHICKEN1,//_MMIO(0x7010)
413 _MMIO(0x7014),
414 HDC_CHICKEN0,//_MMIO(0x7300)
415 GEN8_HDC_CHICKEN1,//_MMIO(0x7304)
416 _MMIO(0x7700),
417 _MMIO(0x7704),
418 _MMIO(0x7708),
419 _MMIO(0x770c),
420 _MMIO(0xb110),
421 GEN8_L3SQCREG4,//_MMIO(0xb118)
422 _MMIO(0xe100),
423 _MMIO(0xe18c),
424 _MMIO(0xe48c),
425 _MMIO(0xe5f4),
426};
427
428/* a simple bsearch */
429static inline bool in_whitelist(unsigned int reg)
430{
431 int left = 0, right = ARRAY_SIZE(force_nonpriv_white_list);
432 i915_reg_t *array = force_nonpriv_white_list;
433
434 while (left < right) {
435 int mid = (left + right)/2;
436
437 if (reg > array[mid].reg)
438 left = mid + 1;
439 else if (reg < array[mid].reg)
440 right = mid;
441 else
442 return true;
443 }
444 return false;
445}
446
447static int force_nonpriv_write(struct intel_vgpu *vgpu,
448 unsigned int offset, void *p_data, unsigned int bytes)
449{
450 u32 reg_nonpriv = *(u32 *)p_data;
451 int ret = -EINVAL;
452
453 if ((bytes != 4) || ((offset & (bytes - 1)) != 0)) {
454 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV offset %x(%dB)\n",
455 vgpu->id, offset, bytes);
456 return ret;
457 }
458
459 if (in_whitelist(reg_nonpriv)) {
460 ret = intel_vgpu_default_mmio_write(vgpu, offset, p_data,
461 bytes);
462 } else {
463 gvt_err("vgpu(%d) Invalid FORCE_NONPRIV write %x\n",
464 vgpu->id, reg_nonpriv);
465 }
466 return ret;
467}
468
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]469static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
470 void *p_data, unsigned int bytes)
471{
472 write_vreg(vgpu, offset, p_data, bytes);
473
474 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
475 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
476 } else {
477 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
478 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
479 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E))
480 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
481 }
482 return 0;
483}
484
485static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
486 unsigned int offset, void *p_data, unsigned int bytes)
487{
488 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
489 return 0;
490}
491
492#define FDI_LINK_TRAIN_PATTERN1 0
493#define FDI_LINK_TRAIN_PATTERN2 1
494
495static int fdi_auto_training_started(struct intel_vgpu *vgpu)
496{
497 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E));
498 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
499 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E));
500
501 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
502 (rx_ctl & FDI_RX_ENABLE) &&
503 (rx_ctl & FDI_AUTO_TRAINING) &&
504 (tx_ctl & DP_TP_CTL_ENABLE) &&
505 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
506 return 1;
507 else
508 return 0;
509}
510
511static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
512 enum pipe pipe, unsigned int train_pattern)
513{
514 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
515 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
516 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
517 unsigned int fdi_iir_check_bits;
518
519 fdi_rx_imr = FDI_RX_IMR(pipe);
520 fdi_tx_ctl = FDI_TX_CTL(pipe);
521 fdi_rx_ctl = FDI_RX_CTL(pipe);
522
523 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
524 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
525 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
526 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
527 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
528 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
529 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
530 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
531 } else {
532 gvt_err("Invalid train pattern %d\n", train_pattern);
533 return -EINVAL;
534 }
535
536 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
537 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
538
539 /* If imr bit has been masked */
540 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
541 return 0;
542
543 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
544 == fdi_tx_check_bits)
545 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
546 == fdi_rx_check_bits))
547 return 1;
548 else
549 return 0;
550}
551
552#define INVALID_INDEX (~0U)
553
554static unsigned int calc_index(unsigned int offset, unsigned int start,
555 unsigned int next, unsigned int end, i915_reg_t i915_end)
556{
557 unsigned int range = next - start;
558
559 if (!end)
560 end = i915_mmio_reg_offset(i915_end);
561 if (offset < start || offset > end)
562 return INVALID_INDEX;
563 offset -= start;
564 return offset / range;
565}
566
567#define FDI_RX_CTL_TO_PIPE(offset) \
568 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
569
570#define FDI_TX_CTL_TO_PIPE(offset) \
571 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
572
573#define FDI_RX_IMR_TO_PIPE(offset) \
574 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
575
576static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
577 unsigned int offset, void *p_data, unsigned int bytes)
578{
579 i915_reg_t fdi_rx_iir;
580 unsigned int index;
581 int ret;
582
583 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
584 index = FDI_RX_CTL_TO_PIPE(offset);
585 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
586 index = FDI_TX_CTL_TO_PIPE(offset);
587 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
588 index = FDI_RX_IMR_TO_PIPE(offset);
589 else {
590 gvt_err("Unsupport registers %x\n", offset);
591 return -EINVAL;
592 }
593
594 write_vreg(vgpu, offset, p_data, bytes);
595
596 fdi_rx_iir = FDI_RX_IIR(index);
597
598 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
599 if (ret < 0)
600 return ret;
601 if (ret)
602 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
603
604 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
605 if (ret < 0)
606 return ret;
607 if (ret)
608 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
609
610 if (offset == _FDI_RXA_CTL)
611 if (fdi_auto_training_started(vgpu))
612 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |=
613 DP_TP_STATUS_AUTOTRAIN_DONE;
614 return 0;
615}
616
617#define DP_TP_CTL_TO_PORT(offset) \
618 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
619
620static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
621 void *p_data, unsigned int bytes)
622{
623 i915_reg_t status_reg;
624 unsigned int index;
625 u32 data;
626
627 write_vreg(vgpu, offset, p_data, bytes);
628
629 index = DP_TP_CTL_TO_PORT(offset);
630 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
631 if (data == 0x2) {
632 status_reg = DP_TP_STATUS(index);
633 vgpu_vreg(vgpu, status_reg) |= (1 << 25);
634 }
635 return 0;
636}
637
638static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
639 unsigned int offset, void *p_data, unsigned int bytes)
640{
641 u32 reg_val;
642 u32 sticky_mask;
643
644 reg_val = *((u32 *)p_data);
645 sticky_mask = GENMASK(27, 26) | (1 << 24);
646
647 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
648 (vgpu_vreg(vgpu, offset) & sticky_mask);
649 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
650 return 0;
651}
652
653static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
654 unsigned int offset, void *p_data, unsigned int bytes)
655{
656 u32 data;
657
658 write_vreg(vgpu, offset, p_data, bytes);
659 data = vgpu_vreg(vgpu, offset);
660
661 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
662 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
663 return 0;
664}
665
666static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
667 unsigned int offset, void *p_data, unsigned int bytes)
668{
669 u32 data;
670
671 write_vreg(vgpu, offset, p_data, bytes);
672 data = vgpu_vreg(vgpu, offset);
673
674 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
675 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
676 else
677 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
678 return 0;
679}
680
681#define DSPSURF_TO_PIPE(offset) \
682 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
683
684static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
685 void *p_data, unsigned int bytes)
686{
687 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
688 unsigned int index = DSPSURF_TO_PIPE(offset);
689 i915_reg_t surflive_reg = DSPSURFLIVE(index);
690 int flip_event[] = {
691 [PIPE_A] = PRIMARY_A_FLIP_DONE,
692 [PIPE_B] = PRIMARY_B_FLIP_DONE,
693 [PIPE_C] = PRIMARY_C_FLIP_DONE,
694 };
695
696 write_vreg(vgpu, offset, p_data, bytes);
697 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
698
699 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
700 return 0;
701}
702
703#define SPRSURF_TO_PIPE(offset) \
704 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
705
706static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
707 void *p_data, unsigned int bytes)
708{
709 unsigned int index = SPRSURF_TO_PIPE(offset);
710 i915_reg_t surflive_reg = SPRSURFLIVE(index);
711 int flip_event[] = {
712 [PIPE_A] = SPRITE_A_FLIP_DONE,
713 [PIPE_B] = SPRITE_B_FLIP_DONE,
714 [PIPE_C] = SPRITE_C_FLIP_DONE,
715 };
716
717 write_vreg(vgpu, offset, p_data, bytes);
718 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
719
720 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
721 return 0;
722}
723
724static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
725 unsigned int reg)
726{
727 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
728 enum intel_gvt_event_type event;
729
730 if (reg == _DPA_AUX_CH_CTL)
731 event = AUX_CHANNEL_A;
732 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
733 event = AUX_CHANNEL_B;
734 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
735 event = AUX_CHANNEL_C;
736 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
737 event = AUX_CHANNEL_D;
738 else {
739 WARN_ON(true);
740 return -EINVAL;
741 }
742
743 intel_vgpu_trigger_virtual_event(vgpu, event);
744 return 0;
745}
746
747static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
748 unsigned int reg, int len, bool data_valid)
749{
750 /* mark transaction done */
751 value |= DP_AUX_CH_CTL_DONE;
752 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
753 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
754
755 if (data_valid)
756 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
757 else
758 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
759
760 /* message size */
761 value &= ~(0xf << 20);
762 value |= (len << 20);
763 vgpu_vreg(vgpu, reg) = value;
764
765 if (value & DP_AUX_CH_CTL_INTERRUPT)
766 return trigger_aux_channel_interrupt(vgpu, reg);
767 return 0;
768}
769
770static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
771 uint8_t t)
772{
773 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
774 /* training pattern 1 for CR */
775 /* set LANE0_CR_DONE, LANE1_CR_DONE */
776 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
777 /* set LANE2_CR_DONE, LANE3_CR_DONE */
778 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
779 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
780 DPCD_TRAINING_PATTERN_2) {
781 /* training pattern 2 for EQ */
782 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
783 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
784 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
785 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
786 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
787 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
788 /* set INTERLANE_ALIGN_DONE */
789 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
790 DPCD_INTERLANE_ALIGN_DONE;
791 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
792 DPCD_LINK_TRAINING_DISABLED) {
793 /* finish link training */
794 /* set sink status as synchronized */
795 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
796 }
797}
798
799#define _REG_HSW_DP_AUX_CH_CTL(dp) \
800 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
801
802#define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
803
804#define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
805
806#define dpy_is_valid_port(port) \
807 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
808
809static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
810 unsigned int offset, void *p_data, unsigned int bytes)
811{
812 struct intel_vgpu_display *display = &vgpu->display;
813 int msg, addr, ctrl, op, len;
814 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
815 struct intel_vgpu_dpcd_data *dpcd = NULL;
816 struct intel_vgpu_port *port = NULL;
817 u32 data;
818
819 if (!dpy_is_valid_port(port_index)) {
820 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id);
821 return 0;
822 }
823
824 write_vreg(vgpu, offset, p_data, bytes);
825 data = vgpu_vreg(vgpu, offset);
826
827 if (IS_SKYLAKE(vgpu->gvt->dev_priv) &&
828 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
829 /* SKL DPB/C/D aux ctl register changed */
830 return 0;
831 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
832 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
833 /* write to the data registers */
834 return 0;
835 }
836
837 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
838 /* just want to clear the sticky bits */
839 vgpu_vreg(vgpu, offset) = 0;
840 return 0;
841 }
842
843 port = &display->ports[port_index];
844 dpcd = port->dpcd;
845
846 /* read out message from DATA1 register */
847 msg = vgpu_vreg(vgpu, offset + 4);
848 addr = (msg >> 8) & 0xffff;
849 ctrl = (msg >> 24) & 0xff;
850 len = msg & 0xff;
851 op = ctrl >> 4;
852
853 if (op == GVT_AUX_NATIVE_WRITE) {
854 int t;
855 uint8_t buf[16];
856
857 if ((addr + len + 1) >= DPCD_SIZE) {
858 /*
859 * Write request exceeds what we supported,
860 * DCPD spec: When a Source Device is writing a DPCD
861 * address not supported by the Sink Device, the Sink
862 * Device shall reply with AUX NACK and “M” equal to
863 * zero.
864 */
865
866 /* NAK the write */
867 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
868 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
869 return 0;
870 }
871
872 /*
873 * Write request format: (command + address) occupies
874 * 3 bytes, followed by (len + 1) bytes of data.
875 */
876 if (WARN_ON((len + 4) > AUX_BURST_SIZE))
877 return -EINVAL;
878
879 /* unpack data from vreg to buf */
880 for (t = 0; t < 4; t++) {
881 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
882
883 buf[t * 4] = (r >> 24) & 0xff;
884 buf[t * 4 + 1] = (r >> 16) & 0xff;
885 buf[t * 4 + 2] = (r >> 8) & 0xff;
886 buf[t * 4 + 3] = r & 0xff;
887 }
888
889 /* write to virtual DPCD */
890 if (dpcd && dpcd->data_valid) {
891 for (t = 0; t <= len; t++) {
892 int p = addr + t;
893
894 dpcd->data[p] = buf[t];
895 /* check for link training */
896 if (p == DPCD_TRAINING_PATTERN_SET)
897 dp_aux_ch_ctl_link_training(dpcd,
898 buf[t]);
899 }
900 }
901
902 /* ACK the write */
903 vgpu_vreg(vgpu, offset + 4) = 0;
904 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
905 dpcd && dpcd->data_valid);
906 return 0;
907 }
908
909 if (op == GVT_AUX_NATIVE_READ) {
910 int idx, i, ret = 0;
911
912 if ((addr + len + 1) >= DPCD_SIZE) {
913 /*
914 * read request exceeds what we supported
915 * DPCD spec: A Sink Device receiving a Native AUX CH
916 * read request for an unsupported DPCD address must
917 * reply with an AUX ACK and read data set equal to
918 * zero instead of replying with AUX NACK.
919 */
920
921 /* ACK the READ*/
922 vgpu_vreg(vgpu, offset + 4) = 0;
923 vgpu_vreg(vgpu, offset + 8) = 0;
924 vgpu_vreg(vgpu, offset + 12) = 0;
925 vgpu_vreg(vgpu, offset + 16) = 0;
926 vgpu_vreg(vgpu, offset + 20) = 0;
927
928 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
929 true);
930 return 0;
931 }
932
933 for (idx = 1; idx <= 5; idx++) {
934 /* clear the data registers */
935 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
936 }
937
938 /*
939 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
940 */
941 if (WARN_ON((len + 2) > AUX_BURST_SIZE))
942 return -EINVAL;
943
944 /* read from virtual DPCD to vreg */
945 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
946 if (dpcd && dpcd->data_valid) {
947 for (i = 1; i <= (len + 1); i++) {
948 int t;
949
950 t = dpcd->data[addr + i - 1];
951 t <<= (24 - 8 * (i % 4));
952 ret |= t;
953
954 if ((i % 4 == 3) || (i == (len + 1))) {
955 vgpu_vreg(vgpu, offset +
956 (i / 4 + 1) * 4) = ret;
957 ret = 0;
958 }
959 }
960 }
961 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
962 dpcd && dpcd->data_valid);
963 return 0;
964 }
965
966 /* i2c transaction starts */
967 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
968
969 if (data & DP_AUX_CH_CTL_INTERRUPT)
970 trigger_aux_channel_interrupt(vgpu, offset);
971 return 0;
972}
973
974static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
975 void *p_data, unsigned int bytes)
976{
977 bool vga_disable;
978
979 write_vreg(vgpu, offset, p_data, bytes);
980 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
981
982 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
983 vga_disable ? "Disable" : "Enable");
984 return 0;
985}
986
987static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
988 unsigned int sbi_offset)
989{
990 struct intel_vgpu_display *display = &vgpu->display;
991 int num = display->sbi.number;
992 int i;
993
994 for (i = 0; i < num; ++i)
995 if (display->sbi.registers[i].offset == sbi_offset)
996 break;
997
998 if (i == num)
999 return 0;
1000
1001 return display->sbi.registers[i].value;
1002}
1003
1004static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
1005 unsigned int offset, u32 value)
1006{
1007 struct intel_vgpu_display *display = &vgpu->display;
1008 int num = display->sbi.number;
1009 int i;
1010
1011 for (i = 0; i < num; ++i) {
1012 if (display->sbi.registers[i].offset == offset)
1013 break;
1014 }
1015
1016 if (i == num) {
1017 if (num == SBI_REG_MAX) {
1018 gvt_err("vgpu%d: SBI caching meets maximum limits\n",
1019 vgpu->id);
1020 return;
1021 }
1022 display->sbi.number++;
1023 }
1024
1025 display->sbi.registers[i].offset = offset;
1026 display->sbi.registers[i].value = value;
1027}
1028
1029static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1030 void *p_data, unsigned int bytes)
1031{
1032 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1033 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
1034 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1035 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1036 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
1037 sbi_offset);
1038 }
1039 read_vreg(vgpu, offset, p_data, bytes);
1040 return 0;
1041}
1042
Nicolas Iooss3e70c5d2016-12-26 14:52:23 +0100[diff] [blame]1043static int sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1044 void *p_data, unsigned int bytes)
1045{
1046 u32 data;
1047
1048 write_vreg(vgpu, offset, p_data, bytes);
1049 data = vgpu_vreg(vgpu, offset);
1050
1051 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
1052 data |= SBI_READY;
1053
1054 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
1055 data |= SBI_RESPONSE_SUCCESS;
1056
1057 vgpu_vreg(vgpu, offset) = data;
1058
1059 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
1060 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
1061 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
1062 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
1063
1064 write_virtual_sbi_register(vgpu, sbi_offset,
1065 vgpu_vreg(vgpu, SBI_DATA));
1066 }
1067 return 0;
1068}
1069
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1070#define _vgtif_reg(x) \
1071 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
1072
1073static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
1074 void *p_data, unsigned int bytes)
1075{
1076 bool invalid_read = false;
1077
1078 read_vreg(vgpu, offset, p_data, bytes);
1079
1080 switch (offset) {
1081 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1082 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1083 invalid_read = true;
1084 break;
1085 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1086 _vgtif_reg(avail_rs.fence_num):
1087 if (offset + bytes >
1088 _vgtif_reg(avail_rs.fence_num) + 4)
1089 invalid_read = true;
1090 break;
1091 case 0x78010: /* vgt_caps */
1092 case 0x7881c:
1093 break;
1094 default:
1095 invalid_read = true;
1096 break;
1097 }
1098 if (invalid_read)
1099 gvt_err("invalid pvinfo read: [%x:%x] = %x\n",
1100 offset, bytes, *(u32 *)p_data);
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]1101 vgpu->pv_notified = true;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1102 return 0;
1103}
1104
1105static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1106{
1107 int ret = 0;
1108
1109 switch (notification) {
1110 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1111 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3);
1112 break;
1113 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1114 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3);
1115 break;
1116 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1117 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4);
1118 break;
1119 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1120 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4);
1121 break;
1122 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1123 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1124 case 1: /* Remove this in guest driver. */
1125 break;
1126 default:
1127 gvt_err("Invalid PV notification %d\n", notification);
1128 }
1129 return ret;
1130}
1131
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1132static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1133{
1134 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1135 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1136 char *env[3] = {NULL, NULL, NULL};
1137 char vmid_str[20];
1138 char display_ready_str[20];
1139
Takashi Iwaid8e9b2b2017-02-20 14:58:25 +0100[diff] [blame]1140 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d", ready);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1141 env[0] = display_ready_str;
1142
1143 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1144 env[1] = vmid_str;
1145
1146 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1147}
1148
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1149static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1150 void *p_data, unsigned int bytes)
1151{
1152 u32 data;
1153 int ret;
1154
1155 write_vreg(vgpu, offset, p_data, bytes);
1156 data = vgpu_vreg(vgpu, offset);
1157
1158 switch (offset) {
1159 case _vgtif_reg(display_ready):
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1160 send_display_ready_uevent(vgpu, data ? 1 : 0);
1161 break;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1162 case _vgtif_reg(g2v_notify):
1163 ret = handle_g2v_notification(vgpu, data);
1164 break;
1165 /* add xhot and yhot to handled list to avoid error log */
1166 case 0x78830:
1167 case 0x78834:
1168 case _vgtif_reg(pdp[0].lo):
1169 case _vgtif_reg(pdp[0].hi):
1170 case _vgtif_reg(pdp[1].lo):
1171 case _vgtif_reg(pdp[1].hi):
1172 case _vgtif_reg(pdp[2].lo):
1173 case _vgtif_reg(pdp[2].hi):
1174 case _vgtif_reg(pdp[3].lo):
1175 case _vgtif_reg(pdp[3].hi):
1176 case _vgtif_reg(execlist_context_descriptor_lo):
1177 case _vgtif_reg(execlist_context_descriptor_hi):
1178 break;
Min Hea33fc7a2017-02-17 16:42:38 +0800[diff] [blame]1179 case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
1180 enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
1181 break;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1182 default:
1183 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n",
1184 offset, bytes, data);
1185 break;
1186 }
1187 return 0;
1188}
1189
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1190static int pf_write(struct intel_vgpu *vgpu,
1191 unsigned int offset, void *p_data, unsigned int bytes)
1192{
1193 u32 val = *(u32 *)p_data;
1194
1195 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1196 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1197 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1198 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1199 vgpu->id);
1200 return 0;
1201 }
1202
1203 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1204}
1205
1206static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1207 unsigned int offset, void *p_data, unsigned int bytes)
1208{
1209 write_vreg(vgpu, offset, p_data, bytes);
1210
1211 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST)
1212 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED;
1213 else
1214 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED;
1215 return 0;
1216}
1217
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1218static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1219 unsigned int offset, void *p_data, unsigned int bytes)
1220{
1221 write_vreg(vgpu, offset, p_data, bytes);
1222
1223 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1224 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1225 return 0;
1226}
1227
1228static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1229 void *p_data, unsigned int bytes)
1230{
Ping Gao5f399f12016-10-27 14:46:40 +0800[diff] [blame]1231 u32 mode;
1232
1233 write_vreg(vgpu, offset, p_data, bytes);
1234 mode = vgpu_vreg(vgpu, offset);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1235
1236 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1237 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n",
1238 vgpu->id);
1239 return 0;
1240 }
1241
1242 return 0;
1243}
1244
1245static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1246 void *p_data, unsigned int bytes)
1247{
1248 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1249 u32 trtte = *(u32 *)p_data;
1250
1251 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1252 WARN(1, "VM(%d): Use physical address for TRTT!\n",
1253 vgpu->id);
1254 return -EINVAL;
1255 }
1256 write_vreg(vgpu, offset, p_data, bytes);
1257 /* TRTTE is not per-context */
1258 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
1259
1260 return 0;
1261}
1262
1263static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1264 void *p_data, unsigned int bytes)
1265{
1266 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1267 u32 val = *(u32 *)p_data;
1268
1269 if (val & 1) {
1270 /* unblock hw logic */
1271 I915_WRITE(_MMIO(offset), val);
1272 }
1273 write_vreg(vgpu, offset, p_data, bytes);
1274 return 0;
1275}
1276
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1277static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1278 void *p_data, unsigned int bytes)
1279{
1280 u32 v = 0;
1281
1282 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1283 v |= (1 << 0);
1284
1285 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1286 v |= (1 << 8);
1287
1288 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1289 v |= (1 << 16);
1290
1291 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1292 v |= (1 << 24);
1293
1294 vgpu_vreg(vgpu, offset) = v;
1295
1296 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1297}
1298
1299static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1300 void *p_data, unsigned int bytes)
1301{
1302 u32 value = *(u32 *)p_data;
1303 u32 cmd = value & 0xff;
1304 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA);
1305
1306 switch (cmd) {
Weinan Li8bcd7c12017-02-24 17:07:38 +0800[diff] [blame]1307 case GEN9_PCODE_READ_MEM_LATENCY:
1308 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
1309 /**
1310 * "Read memory latency" command on gen9.
1311 * Below memory latency values are read
1312 * from skylake platform.
1313 */
1314 if (!*data0)
1315 *data0 = 0x1e1a1100;
1316 else
1317 *data0 = 0x61514b3d;
1318 }
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1319 break;
Weinan Lid8a355b2017-02-22 11:03:24 +0800[diff] [blame]1320 case SKL_PCODE_CDCLK_CONTROL:
Weinan Li8bcd7c12017-02-24 17:07:38 +0800[diff] [blame]1321 if (IS_SKYLAKE(vgpu->gvt->dev_priv))
1322 *data0 = SKL_CDCLK_READY_FOR_CHANGE;
Weinan Lid8a355b2017-02-22 11:03:24 +0800[diff] [blame]1323 break;
Weinan Li8bcd7c12017-02-24 17:07:38 +0800[diff] [blame]1324 case GEN6_PCODE_READ_RC6VIDS:
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1325 *data0 |= 0x1;
1326 break;
1327 }
1328
1329 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1330 vgpu->id, value, *data0);
Weinan Lid8a355b2017-02-22 11:03:24 +0800[diff] [blame]1331 /**
1332 * PCODE_READY clear means ready for pcode read/write,
1333 * PCODE_ERROR_MASK clear means no error happened. In GVT-g we
1334 * always emulate as pcode read/write success and ready for access
1335 * anytime, since we don't touch real physical registers here.
1336 */
1337 value &= ~(GEN6_PCODE_READY | GEN6_PCODE_ERROR_MASK);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1338 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1339}
1340
1341static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1342 unsigned int offset, void *p_data, unsigned int bytes)
1343{
1344 u32 v = *(u32 *)p_data;
1345
1346 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1347 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1348 v |= (v >> 1);
1349
1350 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1351}
1352
1353static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1354 void *p_data, unsigned int bytes)
1355{
1356 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1357 i915_reg_t reg = {.reg = offset};
1358
1359 switch (offset) {
1360 case 0x4ddc:
1361 vgpu_vreg(vgpu, offset) = 0x8000003c;
Ping Gaod4362222016-10-28 10:21:45 +0800[diff] [blame]1362 /* WaCompressedResourceSamplerPbeMediaNewHashMode:skl */
Jani Nikula955c1dd2016-11-16 12:13:59 +0200[diff] [blame]1363 I915_WRITE(reg, vgpu_vreg(vgpu, offset));
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1364 break;
1365 case 0x42080:
1366 vgpu_vreg(vgpu, offset) = 0x8000;
Ping Gaod4362222016-10-28 10:21:45 +0800[diff] [blame]1367 /* WaCompressedResourceDisplayNewHashMode:skl */
Jani Nikula955c1dd2016-11-16 12:13:59 +0200[diff] [blame]1368 I915_WRITE(reg, vgpu_vreg(vgpu, offset));
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1369 break;
1370 default:
1371 return -EINVAL;
1372 }
1373
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1374 return 0;
1375}
1376
1377static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1378 void *p_data, unsigned int bytes)
1379{
1380 u32 v = *(u32 *)p_data;
1381
1382 /* other bits are MBZ. */
1383 v &= (1 << 31) | (1 << 30);
1384 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1385
1386 vgpu_vreg(vgpu, offset) = v;
1387
1388 return 0;
1389}
1390
1391static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu,
1392 unsigned int offset, void *p_data, unsigned int bytes)
1393{
1394 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1395
1396 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1397 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1398}
1399
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1400static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1401 void *p_data, unsigned int bytes)
1402{
1403 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
1404 struct intel_vgpu_execlist *execlist;
1405 u32 data = *(u32 *)p_data;
Bing Niu6fb50822016-10-31 17:35:12 +0800[diff] [blame]1406 int ret = 0;
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1407
Zhenyu Wang0fac21e2016-10-20 13:30:33 +0800[diff] [blame]1408 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1))
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1409 return -EINVAL;
1410
1411 execlist = &vgpu->execlist[ring_id];
1412
1413 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data;
Bing Niu6fb50822016-10-31 17:35:12 +0800[diff] [blame]1414 if (execlist->elsp_dwords.index == 3) {
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1415 ret = intel_vgpu_submit_execlist(vgpu, ring_id);
Bing Niu6fb50822016-10-31 17:35:12 +0800[diff] [blame]1416 if(ret)
1417 gvt_err("fail submit workload on ring %d\n", ring_id);
1418 }
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1419
1420 ++execlist->elsp_dwords.index;
1421 execlist->elsp_dwords.index &= 0x3;
Bing Niu6fb50822016-10-31 17:35:12 +0800[diff] [blame]1422 return ret;
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]1423}
1424
Zhi Wang4b639602016-05-01 17:09:58 -0400[diff] [blame]1425static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1426 void *p_data, unsigned int bytes)
1427{
1428 u32 data = *(u32 *)p_data;
1429 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
1430 bool enable_execlist;
1431
1432 write_vreg(vgpu, offset, p_data, bytes);
Min Hefd64be62017-02-17 15:02:36 +0800[diff] [blame]1433
1434 /* when PPGTT mode enabled, we will check if guest has called
1435 * pvinfo, if not, we will treat this guest as non-gvtg-aware
1436 * guest, and stop emulating its cfg space, mmio, gtt, etc.
1437 */
1438 if (((data & _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE)) ||
1439 (data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)))
1440 && !vgpu->pv_notified) {
1441 enter_failsafe_mode(vgpu, GVT_FAILSAFE_UNSUPPORTED_GUEST);
1442 return 0;
1443 }
Zhi Wang4b639602016-05-01 17:09:58 -0400[diff] [blame]1444 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1445 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1446 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1447
1448 gvt_dbg_core("EXECLIST %s on ring %d\n",
1449 (enable_execlist ? "enabling" : "disabling"),
1450 ring_id);
1451
1452 if (enable_execlist)
1453 intel_vgpu_start_schedule(vgpu);
1454 }
1455 return 0;
1456}
1457
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]1458static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1459 unsigned int offset, void *p_data, unsigned int bytes)
1460{
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]1461 unsigned int id = 0;
1462
Ping Gaof24940e2016-10-27 14:37:41 +0800[diff] [blame]1463 write_vreg(vgpu, offset, p_data, bytes);
Ping Gao4f3f1ae2016-11-10 15:27:20 +0800[diff] [blame]1464 vgpu_vreg(vgpu, offset) = 0;
Ping Gaof24940e2016-10-27 14:37:41 +0800[diff] [blame]1465
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]1466 switch (offset) {
1467 case 0x4260:
1468 id = RCS;
1469 break;
1470 case 0x4264:
1471 id = VCS;
1472 break;
1473 case 0x4268:
1474 id = VCS2;
1475 break;
1476 case 0x426c:
1477 id = BCS;
1478 break;
1479 case 0x4270:
1480 id = VECS;
1481 break;
1482 default:
Changbin Dua1201052016-12-27 13:24:52 +0800[diff] [blame]1483 return -EINVAL;
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]1484 }
1485 set_bit(id, (void *)vgpu->tlb_handle_pending);
1486
Changbin Dua1201052016-12-27 13:24:52 +0800[diff] [blame]1487 return 0;
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]1488}
1489
Du, Changbin2fb39fa2016-11-04 12:21:37 +0800[diff] [blame]1490static int ring_reset_ctl_write(struct intel_vgpu *vgpu,
1491 unsigned int offset, void *p_data, unsigned int bytes)
1492{
1493 u32 data;
1494
1495 write_vreg(vgpu, offset, p_data, bytes);
1496 data = vgpu_vreg(vgpu, offset);
1497
1498 if (data & _MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET))
1499 data |= RESET_CTL_READY_TO_RESET;
1500 else if (data & _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET))
1501 data &= ~RESET_CTL_READY_TO_RESET;
1502
1503 vgpu_vreg(vgpu, offset) = data;
1504 return 0;
1505}
1506
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]1507#define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1508 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \
1509 f, s, am, rm, d, r, w); \
1510 if (ret) \
1511 return ret; \
1512} while (0)
1513
1514#define MMIO_D(reg, d) \
1515 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1516
1517#define MMIO_DH(reg, d, r, w) \
1518 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1519
1520#define MMIO_DFH(reg, d, f, r, w) \
1521 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1522
1523#define MMIO_GM(reg, d, r, w) \
1524 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1525
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1526#define MMIO_GM_RDR(reg, d, r, w) \
1527 MMIO_F(reg, 4, F_GMADR | F_CMD_ACCESS, 0xFFFFF000, 0, d, r, w)
1528
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]1529#define MMIO_RO(reg, d, f, rm, r, w) \
1530 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1531
1532#define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1533 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1534 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1535 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1536 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1537} while (0)
1538
1539#define MMIO_RING_D(prefix, d) \
1540 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1541
1542#define MMIO_RING_DFH(prefix, d, f, r, w) \
1543 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1544
1545#define MMIO_RING_GM(prefix, d, r, w) \
1546 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1547
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1548#define MMIO_RING_GM_RDR(prefix, d, r, w) \
1549 MMIO_RING_F(prefix, 4, F_GMADR | F_CMD_ACCESS, 0xFFFF0000, 0, d, r, w)
1550
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]1551#define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1552 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1553
1554static int init_generic_mmio_info(struct intel_gvt *gvt)
1555{
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1556 struct drm_i915_private *dev_priv = gvt->dev_priv;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]1557 int ret;
1558
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1559 MMIO_RING_DFH(RING_IMR, D_ALL, F_CMD_ACCESS, NULL,
1560 intel_vgpu_reg_imr_handler);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1561
1562 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1563 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1564 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1565 MMIO_D(SDEISR, D_ALL);
1566
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1567 MMIO_RING_DFH(RING_HWSTAM, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1568
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1569 MMIO_GM_RDR(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1570 MMIO_GM_RDR(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1571 MMIO_GM_RDR(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1572 MMIO_GM_RDR(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1573
1574#define RING_REG(base) (base + 0x28)
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1575 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1576#undef RING_REG
1577
1578#define RING_REG(base) (base + 0x134)
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1579 MMIO_RING_DFH(RING_REG, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1580#undef RING_REG
1581
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1582 MMIO_GM_RDR(0x2148, D_ALL, NULL, NULL);
1583 MMIO_GM_RDR(CCID, D_ALL, NULL, NULL);
1584 MMIO_GM_RDR(0x12198, D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1585 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1586
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1587 MMIO_RING_DFH(RING_TAIL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1588 MMIO_RING_DFH(RING_HEAD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1589 MMIO_RING_DFH(RING_CTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
1590 MMIO_RING_DFH(RING_ACTHD, D_ALL, F_CMD_ACCESS, NULL, NULL);
1591 MMIO_RING_GM_RDR(RING_START, D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1592
1593 /* RING MODE */
1594#define RING_REG(base) (base + 0x29c)
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1595 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL,
1596 ring_mode_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1597#undef RING_REG
1598
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1599 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1600 NULL, NULL);
Pei Zhang41bfab32017-02-24 16:03:28 +0800[diff] [blame]1601 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1602 NULL, NULL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1603 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1604 ring_timestamp_mmio_read, NULL);
1605 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1606 ring_timestamp_mmio_read, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1607
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1608 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1609 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1610 NULL, NULL);
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]1611 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1612 MMIO_DFH(CACHE_MODE_0, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1613 MMIO_DFH(0x2124, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1614
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1615 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1616 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1617 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1618 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1619 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
1620 MMIO_DFH(GAM_ECOCHK, D_ALL, F_CMD_ACCESS, NULL, NULL);
1621 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS,
1622 NULL, NULL);
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]1623 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]1624 MMIO_DFH(0x9030, D_ALL, F_CMD_ACCESS, NULL, NULL);
1625 MMIO_DFH(0x20a0, D_ALL, F_CMD_ACCESS, NULL, NULL);
1626 MMIO_DFH(0x2420, D_ALL, F_CMD_ACCESS, NULL, NULL);
1627 MMIO_DFH(0x2430, D_ALL, F_CMD_ACCESS, NULL, NULL);
1628 MMIO_DFH(0x2434, D_ALL, F_CMD_ACCESS, NULL, NULL);
1629 MMIO_DFH(0x2438, D_ALL, F_CMD_ACCESS, NULL, NULL);
1630 MMIO_DFH(0x243c, D_ALL, F_CMD_ACCESS, NULL, NULL);
1631 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]1632 MMIO_DFH(HALF_SLICE_CHICKEN3, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Pei Zhang187447a2017-02-21 21:58:14 +0800[diff] [blame]1633 MMIO_DFH(GEN7_HALF_SLICE_CHICKEN1, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1634
1635 /* display */
1636 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1637 MMIO_D(0x602a0, D_ALL);
1638
1639 MMIO_D(0x65050, D_ALL);
1640 MMIO_D(0x650b4, D_ALL);
1641
1642 MMIO_D(0xc4040, D_ALL);
1643 MMIO_D(DERRMR, D_ALL);
1644
1645 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1646 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1647 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1648 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1649
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1650 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1651 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1652 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1653 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1654
1655 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1656 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1657 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1658 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1659
1660 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1661 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1662 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1663 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1664
1665 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
1666 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
1667 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
1668 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
1669
1670 MMIO_D(CURCNTR(PIPE_A), D_ALL);
1671 MMIO_D(CURCNTR(PIPE_B), D_ALL);
1672 MMIO_D(CURCNTR(PIPE_C), D_ALL);
1673
1674 MMIO_D(CURPOS(PIPE_A), D_ALL);
1675 MMIO_D(CURPOS(PIPE_B), D_ALL);
1676 MMIO_D(CURPOS(PIPE_C), D_ALL);
1677
1678 MMIO_D(CURBASE(PIPE_A), D_ALL);
1679 MMIO_D(CURBASE(PIPE_B), D_ALL);
1680 MMIO_D(CURBASE(PIPE_C), D_ALL);
1681
1682 MMIO_D(0x700ac, D_ALL);
1683 MMIO_D(0x710ac, D_ALL);
1684 MMIO_D(0x720ac, D_ALL);
1685
1686 MMIO_D(0x70090, D_ALL);
1687 MMIO_D(0x70094, D_ALL);
1688 MMIO_D(0x70098, D_ALL);
1689 MMIO_D(0x7009c, D_ALL);
1690
1691 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1692 MMIO_D(DSPADDR(PIPE_A), D_ALL);
1693 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
1694 MMIO_D(DSPPOS(PIPE_A), D_ALL);
1695 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1696 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1697 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
1698 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
1699
1700 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
1701 MMIO_D(DSPADDR(PIPE_B), D_ALL);
1702 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
1703 MMIO_D(DSPPOS(PIPE_B), D_ALL);
1704 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1705 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1706 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
1707 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
1708
1709 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
1710 MMIO_D(DSPADDR(PIPE_C), D_ALL);
1711 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
1712 MMIO_D(DSPPOS(PIPE_C), D_ALL);
1713 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1714 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1715 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
1716 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
1717
1718 MMIO_D(SPRCTL(PIPE_A), D_ALL);
1719 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
1720 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
1721 MMIO_D(SPRPOS(PIPE_A), D_ALL);
1722 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
1723 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
1724 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1725 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1726 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
1727 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
1728 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
1729 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
1730
1731 MMIO_D(SPRCTL(PIPE_B), D_ALL);
1732 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
1733 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
1734 MMIO_D(SPRPOS(PIPE_B), D_ALL);
1735 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
1736 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
1737 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1738 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1739 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
1740 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
1741 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
1742 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
1743
1744 MMIO_D(SPRCTL(PIPE_C), D_ALL);
1745 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
1746 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
1747 MMIO_D(SPRPOS(PIPE_C), D_ALL);
1748 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
1749 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
1750 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1751 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1752 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
1753 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
1754 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
1755 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
1756
1757 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
1758 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
1759 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
1760
1761 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
1762 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
1763 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
1764 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
1765 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
1766 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
1767 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
1768 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
1769 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
1770
1771 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
1772 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
1773 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
1774 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
1775 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
1776 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
1777 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
1778 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
1779 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
1780
1781 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
1782 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
1783 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
1784 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
1785 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
1786 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
1787 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
1788 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
1789 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
1790
1791 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
1792 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
1793 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
1794 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
1795 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
1796 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
1797 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
1798 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
1799
1800 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
1801 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
1802 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
1803 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
1804 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
1805 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
1806 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
1807 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
1808
1809 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
1810 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
1811 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
1812 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
1813 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
1814 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
1815 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
1816 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
1817
1818 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
1819 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
1820 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
1821 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
1822 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
1823 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
1824 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
1825 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
1826
1827 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
1828 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
1829 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
1830 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
1831 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
1832 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
1833 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
1834 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
1835
1836 MMIO_D(PF_CTL(PIPE_A), D_ALL);
1837 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
1838 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
1839 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
1840 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
1841
1842 MMIO_D(PF_CTL(PIPE_B), D_ALL);
1843 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
1844 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
1845 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
1846 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
1847
1848 MMIO_D(PF_CTL(PIPE_C), D_ALL);
1849 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
1850 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
1851 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
1852 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
1853
1854 MMIO_D(WM0_PIPEA_ILK, D_ALL);
1855 MMIO_D(WM0_PIPEB_ILK, D_ALL);
1856 MMIO_D(WM0_PIPEC_IVB, D_ALL);
1857 MMIO_D(WM1_LP_ILK, D_ALL);
1858 MMIO_D(WM2_LP_ILK, D_ALL);
1859 MMIO_D(WM3_LP_ILK, D_ALL);
1860 MMIO_D(WM1S_LP_ILK, D_ALL);
1861 MMIO_D(WM2S_LP_IVB, D_ALL);
1862 MMIO_D(WM3S_LP_IVB, D_ALL);
1863
1864 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
1865 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
1866 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
1867 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
1868
1869 MMIO_D(0x48268, D_ALL);
1870
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1871 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
1872 gmbus_mmio_write);
1873 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1874 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL);
1875
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1876 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1877 dp_aux_ch_ctl_mmio_write);
1878 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1879 dp_aux_ch_ctl_mmio_write);
1880 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1881 dp_aux_ch_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1882
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1883 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1884
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1885 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write);
1886 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1887
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1888 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
1889 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
1890 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
1891 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1892 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1893 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1894 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1895 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1896 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1897
1898 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL);
1899 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL);
1900 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL);
1901 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL);
1902 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL);
1903 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL);
1904 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL);
1905
1906 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL);
1907 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL);
1908 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL);
1909 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL);
1910 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL);
1911 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL);
1912 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL);
1913
1914 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL);
1915 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL);
1916 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL);
1917 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL);
1918 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL);
1919 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL);
1920 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL);
1921 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL);
1922
1923 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
1924 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
1925 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
1926
1927 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
1928 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
1929 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
1930
1931 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
1932 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
1933 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
1934
1935 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
1936 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
1937 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
1938
1939 MMIO_D(_FDI_RXA_MISC, D_ALL);
1940 MMIO_D(_FDI_RXB_MISC, D_ALL);
1941 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL);
1942 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL);
1943 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL);
1944 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL);
1945
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1946 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1947 MMIO_D(PCH_PP_DIVISOR, D_ALL);
1948 MMIO_D(PCH_PP_STATUS, D_ALL);
1949 MMIO_D(PCH_LVDS, D_ALL);
1950 MMIO_D(_PCH_DPLL_A, D_ALL);
1951 MMIO_D(_PCH_DPLL_B, D_ALL);
1952 MMIO_D(_PCH_FPA0, D_ALL);
1953 MMIO_D(_PCH_FPA1, D_ALL);
1954 MMIO_D(_PCH_FPB0, D_ALL);
1955 MMIO_D(_PCH_FPB1, D_ALL);
1956 MMIO_D(PCH_DREF_CONTROL, D_ALL);
1957 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
1958 MMIO_D(PCH_DPLL_SEL, D_ALL);
1959
1960 MMIO_D(0x61208, D_ALL);
1961 MMIO_D(0x6120c, D_ALL);
1962 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
1963 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
1964
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1965 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL);
1966 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL);
1967 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL);
1968 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL);
1969 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL);
1970 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1971
1972 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
1973 PORTA_HOTPLUG_STATUS_MASK
1974 | PORTB_HOTPLUG_STATUS_MASK
1975 | PORTC_HOTPLUG_STATUS_MASK
1976 | PORTD_HOTPLUG_STATUS_MASK,
1977 NULL, NULL);
1978
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1979 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1980 MMIO_D(FUSE_STRAP, D_ALL);
1981 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
1982
1983 MMIO_D(DISP_ARB_CTL, D_ALL);
1984 MMIO_D(DISP_ARB_CTL2, D_ALL);
1985
1986 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
1987 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
1988 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
1989
1990 MMIO_D(SOUTH_CHICKEN1, D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]1991 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]1992 MMIO_D(_TRANSA_CHICKEN1, D_ALL);
1993 MMIO_D(_TRANSB_CHICKEN1, D_ALL);
1994 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
1995 MMIO_D(_TRANSA_CHICKEN2, D_ALL);
1996 MMIO_D(_TRANSB_CHICKEN2, D_ALL);
1997
1998 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
1999 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
2000 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
2001 MMIO_D(ILK_DPFC_STATUS, D_ALL);
2002 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
2003 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
2004 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
2005
2006 MMIO_D(IPS_CTL, D_ALL);
2007
2008 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
2009 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
2010 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
2011 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
2012 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
2013 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
2014 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
2015 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
2016 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
2017 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
2018 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
2019 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
2020 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
2021
2022 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
2023 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
2024 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
2025 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
2026 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
2027 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
2028 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
2029 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
2030 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
2031 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
2032 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
2033 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
2034 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
2035
2036 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
2037 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
2038 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
2039 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
2040 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
2041 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
2042 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
2043 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
2044 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
2045 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
2046 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
2047 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
2048 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
2049
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2050 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
2051 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
2052 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2053
2054 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
2055 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
2056 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2057
2058 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
2059 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
2060 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
2061
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2062 MMIO_D(0x60110, D_ALL);
2063 MMIO_D(0x61110, D_ALL);
2064 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2065 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2066 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
2067 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2068 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2069 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2070 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2071 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2072 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
2073
2074 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
2075 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
2076 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
2077 MMIO_D(SPLL_CTL, D_ALL);
2078 MMIO_D(_WRPLL_CTL1, D_ALL);
2079 MMIO_D(_WRPLL_CTL2, D_ALL);
2080 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
2081 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
2082 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
2083 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
2084 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
2085 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
2086 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
2087 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
2088
2089 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
2090 MMIO_D(0x46508, D_ALL);
2091
2092 MMIO_D(0x49080, D_ALL);
2093 MMIO_D(0x49180, D_ALL);
2094 MMIO_D(0x49280, D_ALL);
2095
2096 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2097 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2098 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
2099
2100 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
2101 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
2102 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
2103
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2104 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
2105 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
2106 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
2107
2108 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
2109 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
2110 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
2111
2112 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
2113 MMIO_D(SBI_ADDR, D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2114 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
2115 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2116 MMIO_D(PIXCLK_GATE, D_ALL);
2117
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2118 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL,
2119 dp_aux_ch_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2120
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2121 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2122 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2123 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2124 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
2125 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2126
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2127 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
2128 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
2129 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
2130 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
2131 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2132
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2133 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
2134 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
2135 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
2136 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
2137 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2138
2139 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2140 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2141 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2142 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2143 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2144
2145 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2146 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2147
2148 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL);
2149 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL);
2150 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL);
2151 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL);
2152
2153 MMIO_D(_TRANSA_MSA_MISC, D_ALL);
2154 MMIO_D(_TRANSB_MSA_MISC, D_ALL);
2155 MMIO_D(_TRANSC_MSA_MISC, D_ALL);
2156 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL);
2157
2158 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2159 MMIO_D(FORCEWAKE_ACK, D_ALL);
2160 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2161 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2162 MMIO_DFH(GTFIFODBG, D_ALL, F_CMD_ACCESS, NULL, NULL);
2163 MMIO_DFH(GTFIFOCTL, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2164 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2165 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL);
2166 MMIO_D(ECOBUS, D_ALL);
2167 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2168 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2169 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2170 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2171 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2172 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2173 MMIO_D(GEN6_RPSTAT1, D_ALL);
2174 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2175 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2176 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2177 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2178 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2179 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2180 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2181 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2182 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2183 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2184 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2185 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2186 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2187 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2188 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2189 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2190 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2191 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2192 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2193 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2194 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2195 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2196 MMIO_D(GEN6_PMINTRMSK, D_ALL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2197 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2198 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2199 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2200 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2201 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2202 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2203
2204 MMIO_D(RSTDBYCTL, D_ALL);
2205
2206 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2207 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2208 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2209 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2210
2211 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL);
2212
2213 MMIO_D(TILECTL, D_ALL);
2214
2215 MMIO_D(GEN6_UCGCTL1, D_ALL);
2216 MMIO_D(GEN6_UCGCTL2, D_ALL);
2217
2218 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2219
Weinan Li8bcd7c12017-02-24 17:07:38 +0800[diff] [blame]2220 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_BDW);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2221 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2222 MMIO_D(0x13812c, D_ALL);
2223 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2224 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2225 MMIO_D(HSW_IDICR, D_ALL);
2226 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2227
2228 MMIO_D(0x3c, D_ALL);
2229 MMIO_D(0x860, D_ALL);
2230 MMIO_D(ECOSKPD, D_ALL);
2231 MMIO_D(0x121d0, D_ALL);
2232 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2233 MMIO_D(0x41d0, D_ALL);
2234 MMIO_D(GAC_ECO_BITS, D_ALL);
2235 MMIO_D(0x6200, D_ALL);
2236 MMIO_D(0x6204, D_ALL);
2237 MMIO_D(0x6208, D_ALL);
2238 MMIO_D(0x7118, D_ALL);
2239 MMIO_D(0x7180, D_ALL);
2240 MMIO_D(0x7408, D_ALL);
2241 MMIO_D(0x7c00, D_ALL);
2242 MMIO_D(GEN6_MBCTL, D_ALL);
2243 MMIO_D(0x911c, D_ALL);
2244 MMIO_D(0x9120, D_ALL);
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]2245 MMIO_DFH(GEN7_UCGCTL4, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2246
2247 MMIO_D(GAB_CTL, D_ALL);
2248 MMIO_D(0x48800, D_ALL);
2249 MMIO_D(0xce044, D_ALL);
2250 MMIO_D(0xe6500, D_ALL);
2251 MMIO_D(0xe6504, D_ALL);
2252 MMIO_D(0xe6600, D_ALL);
2253 MMIO_D(0xe6604, D_ALL);
2254 MMIO_D(0xe6700, D_ALL);
2255 MMIO_D(0xe6704, D_ALL);
2256 MMIO_D(0xe6800, D_ALL);
2257 MMIO_D(0xe6804, D_ALL);
2258 MMIO_D(PCH_GMBUS4, D_ALL);
2259 MMIO_D(PCH_GMBUS5, D_ALL);
2260
2261 MMIO_D(0x902c, D_ALL);
2262 MMIO_D(0xec008, D_ALL);
2263 MMIO_D(0xec00c, D_ALL);
2264 MMIO_D(0xec008 + 0x18, D_ALL);
2265 MMIO_D(0xec00c + 0x18, D_ALL);
2266 MMIO_D(0xec008 + 0x18 * 2, D_ALL);
2267 MMIO_D(0xec00c + 0x18 * 2, D_ALL);
2268 MMIO_D(0xec008 + 0x18 * 3, D_ALL);
2269 MMIO_D(0xec00c + 0x18 * 3, D_ALL);
2270 MMIO_D(0xec408, D_ALL);
2271 MMIO_D(0xec40c, D_ALL);
2272 MMIO_D(0xec408 + 0x18, D_ALL);
2273 MMIO_D(0xec40c + 0x18, D_ALL);
2274 MMIO_D(0xec408 + 0x18 * 2, D_ALL);
2275 MMIO_D(0xec40c + 0x18 * 2, D_ALL);
2276 MMIO_D(0xec408 + 0x18 * 3, D_ALL);
2277 MMIO_D(0xec40c + 0x18 * 3, D_ALL);
2278 MMIO_D(0xfc810, D_ALL);
2279 MMIO_D(0xfc81c, D_ALL);
2280 MMIO_D(0xfc828, D_ALL);
2281 MMIO_D(0xfc834, D_ALL);
2282 MMIO_D(0xfcc00, D_ALL);
2283 MMIO_D(0xfcc0c, D_ALL);
2284 MMIO_D(0xfcc18, D_ALL);
2285 MMIO_D(0xfcc24, D_ALL);
2286 MMIO_D(0xfd000, D_ALL);
2287 MMIO_D(0xfd00c, D_ALL);
2288 MMIO_D(0xfd018, D_ALL);
2289 MMIO_D(0xfd024, D_ALL);
2290 MMIO_D(0xfd034, D_ALL);
2291
2292 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2293 MMIO_D(0x2054, D_ALL);
2294 MMIO_D(0x12054, D_ALL);
2295 MMIO_D(0x22054, D_ALL);
2296 MMIO_D(0x1a054, D_ALL);
2297
2298 MMIO_D(0x44070, D_ALL);
Pei Zhang41bfab32017-02-24 16:03:28 +0800[diff] [blame]2299 MMIO_DFH(0x215c, D_HSW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2300 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2301 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2302 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2303 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2304
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2305 MMIO_F(0x2290, 8, F_CMD_ACCESS, 0, 0, D_HSW_PLUS, NULL, NULL);
2306 MMIO_DFH(GEN7_OACONTROL, D_HSW, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2307 MMIO_D(0x2b00, D_BDW_PLUS);
2308 MMIO_D(0x2360, D_BDW_PLUS);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2309 MMIO_F(0x5200, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2310 MMIO_F(0x5240, 32, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2311 MMIO_F(0x5280, 16, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2312
2313 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2314 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2315 MMIO_DFH(BCS_SWCTRL, D_ALL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2316
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2317 MMIO_F(HS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2318 MMIO_F(DS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2319 MMIO_F(IA_VERTICES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2320 MMIO_F(IA_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2321 MMIO_F(VS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2322 MMIO_F(GS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2323 MMIO_F(GS_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2324 MMIO_F(CL_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2325 MMIO_F(CL_PRIMITIVES_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2326 MMIO_F(PS_INVOCATION_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
2327 MMIO_F(PS_DEPTH_COUNT, 8, F_CMD_ACCESS, 0, 0, D_ALL, NULL, NULL);
Zhi Wang17865712016-05-01 19:02:37 -0400[diff] [blame]2328 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2329 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2330 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2331 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2332 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2333 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2334
Zhao Yan9112caa2017-02-28 15:40:10 +0800[diff] [blame]2335 MMIO_DFH(ARB_MODE, D_ALL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2336 MMIO_RING_GM_RDR(RING_BBADDR, D_ALL, NULL, NULL);
2337 MMIO_DFH(0x2220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2338 MMIO_DFH(0x12220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2339 MMIO_DFH(0x22220, D_ALL, F_CMD_ACCESS, NULL, NULL);
2340 MMIO_RING_DFH(RING_SYNC_1, D_ALL, F_CMD_ACCESS, NULL, NULL);
2341 MMIO_RING_DFH(RING_SYNC_0, D_ALL, F_CMD_ACCESS, NULL, NULL);
2342 MMIO_DFH(0x22178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2343 MMIO_DFH(0x1a178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2344 MMIO_DFH(0x1a17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2345 MMIO_DFH(0x2217c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2346 return 0;
2347}
2348
2349static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2350{
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2351 struct drm_i915_private *dev_priv = gvt->dev_priv;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2352 int ret;
2353
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2354 MMIO_DFH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS, NULL,
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2355 intel_vgpu_reg_imr_handler);
2356
2357 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2358 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2359 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2360 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2361
2362 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2363 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2364 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2365 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2366
2367 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2368 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2369 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2370 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2371
2372 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2373 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2374 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2375 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2376
2377 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2378 intel_vgpu_reg_imr_handler);
2379 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2380 intel_vgpu_reg_ier_handler);
2381 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2382 intel_vgpu_reg_iir_handler);
2383 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2384
2385 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2386 intel_vgpu_reg_imr_handler);
2387 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2388 intel_vgpu_reg_ier_handler);
2389 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2390 intel_vgpu_reg_iir_handler);
2391 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2392
2393 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2394 intel_vgpu_reg_imr_handler);
2395 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2396 intel_vgpu_reg_ier_handler);
2397 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2398 intel_vgpu_reg_iir_handler);
2399 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2400
2401 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2402 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2403 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2404 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2405
2406 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2407 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2408 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2409 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2410
2411 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2412 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2413 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2414 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2415
2416 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2417 intel_vgpu_reg_master_irq_handler);
2418
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2419 MMIO_DFH(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2420 F_CMD_ACCESS, NULL, NULL);
2421 MMIO_DFH(0x1c134, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2422
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2423 MMIO_DFH(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2424 NULL, NULL);
2425 MMIO_DFH(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2426 F_CMD_ACCESS, NULL, NULL);
2427 MMIO_GM_RDR(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
2428 MMIO_DFH(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2429 NULL, NULL);
2430 MMIO_DFH(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2431 F_CMD_ACCESS, NULL, NULL);
2432 MMIO_DFH(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2433 F_CMD_ACCESS, NULL, NULL);
2434 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL,
2435 ring_mode_mmio_write);
2436 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2437 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2438 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS,
2439 F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2440 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2441 ring_timestamp_mmio_read, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2442
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2443 MMIO_RING_DFH(RING_ACTHD_UDW, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2444
Du, Changbin2fb39fa2016-11-04 12:21:37 +0800[diff] [blame]2445#define RING_REG(base) (base + 0xd0)
2446 MMIO_RING_F(RING_REG, 4, F_RO, 0,
2447 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2448 ring_reset_ctl_write);
2449 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0,
2450 ~_MASKED_BIT_ENABLE(RESET_CTL_REQUEST_RESET), D_BDW_PLUS, NULL,
2451 ring_reset_ctl_write);
2452#undef RING_REG
2453
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2454#define RING_REG(base) (base + 0x230)
Zhi Wang28c4c6c2016-05-01 05:22:47 -0400[diff] [blame]2455 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2456 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2457#undef RING_REG
2458
2459#define RING_REG(base) (base + 0x234)
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2460 MMIO_RING_F(RING_REG, 8, F_RO | F_CMD_ACCESS, 0, ~0, D_BDW_PLUS,
2461 NULL, NULL);
2462 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO | F_CMD_ACCESS, 0,
2463 ~0LL, D_BDW_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2464#undef RING_REG
2465
2466#define RING_REG(base) (base + 0x244)
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2467 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2468 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2469 NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2470#undef RING_REG
2471
2472#define RING_REG(base) (base + 0x370)
2473 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2474 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS,
2475 NULL, NULL);
2476#undef RING_REG
2477
2478#define RING_REG(base) (base + 0x3a0)
2479 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2480 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2481#undef RING_REG
2482
2483 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2484 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2485 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2486 MMIO_D(0x1c1d0, D_BDW_PLUS);
2487 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2488 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2489 MMIO_D(0x1c054, D_BDW_PLUS);
2490
Weinan Li8bcd7c12017-02-24 17:07:38 +0800[diff] [blame]2491 MMIO_DH(GEN6_PCODE_MAILBOX, D_BDW_PLUS, NULL, mailbox_write);
2492
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2493 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2494 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2495
2496 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2497
2498#define RING_REG(base) (base + 0x270)
2499 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2500 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2501#undef RING_REG
2502
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2503 MMIO_RING_GM_RDR(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
2504 MMIO_GM_RDR(RING_HWS_PGA(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2505
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]2506 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2507
Zhao Yan593e59b2017-02-20 15:51:13 +0800[diff] [blame]2508 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW_PLUS);
2509 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW_PLUS);
2510 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW_PLUS);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2511
2512 MMIO_D(WM_MISC, D_BDW);
2513 MMIO_D(BDW_EDP_PSR_BASE, D_BDW);
2514
2515 MMIO_D(0x66c00, D_BDW_PLUS);
2516 MMIO_D(0x66c04, D_BDW_PLUS);
2517
2518 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2519
2520 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2521 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2522 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2523
Zhao Yan593e59b2017-02-20 15:51:13 +0800[diff] [blame]2524 MMIO_D(0xfdc, D_BDW_PLUS);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2525 MMIO_DFH(GEN8_ROW_CHICKEN, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2526 NULL, NULL);
2527 MMIO_DFH(GEN7_ROW_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS,
2528 NULL, NULL);
2529 MMIO_DFH(GEN8_UCGCTL6, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2530
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2531 MMIO_DFH(0xb1f0, D_BDW, F_CMD_ACCESS, NULL, NULL);
2532 MMIO_DFH(0xb1c0, D_BDW, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2533 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2534 MMIO_DFH(0xb100, D_BDW, F_CMD_ACCESS, NULL, NULL);
2535 MMIO_DFH(0xb10c, D_BDW, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2536 MMIO_D(0xb110, D_BDW);
2537
Zhao Yane6cedfe2017-02-21 10:38:53 +0800[diff] [blame]2538 MMIO_F(0x24d0, 48, F_CMD_ACCESS, 0, 0, D_BDW_PLUS,
2539 NULL, force_nonpriv_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2540
Zhao Yan593e59b2017-02-20 15:51:13 +0800[diff] [blame]2541 MMIO_D(0x22040, D_BDW_PLUS);
2542 MMIO_D(0x44484, D_BDW_PLUS);
2543 MMIO_D(0x4448c, D_BDW_PLUS);
2544
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2545 MMIO_DFH(0x83a4, D_BDW, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2546 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2547
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2548 MMIO_DFH(0x8430, D_BDW, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2549
2550 MMIO_D(0x110000, D_BDW_PLUS);
2551
2552 MMIO_D(0x48400, D_BDW_PLUS);
2553
2554 MMIO_D(0x6e570, D_BDW_PLUS);
2555 MMIO_D(0x65f10, D_BDW_PLUS);
2556
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]2557 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2558 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
2559 MMIO_DFH(HALF_SLICE_CHICKEN2, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2560 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2561
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2562 MMIO_DFH(0x2248, D_BDW, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2563
Zhao Yan9112caa2017-02-28 15:40:10 +0800[diff] [blame]2564 MMIO_DFH(0xe220, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2565 MMIO_DFH(0xe230, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2566 MMIO_DFH(0xe240, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2567 MMIO_DFH(0xe260, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2568 MMIO_DFH(0xe270, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2569 MMIO_DFH(0xe280, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2570 MMIO_DFH(0xe2a0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2571 MMIO_DFH(0xe2b0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2572 MMIO_DFH(0xe2c0, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2573 return 0;
2574}
2575
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2576static int init_skl_mmio_info(struct intel_gvt *gvt)
2577{
2578 struct drm_i915_private *dev_priv = gvt->dev_priv;
2579 int ret;
2580
2581 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2582 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2583 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2584 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2585 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2586 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2587
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2588 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
2589 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
2590 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2591
2592 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2593 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2594
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2595 MMIO_D(0xa210, D_SKL_PLUS);
2596 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2597 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]2598 MMIO_DFH(GEN9_GAMT_ECO_REG_RW_IA, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2599 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write);
2600 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2601 MMIO_D(0x45504, D_SKL);
2602 MMIO_D(0x45520, D_SKL);
2603 MMIO_D(0x46000, D_SKL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2604 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write);
2605 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2606 MMIO_D(0x6C040, D_SKL);
2607 MMIO_D(0x6C048, D_SKL);
2608 MMIO_D(0x6C050, D_SKL);
2609 MMIO_D(0x6C044, D_SKL);
2610 MMIO_D(0x6C04C, D_SKL);
2611 MMIO_D(0x6C054, D_SKL);
2612 MMIO_D(0x6c058, D_SKL);
2613 MMIO_D(0x6c05c, D_SKL);
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2614 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2615
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2616 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write);
2617 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write);
2618 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write);
2619 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write);
2620 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write);
2621 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2622
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2623 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write);
2624 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write);
2625 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write);
2626 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write);
2627 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write);
2628 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2629
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2630 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write);
2631 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write);
2632 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write);
2633 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write);
2634 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write);
2635 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2636
2637 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL);
2638 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL);
2639 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL);
2640 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL);
2641
2642 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL);
2643 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL);
2644 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL);
2645 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL);
2646
2647 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL);
2648 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL);
2649 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL);
2650 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL);
2651
2652 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL);
2653 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL);
2654 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL);
2655
2656 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2657 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2658 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2659
2660 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2661 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2662 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2663
2664 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2665 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2666 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2667
2668 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2669 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2670 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2671
2672 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL);
2673 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL);
2674 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL);
2675
2676 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL);
2677 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL);
2678 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL);
2679
2680 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL);
2681 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL);
2682 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL);
2683
2684 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL);
2685 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL);
2686 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL);
2687
2688 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL);
2689 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL);
2690 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL);
2691 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL);
2692
2693 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL);
2694 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL);
2695 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL);
2696 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL);
2697
2698 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL);
2699 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL);
2700 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL);
2701 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL);
2702
2703 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL);
2704 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL);
2705 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL);
2706 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL);
2707
2708 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL);
2709 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL);
2710 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL);
2711 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL);
2712
2713 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL);
2714 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL);
2715 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL);
2716 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL);
2717
2718 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL);
2719 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL);
2720 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL);
2721 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL);
2722
2723 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL);
2724 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL);
2725 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL);
2726 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL);
2727
2728 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL);
2729 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL);
2730 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL);
2731 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL);
2732
2733 MMIO_D(0x70380, D_SKL);
2734 MMIO_D(0x71380, D_SKL);
2735 MMIO_D(0x72380, D_SKL);
2736 MMIO_D(0x7039c, D_SKL);
2737
2738 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL);
2739 MMIO_D(0x8f074, D_SKL);
2740 MMIO_D(0x8f004, D_SKL);
2741 MMIO_D(0x8f034, D_SKL);
2742
2743 MMIO_D(0xb11c, D_SKL);
2744
2745 MMIO_D(0x51000, D_SKL);
2746 MMIO_D(0x6c00c, D_SKL);
2747
Ping Gaoa045fba2016-11-14 10:22:54 +0800[diff] [blame]2748 MMIO_F(0xc800, 0x7f8, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL);
2749 MMIO_F(0xb020, 0x80, F_CMD_ACCESS, 0, 0, D_SKL, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2750
2751 MMIO_D(0xd08, D_SKL);
Zhao Yan1f58af32017-02-28 15:41:03 +0800[diff] [blame^]2752 MMIO_DFH(0x20e0, D_SKL, F_MODE_MASK, NULL, NULL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2753 MMIO_DFH(0x20ec, D_SKL, F_MODE_MASK | F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2754
2755 /* TRTT */
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2756 MMIO_DFH(0x4de0, D_SKL, F_CMD_ACCESS, NULL, NULL);
2757 MMIO_DFH(0x4de4, D_SKL, F_CMD_ACCESS, NULL, NULL);
2758 MMIO_DFH(0x4de8, D_SKL, F_CMD_ACCESS, NULL, NULL);
2759 MMIO_DFH(0x4dec, D_SKL, F_CMD_ACCESS, NULL, NULL);
2760 MMIO_DFH(0x4df0, D_SKL, F_CMD_ACCESS, NULL, NULL);
2761 MMIO_DFH(0x4df4, D_SKL, F_CMD_ACCESS, NULL, gen9_trtte_write);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2762 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write);
2763
2764 MMIO_D(0x45008, D_SKL);
2765
2766 MMIO_D(0x46430, D_SKL);
2767
2768 MMIO_D(0x46520, D_SKL);
2769
2770 MMIO_D(0xc403c, D_SKL);
2771 MMIO_D(0xb004, D_SKL);
2772 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2773
2774 MMIO_D(0x65900, D_SKL);
2775 MMIO_D(0x1082c0, D_SKL);
2776 MMIO_D(0x4068, D_SKL);
2777 MMIO_D(0x67054, D_SKL);
2778 MMIO_D(0x6e560, D_SKL);
2779 MMIO_D(0x6e554, D_SKL);
2780 MMIO_D(0x2b20, D_SKL);
2781 MMIO_D(0x65f00, D_SKL);
2782 MMIO_D(0x65f08, D_SKL);
2783 MMIO_D(0x320f0, D_SKL);
2784
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2785 MMIO_DFH(_REG_VCS2_EXCC, D_SKL, F_CMD_ACCESS, NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2786 MMIO_D(0x70034, D_SKL);
2787 MMIO_D(0x71034, D_SKL);
2788 MMIO_D(0x72034, D_SKL);
2789
2790 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL);
2791 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL);
2792 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL);
2793 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL);
2794 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL);
2795 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL);
2796
2797 MMIO_D(0x44500, D_SKL);
Zhao Yan0aa52772017-02-28 15:39:25 +0800[diff] [blame]2798 MMIO_DFH(GEN9_CSFE_CHICKEN1_RCS, D_SKL_PLUS, F_CMD_ACCESS, NULL, NULL);
Zhao Yan9112caa2017-02-28 15:40:10 +0800[diff] [blame]2799 MMIO_DFH(GEN8_HDC_CHICKEN1, D_SKL, F_MODE_MASK | F_CMD_ACCESS,
2800 NULL, NULL);
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2801 return 0;
2802}
Zhi Wang04d348a2016-04-25 18:28:56 -0400[diff] [blame]2803
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2804/**
2805 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset
2806 * @gvt: GVT device
2807 * @offset: register offset
2808 *
2809 * This function is used to find the MMIO information entry from hash table
2810 *
2811 * Returns:
2812 * pointer to MMIO information entry, NULL if not exists
2813 */
2814struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
2815 unsigned int offset)
2816{
2817 struct intel_gvt_mmio_info *e;
2818
2819 WARN_ON(!IS_ALIGNED(offset, 4));
2820
2821 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
2822 if (e->offset == offset)
2823 return e;
2824 }
2825 return NULL;
2826}
2827
2828/**
2829 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2830 * @gvt: GVT device
2831 *
2832 * This function is called at the driver unloading stage, to clean up the MMIO
2833 * information table of GVT device
2834 *
2835 */
2836void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2837{
2838 struct hlist_node *tmp;
2839 struct intel_gvt_mmio_info *e;
2840 int i;
2841
2842 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2843 kfree(e);
2844
2845 vfree(gvt->mmio.mmio_attribute);
2846 gvt->mmio.mmio_attribute = NULL;
2847}
2848
2849/**
2850 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2851 * @gvt: GVT device
2852 *
2853 * This function is called at the initialization stage, to setup the MMIO
2854 * information table for GVT device
2855 *
2856 * Returns:
2857 * zero on success, negative if failed.
2858 */
2859int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2860{
2861 struct intel_gvt_device_info *info = &gvt->device_info;
2862 struct drm_i915_private *dev_priv = gvt->dev_priv;
2863 int ret;
2864
2865 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size);
2866 if (!gvt->mmio.mmio_attribute)
2867 return -ENOMEM;
2868
2869 ret = init_generic_mmio_info(gvt);
2870 if (ret)
2871 goto err;
2872
2873 if (IS_BROADWELL(dev_priv)) {
2874 ret = init_broadwell_mmio_info(gvt);
2875 if (ret)
2876 goto err;
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2877 } else if (IS_SKYLAKE(dev_priv)) {
2878 ret = init_broadwell_mmio_info(gvt);
2879 if (ret)
2880 goto err;
2881 ret = init_skl_mmio_info(gvt);
2882 if (ret)
2883 goto err;
Zhi Wang12d14cc2016-08-30 11:06:17 +0800[diff] [blame]2884 }
2885 return 0;
2886err:
2887 intel_gvt_clean_mmio_info(gvt);
2888 return ret;
2889}
Zhi Wange39c5ad2016-09-02 13:33:29 +0800[diff] [blame]2890
2891/**
2892 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
2893 * @gvt: a GVT device
2894 * @offset: register offset
2895 *
2896 */
2897void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset)
2898{
2899 gvt->mmio.mmio_attribute[offset >> 2] |=
2900 F_ACCESSED;
2901}
2902
2903/**
2904 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command
2905 * @gvt: a GVT device
2906 * @offset: register offset
2907 *
2908 */
2909bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt,
2910 unsigned int offset)
2911{
2912 return gvt->mmio.mmio_attribute[offset >> 2] &
2913 F_CMD_ACCESS;
2914}
2915
2916/**
2917 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
2918 * @gvt: a GVT device
2919 * @offset: register offset
2920 *
2921 */
2922bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt,
2923 unsigned int offset)
2924{
2925 return gvt->mmio.mmio_attribute[offset >> 2] &
2926 F_UNALIGN;
2927}
2928
2929/**
2930 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command
2931 * @gvt: a GVT device
2932 * @offset: register offset
2933 *
2934 */
2935void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt,
2936 unsigned int offset)
2937{
2938 gvt->mmio.mmio_attribute[offset >> 2] |=
2939 F_CMD_ACCESSED;
2940}
2941
2942/**
2943 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
2944 * @gvt: a GVT device
2945 * @offset: register offset
2946 *
2947 * Returns:
2948 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
2949 *
2950 */
2951bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset)
2952{
2953 return gvt->mmio.mmio_attribute[offset >> 2] &
2954 F_MODE_MASK;
2955}
2956
2957/**
2958 * intel_vgpu_default_mmio_read - default MMIO read handler
2959 * @vgpu: a vGPU
2960 * @offset: access offset
2961 * @p_data: data return buffer
2962 * @bytes: access data length
2963 *
2964 * Returns:
2965 * Zero on success, negative error code if failed.
2966 */
2967int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
2968 void *p_data, unsigned int bytes)
2969{
2970 read_vreg(vgpu, offset, p_data, bytes);
2971 return 0;
2972}
2973
2974/**
2975 * intel_t_default_mmio_write - default MMIO write handler
2976 * @vgpu: a vGPU
2977 * @offset: access offset
2978 * @p_data: write data buffer
2979 * @bytes: access data length
2980 *
2981 * Returns:
2982 * Zero on success, negative error code if failed.
2983 */
2984int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
2985 void *p_data, unsigned int bytes)
2986{
2987 write_vreg(vgpu, offset, p_data, bytes);
2988 return 0;
2989}