| Ilan Tayari | e29341f | 2017-03-13 20:05:45 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2017, Mellanox Technologies, Ltd. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * |
| 18 | * - Redistributions in binary form must reproduce the above |
| 19 | * copyright notice, this list of conditions and the following |
| 20 | * disclaimer in the documentation and/or other materials |
| 21 | * provided with the distribution. |
| 22 | * |
| 23 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 24 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 25 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 26 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 27 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 28 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 29 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 30 | * SOFTWARE. |
| 31 | */ |
| 32 | #ifndef MLX5_IFC_FPGA_H |
| 33 | #define MLX5_IFC_FPGA_H |
| 34 | |
| 35 | struct mlx5_ifc_fpga_shell_caps_bits { |
| 36 | u8 max_num_qps[0x10]; |
| 37 | u8 reserved_at_10[0x8]; |
| 38 | u8 total_rcv_credits[0x8]; |
| 39 | |
| 40 | u8 reserved_at_20[0xe]; |
| 41 | u8 qp_type[0x2]; |
| 42 | u8 reserved_at_30[0x5]; |
| 43 | u8 rae[0x1]; |
| 44 | u8 rwe[0x1]; |
| 45 | u8 rre[0x1]; |
| 46 | u8 reserved_at_38[0x4]; |
| 47 | u8 dc[0x1]; |
| 48 | u8 ud[0x1]; |
| 49 | u8 uc[0x1]; |
| 50 | u8 rc[0x1]; |
| 51 | |
| 52 | u8 reserved_at_40[0x1a]; |
| 53 | u8 log_ddr_size[0x6]; |
| 54 | |
| 55 | u8 max_fpga_qp_msg_size[0x20]; |
| 56 | |
| 57 | u8 reserved_at_80[0x180]; |
| 58 | }; |
| 59 | |
| 60 | struct mlx5_ifc_fpga_cap_bits { |
| 61 | u8 fpga_id[0x8]; |
| 62 | u8 fpga_device[0x18]; |
| 63 | |
| 64 | u8 register_file_ver[0x20]; |
| 65 | |
| 66 | u8 fpga_ctrl_modify[0x1]; |
| 67 | u8 reserved_at_41[0x5]; |
| 68 | u8 access_reg_query_mode[0x2]; |
| 69 | u8 reserved_at_48[0x6]; |
| 70 | u8 access_reg_modify_mode[0x2]; |
| 71 | u8 reserved_at_50[0x10]; |
| 72 | |
| 73 | u8 reserved_at_60[0x20]; |
| 74 | |
| 75 | u8 image_version[0x20]; |
| 76 | |
| 77 | u8 image_date[0x20]; |
| 78 | |
| 79 | u8 image_time[0x20]; |
| 80 | |
| 81 | u8 shell_version[0x20]; |
| 82 | |
| 83 | u8 reserved_at_100[0x80]; |
| 84 | |
| 85 | struct mlx5_ifc_fpga_shell_caps_bits shell_caps; |
| 86 | |
| 87 | u8 reserved_at_380[0x8]; |
| 88 | u8 ieee_vendor_id[0x18]; |
| 89 | |
| 90 | u8 sandbox_product_version[0x10]; |
| 91 | u8 sandbox_product_id[0x10]; |
| 92 | |
| 93 | u8 sandbox_basic_caps[0x20]; |
| 94 | |
| 95 | u8 reserved_at_3e0[0x10]; |
| 96 | u8 sandbox_extended_caps_len[0x10]; |
| 97 | |
| 98 | u8 sandbox_extended_caps_addr[0x40]; |
| 99 | |
| 100 | u8 fpga_ddr_start_addr[0x40]; |
| 101 | |
| 102 | u8 fpga_cr_space_start_addr[0x40]; |
| 103 | |
| 104 | u8 fpga_ddr_size[0x20]; |
| 105 | |
| 106 | u8 fpga_cr_space_size[0x20]; |
| 107 | |
| 108 | u8 reserved_at_500[0x300]; |
| 109 | }; |
| 110 | |
| 111 | struct mlx5_ifc_fpga_ctrl_bits { |
| 112 | u8 reserved_at_0[0x8]; |
| 113 | u8 operation[0x8]; |
| 114 | u8 reserved_at_10[0x8]; |
| 115 | u8 status[0x8]; |
| 116 | |
| 117 | u8 reserved_at_20[0x8]; |
| 118 | u8 flash_select_admin[0x8]; |
| 119 | u8 reserved_at_30[0x8]; |
| 120 | u8 flash_select_oper[0x8]; |
| 121 | |
| 122 | u8 reserved_at_40[0x40]; |
| 123 | }; |
| 124 | |
| 125 | enum { |
| 126 | MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR = 0x1, |
| 127 | MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT = 0x2, |
| 128 | MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR = 0x3, |
| 129 | MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE = 0x4, |
| 130 | MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE = 0x5, |
| 131 | MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED = 0x6, |
| 132 | MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7, |
| 133 | }; |
| 134 | |
| 135 | struct mlx5_ifc_fpga_error_event_bits { |
| 136 | u8 reserved_at_0[0x40]; |
| 137 | |
| 138 | u8 reserved_at_40[0x18]; |
| 139 | u8 syndrome[0x8]; |
| 140 | |
| 141 | u8 reserved_at_60[0x80]; |
| 142 | }; |
| 143 | |
| 144 | #endif /* MLX5_IFC_FPGA_H */ |