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gerrit-public.fairphone.software / kernel / msm-5.4 / 95beb690170e6ce918fe53c73a0fcc7cf64d704a / . / drivers / gpu / drm / radeon / radeon_asic.h
blob: a0b8280663d1ba9d17dd6252cce1274d73b7181d [file] [log] [blame]
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]1/*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28#ifndef __RADEON_ASIC_H__
29#define __RADEON_ASIC_H__
30
31/*
32 * common functions
33 */
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]34uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]35void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki5ea597f2009-12-17 13:50:09 +0100[diff] [blame]36uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]37void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
38
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]39uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]40void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
Rafał Miłecki74338742009-11-03 00:53:02 +0100[diff] [blame]41uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]42void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
43void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
44
45/*
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]46 * r100,rv100,rs100,rv200,rs200
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]47 */
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]48struct r100_mc_save {
49 u32 GENMO_WT;
50 u32 CRTC_EXT_CNTL;
51 u32 CRTC_GEN_CNTL;
52 u32 CRTC2_GEN_CNTL;
53 u32 CUR_OFFSET;
54 u32 CUR2_OFFSET;
55};
56int r100_init(struct radeon_device *rdev);
57void r100_fini(struct radeon_device *rdev);
58int r100_suspend(struct radeon_device *rdev);
59int r100_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]60uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
61void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]62void r100_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]63int r100_gpu_reset(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]64u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]65void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
66int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]67void r100_cp_commit(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]68void r100_ring_start(struct radeon_device *rdev);
69int r100_irq_set(struct radeon_device *rdev);
70int r100_irq_process(struct radeon_device *rdev);
71void r100_fence_ring_emit(struct radeon_device *rdev,
72 struct radeon_fence *fence);
73int r100_cs_parse(struct radeon_cs_parser *p);
74void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
75uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
76int r100_copy_blit(struct radeon_device *rdev,
77 uint64_t src_offset,
78 uint64_t dst_offset,
79 unsigned num_pages,
80 struct radeon_fence *fence);
Dave Airliee024e112009-06-24 09:48:08 +1000[diff] [blame]81int r100_set_surface_reg(struct radeon_device *rdev, int reg,
82 uint32_t tiling_flags, uint32_t pitch,
83 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]84void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]85void r100_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]86void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]87int r100_ring_test(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]88void r100_hpd_init(struct radeon_device *rdev);
89void r100_hpd_fini(struct radeon_device *rdev);
90bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
91void r100_hpd_set_polarity(struct radeon_device *rdev,
92 enum radeon_hpd_id hpd);
Daniel Vetter2b497502010-03-11 21:19:18 +0000[diff] [blame]93int r100_debugfs_rbbm_init(struct radeon_device *rdev);
94int r100_debugfs_cp_init(struct radeon_device *rdev);
95void r100_cp_disable(struct radeon_device *rdev);
96int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
97void r100_cp_fini(struct radeon_device *rdev);
98int r100_pci_gart_init(struct radeon_device *rdev);
99void r100_pci_gart_fini(struct radeon_device *rdev);
100int r100_pci_gart_enable(struct radeon_device *rdev);
101void r100_pci_gart_disable(struct radeon_device *rdev);
102int r100_debugfs_mc_info_init(struct radeon_device *rdev);
103int r100_gui_wait_for_idle(struct radeon_device *rdev);
104void r100_ib_fini(struct radeon_device *rdev);
105int r100_ib_init(struct radeon_device *rdev);
106void r100_irq_disable(struct radeon_device *rdev);
107void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
108void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
109void r100_vram_init_sizes(struct radeon_device *rdev);
110void r100_wb_disable(struct radeon_device *rdev);
111void r100_wb_fini(struct radeon_device *rdev);
112int r100_wb_init(struct radeon_device *rdev);
113void r100_hdp_reset(struct radeon_device *rdev);
114int r100_rb2d_reset(struct radeon_device *rdev);
115int r100_cp_reset(struct radeon_device *rdev);
116void r100_vga_render_disable(struct radeon_device *rdev);
117int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
118 struct radeon_cs_packet *pkt,
119 struct radeon_bo *robj);
120int r100_cs_parse_packet0(struct radeon_cs_parser *p,
121 struct radeon_cs_packet *pkt,
122 const unsigned *auth, unsigned n,
123 radeon_packet0_check_t check);
124int r100_cs_packet_parse(struct radeon_cs_parser *p,
125 struct radeon_cs_packet *pkt,
126 unsigned idx);
127void r100_enable_bm(struct radeon_device *rdev);
128void r100_set_common_regs(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]129
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]130/*
131 * r200,rv250,rs300,rv280
132 */
133extern int r200_copy_dma(struct radeon_device *rdev,
134 uint64_t src_offset,
135 uint64_t dst_offset,
136 unsigned num_pages,
137 struct radeon_fence *fence);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]138
139/*
140 * r300,r350,rv350,rv380
141 */
Jerome Glisse207bf9e2009-09-30 15:35:32 +0200[diff] [blame]142extern int r300_init(struct radeon_device *rdev);
143extern void r300_fini(struct radeon_device *rdev);
144extern int r300_suspend(struct radeon_device *rdev);
145extern int r300_resume(struct radeon_device *rdev);
146extern int r300_gpu_reset(struct radeon_device *rdev);
147extern void r300_ring_start(struct radeon_device *rdev);
148extern void r300_fence_ring_emit(struct radeon_device *rdev,
149 struct radeon_fence *fence);
150extern int r300_cs_parse(struct radeon_cs_parser *p);
151extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
152extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
153extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
154extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
155extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
Alex Deucherc836a412009-12-23 10:07:50 -0500[diff] [blame]156extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
Pauli Nieminen44ca7472010-02-11 17:25:47 +0000[diff] [blame]157
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]158/*
159 * r420,r423,rv410
160 */
Jerome Glisse9f022dd2009-09-11 15:35:22 +0200[diff] [blame]161extern int r420_init(struct radeon_device *rdev);
162extern void r420_fini(struct radeon_device *rdev);
163extern int r420_suspend(struct radeon_device *rdev);
164extern int r420_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]165
166/*
167 * rs400,rs480
168 */
Jerome Glisseca6ffc62009-10-01 10:20:52 +0200[diff] [blame]169extern int rs400_init(struct radeon_device *rdev);
170extern void rs400_fini(struct radeon_device *rdev);
171extern int rs400_suspend(struct radeon_device *rdev);
172extern int rs400_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]173void rs400_gart_tlb_flush(struct radeon_device *rdev);
174int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
175uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
176void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]177
178/*
179 * rs600.
180 */
Jerome Glissec010f802009-09-30 22:09:06 +0200[diff] [blame]181extern int rs600_init(struct radeon_device *rdev);
182extern void rs600_fini(struct radeon_device *rdev);
183extern int rs600_suspend(struct radeon_device *rdev);
184extern int rs600_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]185int rs600_irq_set(struct radeon_device *rdev);
Michel Dänzer7ed220d2009-08-13 11:10:51 +0200[diff] [blame]186int rs600_irq_process(struct radeon_device *rdev);
187u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]188void rs600_gart_tlb_flush(struct radeon_device *rdev);
189int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
190uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
191void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]192void rs600_bandwidth_update(struct radeon_device *rdev);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]193void rs600_hpd_init(struct radeon_device *rdev);
194void rs600_hpd_fini(struct radeon_device *rdev);
195bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
196void rs600_hpd_set_polarity(struct radeon_device *rdev,
197 enum radeon_hpd_id hpd);
198
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]199/*
200 * rs690,rs740
201 */
Jerome Glisse3bc68532009-10-01 09:39:24 +0200[diff] [blame]202int rs690_init(struct radeon_device *rdev);
203void rs690_fini(struct radeon_device *rdev);
204int rs690_resume(struct radeon_device *rdev);
205int rs690_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]206uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
207void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]208void rs690_bandwidth_update(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]209
210/*
211 * rv515
212 */
Jerome Glisse068a1172009-06-17 13:28:30 +0200[diff] [blame]213int rv515_init(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]214void rv515_fini(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]215int rv515_gpu_reset(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]216uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
217void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
218void rv515_ring_start(struct radeon_device *rdev);
219uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
220void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glissec93bb852009-07-13 21:04:08 +0200[diff] [blame]221void rv515_bandwidth_update(struct radeon_device *rdev);
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]222int rv515_resume(struct radeon_device *rdev);
223int rv515_suspend(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]224
225/*
226 * r520,rv530,rv560,rv570,r580
227 */
Jerome Glissed39c3b82009-09-28 18:34:43 +0200[diff] [blame]228int r520_init(struct radeon_device *rdev);
Jerome Glissef0ed1f62009-09-28 20:39:19 +0200[diff] [blame]229int r520_resume(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]230
231/*
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]232 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]233 */
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]234int r600_init(struct radeon_device *rdev);
235void r600_fini(struct radeon_device *rdev);
236int r600_suspend(struct radeon_device *rdev);
237int r600_resume(struct radeon_device *rdev);
Dave Airlie28d52042009-09-21 14:33:58 +1000[diff] [blame]238void r600_vga_set_state(struct radeon_device *rdev, bool state);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]239int r600_wb_init(struct radeon_device *rdev);
240void r600_wb_fini(struct radeon_device *rdev);
241void r600_cp_commit(struct radeon_device *rdev);
242void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]243uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
244void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]245int r600_cs_parse(struct radeon_cs_parser *p);
246void r600_fence_ring_emit(struct radeon_device *rdev,
247 struct radeon_fence *fence);
248int r600_copy_dma(struct radeon_device *rdev,
249 uint64_t src_offset,
250 uint64_t dst_offset,
251 unsigned num_pages,
252 struct radeon_fence *fence);
253int r600_irq_process(struct radeon_device *rdev);
254int r600_irq_set(struct radeon_device *rdev);
255int r600_gpu_reset(struct radeon_device *rdev);
256int r600_set_surface_reg(struct radeon_device *rdev, int reg,
257 uint32_t tiling_flags, uint32_t pitch,
258 uint32_t offset, uint32_t obj_size);
Daniel Vetter9479c542010-03-11 21:19:16 +0000[diff] [blame]259void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]260void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]261int r600_ring_test(struct radeon_device *rdev);
262int r600_copy_blit(struct radeon_device *rdev,
263 uint64_t src_offset, uint64_t dst_offset,
264 unsigned num_pages, struct radeon_fence *fence);
Alex Deucher429770b2009-12-04 15:26:55 -0500[diff] [blame]265void r600_hpd_init(struct radeon_device *rdev);
266void r600_hpd_fini(struct radeon_device *rdev);
267bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
268void r600_hpd_set_polarity(struct radeon_device *rdev,
269 enum radeon_hpd_id hpd);
Jerome Glisse062b3892010-02-04 20:36:39 +0100[diff] [blame]270extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]271
Jerome Glisse3ce0a232009-09-08 10:10:24 +1000[diff] [blame]272/*
273 * rv770,rv730,rv710,rv740
274 */
275int rv770_init(struct radeon_device *rdev);
276void rv770_fini(struct radeon_device *rdev);
277int rv770_suspend(struct radeon_device *rdev);
278int rv770_resume(struct radeon_device *rdev);
279int rv770_gpu_reset(struct radeon_device *rdev);
280
Alex Deucherbcc1c2a2010-01-12 17:54:34 -0500[diff] [blame]281/*
282 * evergreen
283 */
284int evergreen_init(struct radeon_device *rdev);
285void evergreen_fini(struct radeon_device *rdev);
286int evergreen_suspend(struct radeon_device *rdev);
287int evergreen_resume(struct radeon_device *rdev);
288int evergreen_gpu_reset(struct radeon_device *rdev);
289void evergreen_bandwidth_update(struct radeon_device *rdev);
290void evergreen_hpd_init(struct radeon_device *rdev);
291void evergreen_hpd_fini(struct radeon_device *rdev);
292bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
293void evergreen_hpd_set_polarity(struct radeon_device *rdev,
294 enum radeon_hpd_id hpd);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200[diff] [blame]295#endif