| JeongHyeon Kim | 699efdd | 2011-07-21 16:19:19 +0900 | [diff] [blame] | 1 | /* linux/arch/arm/mach-exynos4/mach-origen.c |
| 2 | * |
| 3 | * Copyright (c) 2011 Insignal Co., Ltd. |
| 4 | * http://www.insignal.co.kr/ |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/serial_core.h> |
| 12 | #include <linux/gpio.h> |
| 13 | #include <linux/mmc/host.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <linux/io.h> |
| 16 | #include <linux/input.h> |
| 17 | |
| 18 | #include <asm/mach/arch.h> |
| 19 | #include <asm/mach-types.h> |
| 20 | |
| 21 | #include <plat/regs-serial.h> |
| 22 | #include <plat/exynos4.h> |
| 23 | #include <plat/cpu.h> |
| 24 | #include <plat/devs.h> |
| 25 | #include <plat/sdhci.h> |
| 26 | #include <plat/iic.h> |
| 27 | |
| 28 | #include <mach/map.h> |
| 29 | |
| 30 | /* Following are default values for UCON, ULCON and UFCON UART registers */ |
| 31 | #define ORIGEN_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
| 32 | S3C2410_UCON_RXILEVEL | \ |
| 33 | S3C2410_UCON_TXIRQMODE | \ |
| 34 | S3C2410_UCON_RXIRQMODE | \ |
| 35 | S3C2410_UCON_RXFIFO_TOI | \ |
| 36 | S3C2443_UCON_RXERR_IRQEN) |
| 37 | |
| 38 | #define ORIGEN_ULCON_DEFAULT S3C2410_LCON_CS8 |
| 39 | |
| 40 | #define ORIGEN_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ |
| 41 | S5PV210_UFCON_TXTRIG4 | \ |
| 42 | S5PV210_UFCON_RXTRIG4) |
| 43 | |
| 44 | static struct s3c2410_uartcfg origen_uartcfgs[] __initdata = { |
| 45 | [0] = { |
| 46 | .hwport = 0, |
| 47 | .flags = 0, |
| 48 | .ucon = ORIGEN_UCON_DEFAULT, |
| 49 | .ulcon = ORIGEN_ULCON_DEFAULT, |
| 50 | .ufcon = ORIGEN_UFCON_DEFAULT, |
| 51 | }, |
| 52 | [1] = { |
| 53 | .hwport = 1, |
| 54 | .flags = 0, |
| 55 | .ucon = ORIGEN_UCON_DEFAULT, |
| 56 | .ulcon = ORIGEN_ULCON_DEFAULT, |
| 57 | .ufcon = ORIGEN_UFCON_DEFAULT, |
| 58 | }, |
| 59 | [2] = { |
| 60 | .hwport = 2, |
| 61 | .flags = 0, |
| 62 | .ucon = ORIGEN_UCON_DEFAULT, |
| 63 | .ulcon = ORIGEN_ULCON_DEFAULT, |
| 64 | .ufcon = ORIGEN_UFCON_DEFAULT, |
| 65 | }, |
| 66 | [3] = { |
| 67 | .hwport = 3, |
| 68 | .flags = 0, |
| 69 | .ucon = ORIGEN_UCON_DEFAULT, |
| 70 | .ulcon = ORIGEN_ULCON_DEFAULT, |
| 71 | .ufcon = ORIGEN_UFCON_DEFAULT, |
| 72 | }, |
| 73 | }; |
| 74 | |
| 75 | static struct s3c_sdhci_platdata origen_hsmmc2_pdata __initdata = { |
| 76 | .cd_type = S3C_SDHCI_CD_GPIO, |
| 77 | .ext_cd_gpio = EXYNOS4_GPK2(2), |
| 78 | .ext_cd_gpio_invert = 1, |
| 79 | .clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL, |
| 80 | }; |
| 81 | |
| 82 | static struct platform_device *origen_devices[] __initdata = { |
| 83 | &s3c_device_hsmmc2, |
| 84 | &s3c_device_rtc, |
| 85 | &s3c_device_wdt, |
| 86 | }; |
| 87 | |
| 88 | static void __init origen_map_io(void) |
| 89 | { |
| 90 | s5p_init_io(NULL, 0, S5P_VA_CHIPID); |
| 91 | s3c24xx_init_clocks(24000000); |
| 92 | s3c24xx_init_uarts(origen_uartcfgs, ARRAY_SIZE(origen_uartcfgs)); |
| 93 | } |
| 94 | |
| 95 | static void __init origen_machine_init(void) |
| 96 | { |
| 97 | s3c_sdhci2_set_platdata(&origen_hsmmc2_pdata); |
| 98 | platform_add_devices(origen_devices, ARRAY_SIZE(origen_devices)); |
| 99 | } |
| 100 | |
| 101 | MACHINE_START(ORIGEN, "ORIGEN") |
| 102 | /* Maintainer: JeongHyeon Kim <jhkim@insignal.co.kr> */ |
| 103 | .boot_params = S5P_PA_SDRAM + 0x100, |
| 104 | .init_irq = exynos4_init_irq, |
| 105 | .map_io = origen_map_io, |
| 106 | .init_machine = origen_machine_init, |
| 107 | .timer = &exynos4_timer, |
| 108 | MACHINE_END |