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gerrit-public.fairphone.software / kernel / msm-5.4 / 1bde9906414b46b6922464e7c91dd815e5f217b3 / . / arch / arm / boot / dts / versatile-ab.dts
blob: 85c7b2b8ad1bc780d2cacc7b75db431ccfdb701b [file] [log] [blame]
Grant Likely3ba72222011-07-26 03:19:06 -0600[diff] [blame]1/dts-v1/;
2/include/ "skeleton.dtsi"
3
4/ {
5 model = "ARM Versatile AB";
6 compatible = "arm,versatile-ab";
7 #address-cells = <1>;
8 #size-cells = <1>;
9 interrupt-parent = <&vic>;
10
11 aliases {
12 serial0 = &uart0;
13 serial1 = &uart1;
14 serial2 = &uart2;
15 i2c0 = &i2c0;
16 };
17
18 memory {
19 reg = <0x0 0x08000000>;
20 };
21
22 flash@34000000 {
23 compatible = "arm,versatile-flash";
24 reg = <0x34000000 0x4000000>;
25 bank-width = <4>;
26 };
27
28 i2c0: i2c@10002000 {
29 #address-cells = <1>;
30 #size-cells = <0>;
31 compatible = "arm,versatile-i2c";
32 reg = <0x10002000 0x1000>;
33
34 rtc@68 {
35 compatible = "dallas,ds1338";
36 reg = <0x68>;
37 };
38 };
39
40 net@10010000 {
41 compatible = "smsc,lan91c111";
42 reg = <0x10010000 0x10000>;
43 interrupts = <25>;
44 };
45
46 lcd@10008000 {
47 compatible = "arm,versatile-lcd";
48 reg = <0x10008000 0x1000>;
49 };
50
51 amba {
52 compatible = "arm,amba-bus";
53 #address-cells = <1>;
54 #size-cells = <1>;
55 ranges;
56
57 vic: intc@10140000 {
58 compatible = "arm,versatile-vic";
59 interrupt-controller;
60 #interrupt-cells = <1>;
61 reg = <0x10140000 0x1000>;
Rob Herring0ba6c5d2014-03-01 22:22:21 -0600[diff] [blame]62 clear-mask = <0xffffffff>;
63 valid-mask = <0xffffffff>;
Grant Likely3ba72222011-07-26 03:19:06 -0600[diff] [blame]64 };
65
66 sic: intc@10003000 {
67 compatible = "arm,versatile-sic";
68 interrupt-controller;
69 #interrupt-cells = <1>;
70 reg = <0x10003000 0x1000>;
71 interrupt-parent = <&vic>;
72 interrupts = <31>; /* Cascaded to vic */
Rob Herring0ba6c5d2014-03-01 22:22:21 -0600[diff] [blame]73 clear-mask = <0xffffffff>;
74 valid-mask = <0xffc203f8>;
Grant Likely3ba72222011-07-26 03:19:06 -0600[diff] [blame]75 };
76
77 dma@10130000 {
78 compatible = "arm,pl081", "arm,primecell";
79 reg = <0x10130000 0x1000>;
80 interrupts = <17>;
81 };
82
83 uart0: uart@101f1000 {
84 compatible = "arm,pl011", "arm,primecell";
85 reg = <0x101f1000 0x1000>;
86 interrupts = <12>;
87 };
88
89 uart1: uart@101f2000 {
90 compatible = "arm,pl011", "arm,primecell";
91 reg = <0x101f2000 0x1000>;
92 interrupts = <13>;
93 };
94
95 uart2: uart@101f3000 {
96 compatible = "arm,pl011", "arm,primecell";
97 reg = <0x101f3000 0x1000>;
98 interrupts = <14>;
99 };
100
101 smc@10100000 {
102 compatible = "arm,primecell";
103 reg = <0x10100000 0x1000>;
104 };
105
106 mpmc@10110000 {
107 compatible = "arm,primecell";
108 reg = <0x10110000 0x1000>;
109 };
110
111 display@10120000 {
112 compatible = "arm,pl110", "arm,primecell";
113 reg = <0x10120000 0x1000>;
114 interrupts = <16>;
115 };
116
117 sctl@101e0000 {
118 compatible = "arm,primecell";
119 reg = <0x101e0000 0x1000>;
120 };
121
122 watchdog@101e1000 {
123 compatible = "arm,primecell";
124 reg = <0x101e1000 0x1000>;
125 interrupts = <0>;
126 };
127
Rob Herring818270d2013-03-13 17:07:44 -0500[diff] [blame]128 timer@101e2000 {
129 compatible = "arm,sp804", "arm,primecell";
130 reg = <0x101e2000 0x1000>;
131 interrupts = <4>;
132 };
133
134 timer@101e3000 {
135 compatible = "arm,sp804", "arm,primecell";
136 reg = <0x101e3000 0x1000>;
137 interrupts = <5>;
138 };
139
Grant Likely3ba72222011-07-26 03:19:06 -0600[diff] [blame]140 gpio0: gpio@101e4000 {
141 compatible = "arm,pl061", "arm,primecell";
142 reg = <0x101e4000 0x1000>;
143 gpio-controller;
144 interrupts = <6>;
145 #gpio-cells = <2>;
146 interrupt-controller;
147 #interrupt-cells = <2>;
148 };
149
150 gpio1: gpio@101e5000 {
151 compatible = "arm,pl061", "arm,primecell";
152 reg = <0x101e5000 0x1000>;
153 interrupts = <7>;
154 gpio-controller;
155 #gpio-cells = <2>;
156 interrupt-controller;
157 #interrupt-cells = <2>;
158 };
159
160 rtc@101e8000 {
161 compatible = "arm,pl030", "arm,primecell";
162 reg = <0x101e8000 0x1000>;
163 interrupts = <10>;
164 };
165
166 sci@101f0000 {
167 compatible = "arm,primecell";
168 reg = <0x101f0000 0x1000>;
169 interrupts = <15>;
170 };
171
172 ssp@101f4000 {
173 compatible = "arm,pl022", "arm,primecell";
174 reg = <0x101f4000 0x1000>;
175 interrupts = <11>;
176 };
177
178 fpga {
179 compatible = "arm,versatile-fpga", "simple-bus";
180 #address-cells = <1>;
181 #size-cells = <1>;
182 ranges = <0 0x10000000 0x10000>;
183
184 aaci@4000 {
185 compatible = "arm,primecell";
186 reg = <0x4000 0x1000>;
187 interrupts = <24>;
188 };
189 mmc@5000 {
Rob Herring04aa49f2014-03-03 02:28:38 -0600[diff] [blame]190 compatible = "arm,pl180", "arm,primecell";
Grant Likely3ba72222011-07-26 03:19:06 -0600[diff] [blame]191 reg = < 0x5000 0x1000>;
Grant Likely0976c942013-10-28 16:50:11 -0700[diff] [blame]192 interrupts-extended = <&vic 22 &sic 2>;
Grant Likely3ba72222011-07-26 03:19:06 -0600[diff] [blame]193 };
194 kmi@6000 {
195 compatible = "arm,pl050", "arm,primecell";
196 reg = <0x6000 0x1000>;
197 interrupt-parent = <&sic>;
198 interrupts = <3>;
199 };
200 kmi@7000 {
201 compatible = "arm,pl050", "arm,primecell";
202 reg = <0x7000 0x1000>;
203 interrupt-parent = <&sic>;
204 interrupts = <4>;
205 };
206 };
207 };
208};