Archit Taneja | 5cac5ae | 2013-10-08 13:07:00 +0530 | [diff] [blame] | 1 | /* |
| 2 | * HDMI PHY |
| 3 | * |
| 4 | * Copyright (C) 2013 Texas Instruments Incorporated |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published by |
| 8 | * the Free Software Foundation. |
| 9 | */ |
| 10 | |
| 11 | #include <linux/kernel.h> |
Archit Taneja | 5cac5ae | 2013-10-08 13:07:00 +0530 | [diff] [blame] | 12 | #include <linux/err.h> |
| 13 | #include <linux/io.h> |
| 14 | #include <linux/platform_device.h> |
| 15 | #include <video/omapdss.h> |
| 16 | |
| 17 | #include "dss.h" |
Archit Taneja | ef26958 | 2013-09-12 17:45:57 +0530 | [diff] [blame] | 18 | #include "hdmi.h" |
Archit Taneja | 5cac5ae | 2013-10-08 13:07:00 +0530 | [diff] [blame] | 19 | |
Archit Taneja | 5cac5ae | 2013-10-08 13:07:00 +0530 | [diff] [blame] | 20 | void hdmi_phy_dump(struct hdmi_phy_data *phy, struct seq_file *s) |
| 21 | { |
| 22 | #define DUMPPHY(r) seq_printf(s, "%-35s %08x\n", #r,\ |
| 23 | hdmi_read_reg(phy->base, r)) |
| 24 | |
| 25 | DUMPPHY(HDMI_TXPHY_TX_CTRL); |
| 26 | DUMPPHY(HDMI_TXPHY_DIGITAL_CTRL); |
| 27 | DUMPPHY(HDMI_TXPHY_POWER_CTRL); |
| 28 | DUMPPHY(HDMI_TXPHY_PAD_CFG_CTRL); |
| 29 | } |
| 30 | |
| 31 | static irqreturn_t hdmi_irq_handler(int irq, void *data) |
| 32 | { |
| 33 | struct hdmi_wp_data *wp = data; |
| 34 | u32 irqstatus; |
| 35 | |
| 36 | irqstatus = hdmi_wp_get_irqstatus(wp); |
| 37 | hdmi_wp_set_irqstatus(wp, irqstatus); |
| 38 | |
| 39 | if ((irqstatus & HDMI_IRQ_LINK_CONNECT) && |
| 40 | irqstatus & HDMI_IRQ_LINK_DISCONNECT) { |
| 41 | /* |
| 42 | * If we get both connect and disconnect interrupts at the same |
| 43 | * time, turn off the PHY, clear interrupts, and restart, which |
| 44 | * raises connect interrupt if a cable is connected, or nothing |
| 45 | * if cable is not connected. |
| 46 | */ |
| 47 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); |
| 48 | |
| 49 | hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT | |
| 50 | HDMI_IRQ_LINK_DISCONNECT); |
| 51 | |
| 52 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); |
| 53 | } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) { |
| 54 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON); |
| 55 | } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) { |
| 56 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); |
| 57 | } |
| 58 | |
| 59 | return IRQ_HANDLED; |
| 60 | } |
| 61 | |
| 62 | int hdmi_phy_enable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp, |
| 63 | struct hdmi_config *cfg) |
| 64 | { |
| 65 | u16 r = 0; |
| 66 | u32 irqstatus; |
| 67 | |
| 68 | hdmi_wp_clear_irqenable(wp, 0xffffffff); |
| 69 | |
| 70 | irqstatus = hdmi_wp_get_irqstatus(wp); |
| 71 | hdmi_wp_set_irqstatus(wp, irqstatus); |
| 72 | |
| 73 | r = hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON); |
| 74 | if (r) |
| 75 | return r; |
| 76 | |
| 77 | /* |
| 78 | * Read address 0 in order to get the SCP reset done completed |
| 79 | * Dummy access performed to make sure reset is done |
| 80 | */ |
| 81 | hdmi_read_reg(phy->base, HDMI_TXPHY_TX_CTRL); |
| 82 | |
| 83 | /* |
| 84 | * Write to phy address 0 to configure the clock |
| 85 | * use HFBITCLK write HDMI_TXPHY_TX_CONTROL_FREQOUT field |
| 86 | */ |
| 87 | REG_FLD_MOD(phy->base, HDMI_TXPHY_TX_CTRL, 0x1, 31, 30); |
| 88 | |
| 89 | /* Write to phy address 1 to start HDMI line (TXVALID and TMDSCLKEN) */ |
| 90 | hdmi_write_reg(phy->base, HDMI_TXPHY_DIGITAL_CTRL, 0xF0000000); |
| 91 | |
| 92 | /* Setup max LDO voltage */ |
| 93 | REG_FLD_MOD(phy->base, HDMI_TXPHY_POWER_CTRL, 0xB, 3, 0); |
| 94 | |
| 95 | /* Write to phy address 3 to change the polarity control */ |
| 96 | REG_FLD_MOD(phy->base, HDMI_TXPHY_PAD_CFG_CTRL, 0x1, 27, 27); |
| 97 | |
| 98 | r = request_threaded_irq(phy->irq, NULL, hdmi_irq_handler, |
| 99 | IRQF_ONESHOT, "OMAP HDMI", wp); |
| 100 | if (r) { |
| 101 | DSSERR("HDMI IRQ request failed\n"); |
| 102 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); |
| 103 | return r; |
| 104 | } |
| 105 | |
| 106 | hdmi_wp_set_irqenable(wp, |
| 107 | HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT); |
| 108 | |
| 109 | return 0; |
| 110 | } |
| 111 | |
| 112 | void hdmi_phy_disable(struct hdmi_phy_data *phy, struct hdmi_wp_data *wp) |
| 113 | { |
| 114 | free_irq(phy->irq, wp); |
| 115 | |
| 116 | hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF); |
| 117 | } |
| 118 | |
| 119 | #define PHY_OFFSET 0x300 |
| 120 | #define PHY_SIZE 0x100 |
| 121 | |
| 122 | int hdmi_phy_init(struct platform_device *pdev, struct hdmi_phy_data *phy) |
| 123 | { |
| 124 | struct resource *res; |
| 125 | struct resource temp_res; |
| 126 | |
Tomi Valkeinen | 7760150 | 2013-12-17 14:41:14 +0200 | [diff] [blame] | 127 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "phy"); |
Archit Taneja | 5cac5ae | 2013-10-08 13:07:00 +0530 | [diff] [blame] | 128 | if (!res) { |
| 129 | DSSDBG("can't get PHY mem resource by name\n"); |
| 130 | /* |
| 131 | * if hwmod/DT doesn't have the memory resource information |
| 132 | * split into HDMI sub blocks by name, we try again by getting |
| 133 | * the platform's first resource. this code will be removed when |
| 134 | * the driver can get the mem resources by name |
| 135 | */ |
| 136 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 137 | if (!res) { |
| 138 | DSSERR("can't get PHY mem resource\n"); |
| 139 | return -EINVAL; |
| 140 | } |
| 141 | |
| 142 | temp_res.start = res->start + PHY_OFFSET; |
| 143 | temp_res.end = temp_res.start + PHY_SIZE - 1; |
| 144 | res = &temp_res; |
| 145 | } |
| 146 | |
| 147 | phy->base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); |
| 148 | if (!phy->base) { |
| 149 | DSSERR("can't ioremap TX PHY\n"); |
| 150 | return -ENOMEM; |
| 151 | } |
| 152 | |
| 153 | phy->irq = platform_get_irq(pdev, 0); |
| 154 | if (phy->irq < 0) { |
| 155 | DSSERR("platform_get_irq failed\n"); |
| 156 | return -ENODEV; |
| 157 | } |
| 158 | |
| 159 | return 0; |
| 160 | } |