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gerrit-public.fairphone.software / kernel / msm-5.4 / 0007b9bdbef801a4f177899fa557997d2f06c36d / . / arch / mips / powertv / asic / irq_asic.c
blob: e5538243415576d121b1400aceadc726c6a7fec8 [file] [log] [blame]
David VomLehna3a0f8c2009-08-30 17:15:11 -0700[diff] [blame]1/*
2 * Portions copyright (C) 2005-2009 Scientific Atlanta
3 * Portions copyright (C) 2009 Cisco Systems, Inc.
4 *
5 * Modified from arch/mips/kernel/irq-rm7000.c:
6 * Copyright (C) 2003 Ralf Baechle
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13#include <linux/init.h>
14#include <linux/interrupt.h>
15#include <linux/kernel.h>
David Howellsca4d3e672010-10-07 14:08:54 +0100[diff] [blame]16#include <linux/irq.h>
David VomLehna3a0f8c2009-08-30 17:15:11 -0700[diff] [blame]17
18#include <asm/irq_cpu.h>
19#include <asm/mipsregs.h>
20#include <asm/system.h>
21
22#include <asm/mach-powertv/asic_regs.h>
23
24static inline void unmask_asic_irq(unsigned int irq)
25{
26 unsigned long enable_bit;
27
28 enable_bit = (1 << (irq & 0x1f));
29
30 switch (irq >> 5) {
31 case 0:
32 asic_write(asic_read(ien_int_0) | enable_bit, ien_int_0);
33 break;
34 case 1:
35 asic_write(asic_read(ien_int_1) | enable_bit, ien_int_1);
36 break;
37 case 2:
38 asic_write(asic_read(ien_int_2) | enable_bit, ien_int_2);
39 break;
40 case 3:
41 asic_write(asic_read(ien_int_3) | enable_bit, ien_int_3);
42 break;
43 default:
44 BUG();
45 }
46}
47
48static inline void mask_asic_irq(unsigned int irq)
49{
50 unsigned long disable_mask;
51
52 disable_mask = ~(1 << (irq & 0x1f));
53
54 switch (irq >> 5) {
55 case 0:
56 asic_write(asic_read(ien_int_0) & disable_mask, ien_int_0);
57 break;
58 case 1:
59 asic_write(asic_read(ien_int_1) & disable_mask, ien_int_1);
60 break;
61 case 2:
62 asic_write(asic_read(ien_int_2) & disable_mask, ien_int_2);
63 break;
64 case 3:
65 asic_write(asic_read(ien_int_3) & disable_mask, ien_int_3);
66 break;
67 default:
68 BUG();
69 }
70}
71
72static struct irq_chip asic_irq_chip = {
73 .name = "ASIC Level",
74 .ack = mask_asic_irq,
75 .mask = mask_asic_irq,
76 .mask_ack = mask_asic_irq,
77 .unmask = unmask_asic_irq,
78 .eoi = unmask_asic_irq,
79};
80
81void __init asic_irq_init(void)
82{
83 int i;
84
85 /* set priority to 0 */
86 write_c0_status(read_c0_status() & ~(0x0000fc00));
87
88 asic_write(0, ien_int_0);
89 asic_write(0, ien_int_1);
90 asic_write(0, ien_int_2);
91 asic_write(0, ien_int_3);
92
93 asic_write(0x0fffffff, int_level_3_3);
94 asic_write(0xffffffff, int_level_3_2);
95 asic_write(0xffffffff, int_level_3_1);
96 asic_write(0xffffffff, int_level_3_0);
97 asic_write(0xffffffff, int_level_2_3);
98 asic_write(0xffffffff, int_level_2_2);
99 asic_write(0xffffffff, int_level_2_1);
100 asic_write(0xffffffff, int_level_2_0);
101 asic_write(0xffffffff, int_level_1_3);
102 asic_write(0xffffffff, int_level_1_2);
103 asic_write(0xffffffff, int_level_1_1);
104 asic_write(0xffffffff, int_level_1_0);
105 asic_write(0xffffffff, int_level_0_3);
106 asic_write(0xffffffff, int_level_0_2);
107 asic_write(0xffffffff, int_level_0_1);
108 asic_write(0xffffffff, int_level_0_0);
109
110 asic_write(0xf, int_int_scan);
111
112 /*
113 * Initialize interrupt handlers.
114 */
115 for (i = 0; i < NR_IRQS; i++)
116 set_irq_chip_and_handler(i, &asic_irq_chip, handle_level_irq);
117}