Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-5.4 / d48071be6cb94912cf3c3ac0b4d520438fab4778 / . / drivers / net / can / c_can / c_can.h
blob: d9f59cc4fcb511cc4da3e85ddc501882f9b57b3e [file] [log] [blame]
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]1/*
2 * CAN bus driver for Bosch C_CAN controller
3 *
4 * Copyright (C) 2010 ST Microelectronics
5 * Bhupesh Sharma <bhupesh.sharma@st.com>
6 *
7 * Borrowed heavily from the C_CAN driver originally written by:
8 * Copyright (C) 2007
9 * - Sascha Hauer, Marc Kleine-Budde, Pengutronix <s.hauer@pengutronix.de>
10 * - Simon Kallweit, intefo AG <simon.kallweit@intefo.ch>
11 *
12 * Bosch C_CAN controller is compliant to CAN protocol version 2.0 part A and B.
13 * Bosch C_CAN user manual can be obtained from:
14 * http://www.semiconductors.bosch.de/media/en/pdf/ipmodules_1/c_can/
15 * users_manual_c_can.pdf
16 *
17 * This file is licensed under the terms of the GNU General Public
18 * License version 2. This program is licensed "as is" without any
19 * warranty of any kind, whether express or implied.
20 */
21
22#ifndef C_CAN_H
23#define C_CAN_H
24
Thomas Gleixner90247002014-03-18 17:19:14 +0000[diff] [blame]25/* message object split */
26#define C_CAN_NO_OF_OBJECTS 32
27#define C_CAN_MSG_OBJ_RX_NUM 16
28#define C_CAN_MSG_OBJ_TX_NUM 16
29
30#define C_CAN_MSG_OBJ_RX_FIRST 1
31#define C_CAN_MSG_OBJ_RX_LAST (C_CAN_MSG_OBJ_RX_FIRST + \
32 C_CAN_MSG_OBJ_RX_NUM - 1)
33
34#define C_CAN_MSG_OBJ_TX_FIRST (C_CAN_MSG_OBJ_RX_LAST + 1)
35#define C_CAN_MSG_OBJ_TX_LAST (C_CAN_MSG_OBJ_TX_FIRST + \
36 C_CAN_MSG_OBJ_TX_NUM - 1)
37
38#define C_CAN_MSG_OBJ_RX_SPLIT 9
39#define C_CAN_MSG_RX_LOW_LAST (C_CAN_MSG_OBJ_RX_SPLIT - 1)
40
41#define C_CAN_NEXT_MSG_OBJ_MASK (C_CAN_MSG_OBJ_TX_NUM - 1)
42#define RECEIVE_OBJECT_BITS 0x0000ffff
43
AnilKumar Ch33f81002012-05-29 11:13:15 +0530[diff] [blame]44enum reg {
45 C_CAN_CTRL_REG = 0,
AnilKumar Ch82120032012-09-21 15:29:01 +0530[diff] [blame]46 C_CAN_CTRL_EX_REG,
AnilKumar Ch33f81002012-05-29 11:13:15 +0530[diff] [blame]47 C_CAN_STS_REG,
48 C_CAN_ERR_CNT_REG,
49 C_CAN_BTR_REG,
50 C_CAN_INT_REG,
51 C_CAN_TEST_REG,
52 C_CAN_BRPEXT_REG,
53 C_CAN_IF1_COMREQ_REG,
54 C_CAN_IF1_COMMSK_REG,
55 C_CAN_IF1_MASK1_REG,
56 C_CAN_IF1_MASK2_REG,
57 C_CAN_IF1_ARB1_REG,
58 C_CAN_IF1_ARB2_REG,
59 C_CAN_IF1_MSGCTRL_REG,
60 C_CAN_IF1_DATA1_REG,
61 C_CAN_IF1_DATA2_REG,
62 C_CAN_IF1_DATA3_REG,
63 C_CAN_IF1_DATA4_REG,
64 C_CAN_IF2_COMREQ_REG,
65 C_CAN_IF2_COMMSK_REG,
66 C_CAN_IF2_MASK1_REG,
67 C_CAN_IF2_MASK2_REG,
68 C_CAN_IF2_ARB1_REG,
69 C_CAN_IF2_ARB2_REG,
70 C_CAN_IF2_MSGCTRL_REG,
71 C_CAN_IF2_DATA1_REG,
72 C_CAN_IF2_DATA2_REG,
73 C_CAN_IF2_DATA3_REG,
74 C_CAN_IF2_DATA4_REG,
75 C_CAN_TXRQST1_REG,
76 C_CAN_TXRQST2_REG,
77 C_CAN_NEWDAT1_REG,
78 C_CAN_NEWDAT2_REG,
79 C_CAN_INTPND1_REG,
80 C_CAN_INTPND2_REG,
81 C_CAN_MSGVAL1_REG,
82 C_CAN_MSGVAL2_REG,
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]83};
84
AnilKumar Ch33f81002012-05-29 11:13:15 +0530[diff] [blame]85static const u16 reg_map_c_can[] = {
86 [C_CAN_CTRL_REG] = 0x00,
87 [C_CAN_STS_REG] = 0x02,
88 [C_CAN_ERR_CNT_REG] = 0x04,
89 [C_CAN_BTR_REG] = 0x06,
90 [C_CAN_INT_REG] = 0x08,
91 [C_CAN_TEST_REG] = 0x0A,
92 [C_CAN_BRPEXT_REG] = 0x0C,
93 [C_CAN_IF1_COMREQ_REG] = 0x10,
94 [C_CAN_IF1_COMMSK_REG] = 0x12,
95 [C_CAN_IF1_MASK1_REG] = 0x14,
96 [C_CAN_IF1_MASK2_REG] = 0x16,
97 [C_CAN_IF1_ARB1_REG] = 0x18,
98 [C_CAN_IF1_ARB2_REG] = 0x1A,
99 [C_CAN_IF1_MSGCTRL_REG] = 0x1C,
100 [C_CAN_IF1_DATA1_REG] = 0x1E,
101 [C_CAN_IF1_DATA2_REG] = 0x20,
102 [C_CAN_IF1_DATA3_REG] = 0x22,
103 [C_CAN_IF1_DATA4_REG] = 0x24,
104 [C_CAN_IF2_COMREQ_REG] = 0x40,
105 [C_CAN_IF2_COMMSK_REG] = 0x42,
106 [C_CAN_IF2_MASK1_REG] = 0x44,
107 [C_CAN_IF2_MASK2_REG] = 0x46,
108 [C_CAN_IF2_ARB1_REG] = 0x48,
109 [C_CAN_IF2_ARB2_REG] = 0x4A,
110 [C_CAN_IF2_MSGCTRL_REG] = 0x4C,
111 [C_CAN_IF2_DATA1_REG] = 0x4E,
112 [C_CAN_IF2_DATA2_REG] = 0x50,
113 [C_CAN_IF2_DATA3_REG] = 0x52,
114 [C_CAN_IF2_DATA4_REG] = 0x54,
115 [C_CAN_TXRQST1_REG] = 0x80,
116 [C_CAN_TXRQST2_REG] = 0x82,
117 [C_CAN_NEWDAT1_REG] = 0x90,
118 [C_CAN_NEWDAT2_REG] = 0x92,
119 [C_CAN_INTPND1_REG] = 0xA0,
120 [C_CAN_INTPND2_REG] = 0xA2,
121 [C_CAN_MSGVAL1_REG] = 0xB0,
122 [C_CAN_MSGVAL2_REG] = 0xB2,
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]123};
124
AnilKumar Ch69927fc2012-05-29 11:13:16 +0530[diff] [blame]125static const u16 reg_map_d_can[] = {
126 [C_CAN_CTRL_REG] = 0x00,
AnilKumar Ch82120032012-09-21 15:29:01 +0530[diff] [blame]127 [C_CAN_CTRL_EX_REG] = 0x02,
AnilKumar Ch69927fc2012-05-29 11:13:16 +0530[diff] [blame]128 [C_CAN_STS_REG] = 0x04,
129 [C_CAN_ERR_CNT_REG] = 0x08,
130 [C_CAN_BTR_REG] = 0x0C,
131 [C_CAN_BRPEXT_REG] = 0x0E,
132 [C_CAN_INT_REG] = 0x10,
133 [C_CAN_TEST_REG] = 0x14,
134 [C_CAN_TXRQST1_REG] = 0x88,
135 [C_CAN_TXRQST2_REG] = 0x8A,
136 [C_CAN_NEWDAT1_REG] = 0x9C,
137 [C_CAN_NEWDAT2_REG] = 0x9E,
138 [C_CAN_INTPND1_REG] = 0xB0,
139 [C_CAN_INTPND2_REG] = 0xB2,
140 [C_CAN_MSGVAL1_REG] = 0xC4,
141 [C_CAN_MSGVAL2_REG] = 0xC6,
142 [C_CAN_IF1_COMREQ_REG] = 0x100,
143 [C_CAN_IF1_COMMSK_REG] = 0x102,
144 [C_CAN_IF1_MASK1_REG] = 0x104,
145 [C_CAN_IF1_MASK2_REG] = 0x106,
146 [C_CAN_IF1_ARB1_REG] = 0x108,
147 [C_CAN_IF1_ARB2_REG] = 0x10A,
148 [C_CAN_IF1_MSGCTRL_REG] = 0x10C,
149 [C_CAN_IF1_DATA1_REG] = 0x110,
150 [C_CAN_IF1_DATA2_REG] = 0x112,
151 [C_CAN_IF1_DATA3_REG] = 0x114,
152 [C_CAN_IF1_DATA4_REG] = 0x116,
153 [C_CAN_IF2_COMREQ_REG] = 0x120,
154 [C_CAN_IF2_COMMSK_REG] = 0x122,
155 [C_CAN_IF2_MASK1_REG] = 0x124,
156 [C_CAN_IF2_MASK2_REG] = 0x126,
157 [C_CAN_IF2_ARB1_REG] = 0x128,
158 [C_CAN_IF2_ARB2_REG] = 0x12A,
159 [C_CAN_IF2_MSGCTRL_REG] = 0x12C,
160 [C_CAN_IF2_DATA1_REG] = 0x130,
161 [C_CAN_IF2_DATA2_REG] = 0x132,
162 [C_CAN_IF2_DATA3_REG] = 0x134,
163 [C_CAN_IF2_DATA4_REG] = 0x136,
164};
165
166enum c_can_dev_id {
AnilKumar Chf27b1db2012-08-02 18:43:09 +0530[diff] [blame]167 BOSCH_C_CAN_PLATFORM,
168 BOSCH_C_CAN,
169 BOSCH_D_CAN,
AnilKumar Ch69927fc2012-05-29 11:13:16 +0530[diff] [blame]170};
171
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]172/* c_can private data structure */
173struct c_can_priv {
174 struct can_priv can; /* must be the first member */
175 struct napi_struct napi;
176 struct net_device *dev;
AnilKumar Ch4cdd34b2012-08-20 16:50:54 +0530[diff] [blame]177 struct device *device;
Thomas Gleixnerbf88a2062014-03-18 17:19:12 +0000[diff] [blame]178 spinlock_t xmit_lock;
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]179 int tx_object;
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]180 int last_status;
AnilKumar Ch33f81002012-05-29 11:13:15 +0530[diff] [blame]181 u16 (*read_reg) (struct c_can_priv *priv, enum reg index);
182 void (*write_reg) (struct c_can_priv *priv, enum reg index, u16 val);
183 void __iomem *base;
184 const u16 *regs;
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]185 unsigned long irq_flags; /* for request_irq() */
186 unsigned int tx_next;
187 unsigned int tx_echo;
188 void *priv; /* for board-specific data */
AnilKumar Ch82120032012-09-21 15:29:01 +0530[diff] [blame]189 enum c_can_dev_id type;
AnilKumar Ch52cde852012-11-21 11:14:10 +0530[diff] [blame]190 u32 __iomem *raminit_ctrlreg;
191 unsigned int instance;
192 void (*raminit) (const struct c_can_priv *priv, bool enable);
Thomas Gleixnerd61d09d2014-04-11 08:13:17 +0000[diff] [blame]193 u32 comm_rcv_high;
Thomas Gleixnerfa39b542014-04-11 08:13:15 +0000[diff] [blame]194 u32 rxmasked;
Thomas Gleixner90247002014-03-18 17:19:14 +0000[diff] [blame]195 u32 dlc[C_CAN_MSG_OBJ_TX_NUM];
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]196};
197
198struct net_device *alloc_c_can_dev(void);
199void free_c_can_dev(struct net_device *dev);
200int register_c_can_dev(struct net_device *dev);
201void unregister_c_can_dev(struct net_device *dev);
202
AnilKumar Ch82120032012-09-21 15:29:01 +0530[diff] [blame]203#ifdef CONFIG_PM
204int c_can_power_up(struct net_device *dev);
205int c_can_power_down(struct net_device *dev);
206#endif
207
Bhupesh Sharma881ff672011-02-13 22:51:44 -0800[diff] [blame]208#endif /* C_CAN_H */