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gerrit-public.fairphone.software / kernel / msm-5.4 / 868b83511ba92b24ce5c5d852cf16b1bc07e13a7 / . / drivers / gpu / drm / amd / include / atomfirmware.h
blob: 0f5ad54d3fd3d9c5e3700ec1d3e6324bf0436f4c [file] [log] [blame]
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1/****************************************************************************\
2*
3* File Name atomfirmware.h
4* Project This is an interface header file between atombios and OS GPU drivers for SoC15 products
5*
6* Description header file of general definitions for OS nd pre-OS video drivers
7*
8* Copyright 2014 Advanced Micro Devices, Inc.
9*
10* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
11* and associated documentation files (the "Software"), to deal in the Software without restriction,
12* including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense,
13* and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so,
14* subject to the following conditions:
15*
16* The above copyright notice and this permission notice shall be included in all copies or substantial
17* portions of the Software.
18*
19* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
23* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25* OTHER DEALINGS IN THE SOFTWARE.
26*
27\****************************************************************************/
28
29/*IMPORTANT NOTES
30* If a change in VBIOS/Driver/Tool's interface is only needed for SoC15 and forward products, then the change is only needed in this atomfirmware.h header file.
31* If a change in VBIOS/Driver/Tool's interface is only needed for pre-SoC15 products, then the change is only needed in atombios.h header file.
32* If a change is needed for both pre and post SoC15 products, then the change has to be made separately and might be differently in both atomfirmware.h and atombios.h.
33*/
34
35#ifndef _ATOMFIRMWARE_H_
36#define _ATOMFIRMWARE_H_
37
38enum atom_bios_header_version_def{
39 ATOM_MAJOR_VERSION =0x0003,
40 ATOM_MINOR_VERSION =0x0003,
41};
42
43#ifdef _H2INC
44 #ifndef uint32_t
45 typedef unsigned long uint32_t;
46 #endif
47
48 #ifndef uint16_t
49 typedef unsigned short uint16_t;
50 #endif
51
52 #ifndef uint8_t
53 typedef unsigned char uint8_t;
54 #endif
55#endif
56
57enum atom_crtc_def{
58 ATOM_CRTC1 =0,
59 ATOM_CRTC2 =1,
60 ATOM_CRTC3 =2,
61 ATOM_CRTC4 =3,
62 ATOM_CRTC5 =4,
63 ATOM_CRTC6 =5,
64 ATOM_CRTC_INVALID =0xff,
65};
66
67enum atom_ppll_def{
68 ATOM_PPLL0 =2,
69 ATOM_GCK_DFS =8,
70 ATOM_FCH_CLK =9,
71 ATOM_DP_DTO =11,
72 ATOM_COMBOPHY_PLL0 =20,
73 ATOM_COMBOPHY_PLL1 =21,
74 ATOM_COMBOPHY_PLL2 =22,
75 ATOM_COMBOPHY_PLL3 =23,
76 ATOM_COMBOPHY_PLL4 =24,
77 ATOM_COMBOPHY_PLL5 =25,
78 ATOM_PPLL_INVALID =0xff,
79};
80
81// define ASIC internal encoder id ( bit vector ), used for CRTC_SourceSel
82enum atom_dig_def{
83 ASIC_INT_DIG1_ENCODER_ID =0x03,
84 ASIC_INT_DIG2_ENCODER_ID =0x09,
85 ASIC_INT_DIG3_ENCODER_ID =0x0a,
86 ASIC_INT_DIG4_ENCODER_ID =0x0b,
87 ASIC_INT_DIG5_ENCODER_ID =0x0c,
88 ASIC_INT_DIG6_ENCODER_ID =0x0d,
89 ASIC_INT_DIG7_ENCODER_ID =0x0e,
90};
91
92//ucEncoderMode
93enum atom_encode_mode_def
94{
95 ATOM_ENCODER_MODE_DP =0,
96 ATOM_ENCODER_MODE_DP_SST =0,
97 ATOM_ENCODER_MODE_LVDS =1,
98 ATOM_ENCODER_MODE_DVI =2,
99 ATOM_ENCODER_MODE_HDMI =3,
100 ATOM_ENCODER_MODE_DP_AUDIO =5,
101 ATOM_ENCODER_MODE_DP_MST =5,
102 ATOM_ENCODER_MODE_CRT =15,
103 ATOM_ENCODER_MODE_DVO =16,
104};
105
106enum atom_encoder_refclk_src_def{
107 ENCODER_REFCLK_SRC_P1PLL =0,
108 ENCODER_REFCLK_SRC_P2PLL =1,
109 ENCODER_REFCLK_SRC_P3PLL =2,
110 ENCODER_REFCLK_SRC_EXTCLK =3,
111 ENCODER_REFCLK_SRC_INVALID =0xff,
112};
113
114enum atom_scaler_def{
115 ATOM_SCALER_DISABLE =0, /*scaler bypass mode, auto-center & no replication*/
116 ATOM_SCALER_CENTER =1, //For Fudo, it's bypass and auto-center & auto replication
117 ATOM_SCALER_EXPANSION =2, /*scaler expansion by 2 tap alpha blending mode*/
118};
119
120enum atom_operation_def{
121 ATOM_DISABLE = 0,
122 ATOM_ENABLE = 1,
123 ATOM_INIT = 7,
124 ATOM_GET_STATUS = 8,
125};
126
127enum atom_embedded_display_op_def{
128 ATOM_LCD_BL_OFF = 2,
129 ATOM_LCD_BL_OM = 3,
130 ATOM_LCD_BL_BRIGHTNESS_CONTROL = 4,
131 ATOM_LCD_SELFTEST_START = 5,
132 ATOM_LCD_SELFTEST_STOP = 6,
133};
134
135enum atom_spread_spectrum_mode{
136 ATOM_SS_CENTER_OR_DOWN_MODE_MASK = 0x01,
137 ATOM_SS_DOWN_SPREAD_MODE = 0x00,
138 ATOM_SS_CENTRE_SPREAD_MODE = 0x01,
139 ATOM_INT_OR_EXT_SS_MASK = 0x02,
140 ATOM_INTERNAL_SS_MASK = 0x00,
141 ATOM_EXTERNAL_SS_MASK = 0x02,
142};
143
144/* define panel bit per color */
145enum atom_panel_bit_per_color{
146 PANEL_BPC_UNDEFINE =0x00,
147 PANEL_6BIT_PER_COLOR =0x01,
148 PANEL_8BIT_PER_COLOR =0x02,
149 PANEL_10BIT_PER_COLOR =0x03,
150 PANEL_12BIT_PER_COLOR =0x04,
151 PANEL_16BIT_PER_COLOR =0x05,
152};
153
154//ucVoltageType
155enum atom_voltage_type
156{
157 VOLTAGE_TYPE_VDDC = 1,
158 VOLTAGE_TYPE_MVDDC = 2,
159 VOLTAGE_TYPE_MVDDQ = 3,
160 VOLTAGE_TYPE_VDDCI = 4,
161 VOLTAGE_TYPE_VDDGFX = 5,
162 VOLTAGE_TYPE_PCC = 6,
163 VOLTAGE_TYPE_MVPP = 7,
164 VOLTAGE_TYPE_LEDDPM = 8,
165 VOLTAGE_TYPE_PCC_MVDD = 9,
166 VOLTAGE_TYPE_PCIE_VDDC = 10,
167 VOLTAGE_TYPE_PCIE_VDDR = 11,
168 VOLTAGE_TYPE_GENERIC_I2C_1 = 0x11,
169 VOLTAGE_TYPE_GENERIC_I2C_2 = 0x12,
170 VOLTAGE_TYPE_GENERIC_I2C_3 = 0x13,
171 VOLTAGE_TYPE_GENERIC_I2C_4 = 0x14,
172 VOLTAGE_TYPE_GENERIC_I2C_5 = 0x15,
173 VOLTAGE_TYPE_GENERIC_I2C_6 = 0x16,
174 VOLTAGE_TYPE_GENERIC_I2C_7 = 0x17,
175 VOLTAGE_TYPE_GENERIC_I2C_8 = 0x18,
176 VOLTAGE_TYPE_GENERIC_I2C_9 = 0x19,
177 VOLTAGE_TYPE_GENERIC_I2C_10 = 0x1A,
178};
179
180enum atom_dgpu_vram_type{
181 ATOM_DGPU_VRAM_TYPE_GDDR5 = 0x50,
182 ATOM_DGPU_VRAM_TYPE_HBM = 0x60,
183};
184
185enum atom_dp_vs_preemph_def{
186 DP_VS_LEVEL0_PREEMPH_LEVEL0 = 0x00,
187 DP_VS_LEVEL1_PREEMPH_LEVEL0 = 0x01,
188 DP_VS_LEVEL2_PREEMPH_LEVEL0 = 0x02,
189 DP_VS_LEVEL3_PREEMPH_LEVEL0 = 0x03,
190 DP_VS_LEVEL0_PREEMPH_LEVEL1 = 0x08,
191 DP_VS_LEVEL1_PREEMPH_LEVEL1 = 0x09,
192 DP_VS_LEVEL2_PREEMPH_LEVEL1 = 0x0a,
193 DP_VS_LEVEL0_PREEMPH_LEVEL2 = 0x10,
194 DP_VS_LEVEL1_PREEMPH_LEVEL2 = 0x11,
195 DP_VS_LEVEL0_PREEMPH_LEVEL3 = 0x18,
196};
197
198
199/*
200enum atom_string_def{
201asic_bus_type_pcie_string = "PCI_EXPRESS",
202atom_fire_gl_string = "FGL",
203atom_bios_string = "ATOM"
204};
205*/
206
207#pragma pack(1) /* BIOS data must use byte aligment*/
208
209enum atombios_image_offset{
210OFFSET_TO_ATOM_ROM_HEADER_POINTER =0x00000048,
211OFFSET_TO_ATOM_ROM_IMAGE_SIZE =0x00000002,
212OFFSET_TO_ATOMBIOS_ASIC_BUS_MEM_TYPE =0x94,
213MAXSIZE_OF_ATOMBIOS_ASIC_BUS_MEM_TYPE =20, /*including the terminator 0x0!*/
214OFFSET_TO_GET_ATOMBIOS_NUMBER_OF_STRINGS =0x2f,
215OFFSET_TO_GET_ATOMBIOS_STRING_START =0x6e,
216};
217
218/****************************************************************************
219* Common header for all tables (Data table, Command function).
220* Every table pointed in _ATOM_MASTER_DATA_TABLE has this common header.
221* And the pointer actually points to this header.
222****************************************************************************/
223
224struct atom_common_table_header
225{
226 uint16_t structuresize;
227 uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compatible
228 uint8_t content_revision; //change it when a data table has a structure change, or a hw function has a input/output parameter change
229};
230
231/****************************************************************************
232* Structure stores the ROM header.
233****************************************************************************/
234struct atom_rom_header_v2_2
235{
236 struct atom_common_table_header table_header;
237 uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to distinguish between Atombios and non-atombios,
238 uint16_t bios_segment_address;
239 uint16_t protectedmodeoffset;
240 uint16_t configfilenameoffset;
241 uint16_t crc_block_offset;
242 uint16_t vbios_bootupmessageoffset;
243 uint16_t int10_offset;
244 uint16_t pcibusdevinitcode;
245 uint16_t iobaseaddress;
246 uint16_t subsystem_vendor_id;
247 uint16_t subsystem_id;
248 uint16_t pci_info_offset;
249 uint16_t masterhwfunction_offset; //Offest for SW to get all command function offsets, Don't change the position
250 uint16_t masterdatatable_offset; //Offest for SW to get all data table offsets, Don't change the position
251 uint16_t reserved;
252 uint32_t pspdirtableoffset;
253};
254
255/*==============================hw function portion======================================================================*/
256
257
258/****************************************************************************
259* Structures used in Command.mtb, each function name is not given here since those function could change from time to time
260* The real functionality of each function is associated with the parameter structure version when defined
261* For all internal cmd function definitions, please reference to atomstruct.h
262****************************************************************************/
263struct atom_master_list_of_command_functions_v2_1{
264 uint16_t asic_init; //Function
265 uint16_t cmd_function1; //used as an internal one
266 uint16_t cmd_function2; //used as an internal one
267 uint16_t cmd_function3; //used as an internal one
268 uint16_t digxencodercontrol; //Function
269 uint16_t cmd_function5; //used as an internal one
270 uint16_t cmd_function6; //used as an internal one
271 uint16_t cmd_function7; //used as an internal one
272 uint16_t cmd_function8; //used as an internal one
273 uint16_t cmd_function9; //used as an internal one
274 uint16_t setengineclock; //Function
275 uint16_t setmemoryclock; //Function
276 uint16_t setpixelclock; //Function
277 uint16_t enabledisppowergating; //Function
278 uint16_t cmd_function14; //used as an internal one
279 uint16_t cmd_function15; //used as an internal one
280 uint16_t cmd_function16; //used as an internal one
281 uint16_t cmd_function17; //used as an internal one
282 uint16_t cmd_function18; //used as an internal one
283 uint16_t cmd_function19; //used as an internal one
284 uint16_t cmd_function20; //used as an internal one
285 uint16_t cmd_function21; //used as an internal one
286 uint16_t cmd_function22; //used as an internal one
287 uint16_t cmd_function23; //used as an internal one
288 uint16_t cmd_function24; //used as an internal one
289 uint16_t cmd_function25; //used as an internal one
290 uint16_t cmd_function26; //used as an internal one
291 uint16_t cmd_function27; //used as an internal one
292 uint16_t cmd_function28; //used as an internal one
293 uint16_t cmd_function29; //used as an internal one
294 uint16_t cmd_function30; //used as an internal one
295 uint16_t cmd_function31; //used as an internal one
296 uint16_t cmd_function32; //used as an internal one
297 uint16_t cmd_function33; //used as an internal one
298 uint16_t blankcrtc; //Function
299 uint16_t enablecrtc; //Function
300 uint16_t cmd_function36; //used as an internal one
301 uint16_t cmd_function37; //used as an internal one
302 uint16_t cmd_function38; //used as an internal one
303 uint16_t cmd_function39; //used as an internal one
304 uint16_t cmd_function40; //used as an internal one
305 uint16_t getsmuclockinfo; //Function
306 uint16_t selectcrtc_source; //Function
307 uint16_t cmd_function43; //used as an internal one
308 uint16_t cmd_function44; //used as an internal one
309 uint16_t cmd_function45; //used as an internal one
310 uint16_t setdceclock; //Function
311 uint16_t getmemoryclock; //Function
312 uint16_t getengineclock; //Function
313 uint16_t setcrtc_usingdtdtiming; //Function
314 uint16_t externalencodercontrol; //Function
315 uint16_t cmd_function51; //used as an internal one
316 uint16_t cmd_function52; //used as an internal one
317 uint16_t cmd_function53; //used as an internal one
318 uint16_t processi2cchanneltransaction;//Function
319 uint16_t cmd_function55; //used as an internal one
320 uint16_t cmd_function56; //used as an internal one
321 uint16_t cmd_function57; //used as an internal one
322 uint16_t cmd_function58; //used as an internal one
323 uint16_t cmd_function59; //used as an internal one
324 uint16_t computegpuclockparam; //Function
325 uint16_t cmd_function61; //used as an internal one
326 uint16_t cmd_function62; //used as an internal one
327 uint16_t dynamicmemorysettings; //Function function
328 uint16_t memorytraining; //Function function
329 uint16_t cmd_function65; //used as an internal one
330 uint16_t cmd_function66; //used as an internal one
331 uint16_t setvoltage; //Function
332 uint16_t cmd_function68; //used as an internal one
333 uint16_t readefusevalue; //Function
334 uint16_t cmd_function70; //used as an internal one
335 uint16_t cmd_function71; //used as an internal one
336 uint16_t cmd_function72; //used as an internal one
337 uint16_t cmd_function73; //used as an internal one
338 uint16_t cmd_function74; //used as an internal one
339 uint16_t cmd_function75; //used as an internal one
340 uint16_t dig1transmittercontrol; //Function
341 uint16_t cmd_function77; //used as an internal one
342 uint16_t processauxchanneltransaction;//Function
343 uint16_t cmd_function79; //used as an internal one
344 uint16_t getvoltageinfo; //Function
345};
346
347struct atom_master_command_function_v2_1
348{
349 struct atom_common_table_header table_header;
350 struct atom_master_list_of_command_functions_v2_1 listofcmdfunctions;
351};
352
353/****************************************************************************
354* Structures used in every command function
355****************************************************************************/
356struct atom_function_attribute
357{
358 uint16_t ws_in_bytes:8; //[7:0]=Size of workspace in Bytes (in multiple of a dword),
359 uint16_t ps_in_bytes:7; //[14:8]=Size of parameter space in Bytes (multiple of a dword),
360 uint16_t updated_by_util:1; //[15]=flag to indicate the function is updated by util
361};
362
363
364/****************************************************************************
365* Common header for all hw functions.
366* Every function pointed by _master_list_of_hw_function has this common header.
367* And the pointer actually points to this header.
368****************************************************************************/
369struct atom_rom_hw_function_header
370{
371 struct atom_common_table_header func_header;
372 struct atom_function_attribute func_attrib;
373};
374
375
376/*==============================sw data table portion======================================================================*/
377/****************************************************************************
378* Structures used in data.mtb, each data table name is not given here since those data table could change from time to time
379* The real name of each table is given when its data structure version is defined
380****************************************************************************/
381struct atom_master_list_of_data_tables_v2_1{
382 uint16_t utilitypipeline; /* Offest for the utility to get parser info,Don't change this position!*/
383 uint16_t multimedia_info;
Evan Quanf3f88642017-12-25 10:13:31 +0800[diff] [blame]384 uint16_t smc_dpm_info;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]385 uint16_t sw_datatable3;
386 uint16_t firmwareinfo; /* Shared by various SW components */
387 uint16_t sw_datatable5;
388 uint16_t lcd_info; /* Shared by various SW components */
389 uint16_t sw_datatable7;
390 uint16_t smu_info;
391 uint16_t sw_datatable9;
392 uint16_t sw_datatable10;
393 uint16_t vram_usagebyfirmware; /* Shared by various SW components */
394 uint16_t gpio_pin_lut; /* Shared by various SW components */
395 uint16_t sw_datatable13;
396 uint16_t gfx_info;
397 uint16_t powerplayinfo; /* Shared by various SW components */
398 uint16_t sw_datatable16;
399 uint16_t sw_datatable17;
400 uint16_t sw_datatable18;
401 uint16_t sw_datatable19;
402 uint16_t sw_datatable20;
403 uint16_t sw_datatable21;
404 uint16_t displayobjectinfo; /* Shared by various SW components */
405 uint16_t indirectioaccess; /* used as an internal one */
406 uint16_t umc_info; /* Shared by various SW components */
407 uint16_t sw_datatable25;
408 uint16_t sw_datatable26;
409 uint16_t dce_info; /* Shared by various SW components */
410 uint16_t vram_info; /* Shared by various SW components */
411 uint16_t sw_datatable29;
412 uint16_t integratedsysteminfo; /* Shared by various SW components */
413 uint16_t asic_profiling_info; /* Shared by various SW components */
414 uint16_t voltageobject_info; /* shared by various SW components */
415 uint16_t sw_datatable33;
416 uint16_t sw_datatable34;
417};
418
419
420struct atom_master_data_table_v2_1
421{
422 struct atom_common_table_header table_header;
423 struct atom_master_list_of_data_tables_v2_1 listOfdatatables;
424};
425
426
427struct atom_dtd_format
428{
429 uint16_t pixclk;
430 uint16_t h_active;
431 uint16_t h_blanking_time;
432 uint16_t v_active;
433 uint16_t v_blanking_time;
434 uint16_t h_sync_offset;
435 uint16_t h_sync_width;
436 uint16_t v_sync_offset;
437 uint16_t v_syncwidth;
438 uint16_t reserved;
439 uint16_t reserved0;
440 uint8_t h_border;
441 uint8_t v_border;
442 uint16_t miscinfo;
443 uint8_t atom_mode_id;
444 uint8_t refreshrate;
445};
446
447/* atom_dtd_format.modemiscinfo defintion */
448enum atom_dtd_format_modemiscinfo{
449 ATOM_HSYNC_POLARITY = 0x0002,
450 ATOM_VSYNC_POLARITY = 0x0004,
451 ATOM_H_REPLICATIONBY2 = 0x0010,
452 ATOM_V_REPLICATIONBY2 = 0x0020,
453 ATOM_INTERLACE = 0x0080,
454 ATOM_COMPOSITESYNC = 0x0040,
455};
456
457
458/* utilitypipeline
459 * when format_revision==1 && content_revision==1, then this an info table for atomworks to use during debug session, no structure is associated with it.
460 * the location of it can't change
461*/
462
463
464/*
465 ***************************************************************************
466 Data Table firmwareinfo structure
467 ***************************************************************************
468*/
469
470struct atom_firmware_info_v3_1
471{
472 struct atom_common_table_header table_header;
473 uint32_t firmware_revision;
474 uint32_t bootup_sclk_in10khz;
475 uint32_t bootup_mclk_in10khz;
476 uint32_t firmware_capability; // enum atombios_firmware_capability
477 uint32_t main_call_parser_entry; /* direct address of main parser call in VBIOS binary. */
478 uint32_t bios_scratch_reg_startaddr; // 1st bios scratch register dword address
479 uint16_t bootup_vddc_mv;
480 uint16_t bootup_vddci_mv;
481 uint16_t bootup_mvddc_mv;
482 uint16_t bootup_vddgfx_mv;
483 uint8_t mem_module_id;
484 uint8_t coolingsolution_id; /*0: Air cooling; 1: Liquid cooling ... */
485 uint8_t reserved1[2];
486 uint32_t mc_baseaddr_high;
487 uint32_t mc_baseaddr_low;
488 uint32_t reserved2[6];
489};
490
491/* Total 32bit cap indication */
492enum atombios_firmware_capability
493{
494 ATOM_FIRMWARE_CAP_FIRMWARE_POSTED = 0x00000001,
495 ATOM_FIRMWARE_CAP_GPU_VIRTUALIZATION = 0x00000002,
496 ATOM_FIRMWARE_CAP_WMI_SUPPORT = 0x00000040,
497};
498
499enum atom_cooling_solution_id{
500 AIR_COOLING = 0x00,
501 LIQUID_COOLING = 0x01
502};
503
504
505/*
506 ***************************************************************************
507 Data Table lcd_info structure
508 ***************************************************************************
509*/
510
511struct lcd_info_v2_1
512{
513 struct atom_common_table_header table_header;
514 struct atom_dtd_format lcd_timing;
515 uint16_t backlight_pwm;
516 uint16_t special_handle_cap;
517 uint16_t panel_misc;
518 uint16_t lvds_max_slink_pclk;
519 uint16_t lvds_ss_percentage;
520 uint16_t lvds_ss_rate_10hz;
521 uint8_t pwr_on_digon_to_de; /*all pwr sequence numbers below are in uint of 4ms*/
522 uint8_t pwr_on_de_to_vary_bl;
523 uint8_t pwr_down_vary_bloff_to_de;
524 uint8_t pwr_down_de_to_digoff;
525 uint8_t pwr_off_delay;
526 uint8_t pwr_on_vary_bl_to_blon;
527 uint8_t pwr_down_bloff_to_vary_bloff;
528 uint8_t panel_bpc;
529 uint8_t dpcd_edp_config_cap;
530 uint8_t dpcd_max_link_rate;
531 uint8_t dpcd_max_lane_count;
532 uint8_t dpcd_max_downspread;
533 uint8_t min_allowed_bl_level;
534 uint8_t max_allowed_bl_level;
535 uint8_t bootup_bl_level;
536 uint8_t dplvdsrxid;
537 uint32_t reserved1[8];
538};
539
540/* lcd_info_v2_1.panel_misc defintion */
541enum atom_lcd_info_panel_misc{
542 ATOM_PANEL_MISC_FPDI =0x0002,
543};
544
545//uceDPToLVDSRxId
546enum atom_lcd_info_dptolvds_rx_id
547{
548 eDP_TO_LVDS_RX_DISABLE = 0x00, // no eDP->LVDS translator chip
549 eDP_TO_LVDS_COMMON_ID = 0x01, // common eDP->LVDS translator chip without AMD SW init
550 eDP_TO_LVDS_REALTEK_ID = 0x02, // Realtek tansaltor which require AMD SW init
551};
552
553
554/*
555 ***************************************************************************
556 Data Table gpio_pin_lut structure
557 ***************************************************************************
558*/
559
560struct atom_gpio_pin_assignment
561{
562 uint32_t data_a_reg_index;
563 uint8_t gpio_bitshift;
564 uint8_t gpio_mask_bitshift;
565 uint8_t gpio_id;
566 uint8_t reserved;
567};
568
569/* atom_gpio_pin_assignment.gpio_id definition */
570enum atom_gpio_pin_assignment_gpio_id {
571 I2C_HW_LANE_MUX =0x0f, /* only valid when bit7=1 */
572 I2C_HW_ENGINE_ID_MASK =0x70, /* only valid when bit7=1 */
573 I2C_HW_CAP =0x80, /*only when the I2C_HW_CAP is set, the pin ID is assigned to an I2C pin pair, otherwise, it's an generic GPIO pin */
574
575 /* gpio_id pre-define id for multiple usage */
576 /* GPIO use to control PCIE_VDDC in certain SLT board */
577 PCIE_VDDC_CONTROL_GPIO_PINID = 56,
578 /* if PP_AC_DC_SWITCH_GPIO_PINID in Gpio_Pin_LutTable, AC/DC swithing feature is enable */
579 PP_AC_DC_SWITCH_GPIO_PINID = 60,
580 /* VDDC_REGULATOR_VRHOT_GPIO_PINID in Gpio_Pin_LutTable, VRHot feature is enable */
581 VDDC_VRHOT_GPIO_PINID = 61,
582 /*if VDDC_PCC_GPIO_PINID in GPIO_LUTable, Peak Current Control feature is enabled */
583 VDDC_PCC_GPIO_PINID = 62,
584 /* Only used on certain SLT/PA board to allow utility to cut Efuse. */
585 EFUSE_CUT_ENABLE_GPIO_PINID = 63,
586 /* ucGPIO=DRAM_SELF_REFRESH_GPIO_PIND uses for memory self refresh (ucGPIO=0, DRAM self-refresh; ucGPIO= */
587 DRAM_SELF_REFRESH_GPIO_PINID = 64,
588 /* Thermal interrupt output->system thermal chip GPIO pin */
589 THERMAL_INT_OUTPUT_GPIO_PINID =65,
590};
591
592
593struct atom_gpio_pin_lut_v2_1
594{
595 struct atom_common_table_header table_header;
596 /*the real number of this included in the structure is calcualted by using the (whole structure size - the header size)/size of atom_gpio_pin_lut */
597 struct atom_gpio_pin_assignment gpio_pin[8];
598};
599
600
601/*
602 ***************************************************************************
603 Data Table vram_usagebyfirmware structure
604 ***************************************************************************
605*/
606
607struct vram_usagebyfirmware_v2_1
608{
609 struct atom_common_table_header table_header;
610 uint32_t start_address_in_kb;
611 uint16_t used_by_firmware_in_kb;
612 uint16_t used_by_driver_in_kb;
613};
614
615
616/*
617 ***************************************************************************
618 Data Table displayobjectinfo structure
619 ***************************************************************************
620*/
621
622enum atom_object_record_type_id
623{
624 ATOM_I2C_RECORD_TYPE =1,
625 ATOM_HPD_INT_RECORD_TYPE =2,
626 ATOM_OBJECT_GPIO_CNTL_RECORD_TYPE =9,
627 ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE =16,
628 ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE =17,
629 ATOM_ENCODER_CAP_RECORD_TYPE=20,
630 ATOM_BRACKET_LAYOUT_RECORD_TYPE=21,
631 ATOM_CONNECTOR_FORCED_TMDS_CAP_RECORD_TYPE=22,
632 ATOM_RECORD_END_TYPE =0xFF,
633};
634
635struct atom_common_record_header
636{
637 uint8_t record_type; //An emun to indicate the record type
638 uint8_t record_size; //The size of the whole record in byte
639};
640
641struct atom_i2c_record
642{
643 struct atom_common_record_header record_header; //record_type = ATOM_I2C_RECORD_TYPE
644 uint8_t i2c_id;
645 uint8_t i2c_slave_addr; //The slave address, it's 0 when the record is attached to connector for DDC
646};
647
648struct atom_hpd_int_record
649{
650 struct atom_common_record_header record_header; //record_type = ATOM_HPD_INT_RECORD_TYPE
651 uint8_t pin_id; //Corresponding block in GPIO_PIN_INFO table gives the pin info
652 uint8_t plugin_pin_state;
653};
654
655// Bit maps for ATOM_ENCODER_CAP_RECORD.usEncoderCap
656enum atom_encoder_caps_def
657{
658 ATOM_ENCODER_CAP_RECORD_HBR2 =0x01, // DP1.2 HBR2 is supported by HW encoder, it is retired in NI. the real meaning from SI is MST_EN
659 ATOM_ENCODER_CAP_RECORD_MST_EN =0x01, // from SI, this bit means DP MST is enable or not.
660 ATOM_ENCODER_CAP_RECORD_HBR2_EN =0x02, // DP1.2 HBR2 setting is qualified and HBR2 can be enabled
661 ATOM_ENCODER_CAP_RECORD_HDMI6Gbps_EN =0x04, // HDMI2.0 6Gbps enable or not.
662 ATOM_ENCODER_CAP_RECORD_HBR3_EN =0x08, // DP1.3 HBR3 is supported by board.
663};
664
665struct atom_encoder_caps_record
666{
667 struct atom_common_record_header record_header; //record_type = ATOM_ENCODER_CAP_RECORD_TYPE
668 uint32_t encodercaps;
669};
670
671enum atom_connector_caps_def
672{
673 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY = 0x01, //a cap bit to indicate that this non-embedded display connector is an internal display
674 ATOM_CONNECTOR_CAP_INTERNAL_DISPLAY_BL = 0x02, //a cap bit to indicate that this internal display requires BL control from GPU, refers to lcd_info for BL PWM freq
675};
676
677struct atom_disp_connector_caps_record
678{
679 struct atom_common_record_header record_header;
680 uint32_t connectcaps;
681};
682
683//The following generic object gpio pin control record type will replace JTAG_RECORD/FPGA_CONTROL_RECORD/DVI_EXT_INPUT_RECORD above gradually
684struct atom_gpio_pin_control_pair
685{
686 uint8_t gpio_id; // GPIO_ID, find the corresponding ID in GPIO_LUT table
687 uint8_t gpio_pinstate; // Pin state showing how to set-up the pin
688};
689
690struct atom_object_gpio_cntl_record
691{
692 struct atom_common_record_header record_header;
693 uint8_t flag; // Future expnadibility
694 uint8_t number_of_pins; // Number of GPIO pins used to control the object
695 struct atom_gpio_pin_control_pair gpio[1]; // the real gpio pin pair determined by number of pins ucNumberOfPins
696};
697
698//Definitions for GPIO pin state
699enum atom_gpio_pin_control_pinstate_def
700{
701 GPIO_PIN_TYPE_INPUT = 0x00,
702 GPIO_PIN_TYPE_OUTPUT = 0x10,
703 GPIO_PIN_TYPE_HW_CONTROL = 0x20,
704
705//For GPIO_PIN_TYPE_OUTPUT the following is defined
706 GPIO_PIN_OUTPUT_STATE_MASK = 0x01,
707 GPIO_PIN_OUTPUT_STATE_SHIFT = 0,
708 GPIO_PIN_STATE_ACTIVE_LOW = 0x0,
709 GPIO_PIN_STATE_ACTIVE_HIGH = 0x1,
710};
711
712// Indexes to GPIO array in GLSync record
713// GLSync record is for Frame Lock/Gen Lock feature.
714enum atom_glsync_record_gpio_index_def
715{
716 ATOM_GPIO_INDEX_GLSYNC_REFCLK = 0,
717 ATOM_GPIO_INDEX_GLSYNC_HSYNC = 1,
718 ATOM_GPIO_INDEX_GLSYNC_VSYNC = 2,
719 ATOM_GPIO_INDEX_GLSYNC_SWAP_REQ = 3,
720 ATOM_GPIO_INDEX_GLSYNC_SWAP_GNT = 4,
721 ATOM_GPIO_INDEX_GLSYNC_INTERRUPT = 5,
722 ATOM_GPIO_INDEX_GLSYNC_V_RESET = 6,
723 ATOM_GPIO_INDEX_GLSYNC_SWAP_CNTL = 7,
724 ATOM_GPIO_INDEX_GLSYNC_SWAP_SEL = 8,
725 ATOM_GPIO_INDEX_GLSYNC_MAX = 9,
726};
727
728
729struct atom_connector_hpdpin_lut_record //record for ATOM_CONNECTOR_HPDPIN_LUT_RECORD_TYPE
730{
731 struct atom_common_record_header record_header;
732 uint8_t hpd_pin_map[8];
733};
734
735struct atom_connector_auxddc_lut_record //record for ATOM_CONNECTOR_AUXDDC_LUT_RECORD_TYPE
736{
737 struct atom_common_record_header record_header;
738 uint8_t aux_ddc_map[8];
739};
740
741struct atom_connector_forced_tmds_cap_record
742{
743 struct atom_common_record_header record_header;
744 // override TMDS capability on this connector when it operate in TMDS mode. usMaxTmdsClkRate = max TMDS Clock in Mhz/2.5
745 uint8_t maxtmdsclkrate_in2_5mhz;
746 uint8_t reserved;
747};
748
749struct atom_connector_layout_info
750{
751 uint16_t connectorobjid;
752 uint8_t connector_type;
753 uint8_t position;
754};
755
756// define ATOM_CONNECTOR_LAYOUT_INFO.ucConnectorType to describe the display connector size
757enum atom_connector_layout_info_connector_type_def
758{
759 CONNECTOR_TYPE_DVI_D = 1,
760
761 CONNECTOR_TYPE_HDMI = 4,
762 CONNECTOR_TYPE_DISPLAY_PORT = 5,
763 CONNECTOR_TYPE_MINI_DISPLAY_PORT = 6,
764};
765
766struct atom_bracket_layout_record
767{
768 struct atom_common_record_header record_header;
769 uint8_t bracketlen;
770 uint8_t bracketwidth;
771 uint8_t conn_num;
772 uint8_t reserved;
773 struct atom_connector_layout_info conn_info[1];
774};
775
776enum atom_display_device_tag_def{
777 ATOM_DISPLAY_LCD1_SUPPORT = 0x0002, //an embedded display is either an LVDS or eDP signal type of display
778 ATOM_DISPLAY_DFP1_SUPPORT = 0x0008,
779 ATOM_DISPLAY_DFP2_SUPPORT = 0x0080,
780 ATOM_DISPLAY_DFP3_SUPPORT = 0x0200,
781 ATOM_DISPLAY_DFP4_SUPPORT = 0x0400,
782 ATOM_DISPLAY_DFP5_SUPPORT = 0x0800,
783 ATOM_DISPLAY_DFP6_SUPPORT = 0x0040,
784 ATOM_DISPLAY_DFPx_SUPPORT = 0x0ec8,
785};
786
787struct atom_display_object_path_v2
788{
789 uint16_t display_objid; //Connector Object ID or Misc Object ID
790 uint16_t disp_recordoffset;
791 uint16_t encoderobjid; //first encoder closer to the connector, could be either an external or intenal encoder
792 uint16_t extencoderobjid; //2nd encoder after the first encoder, from the connector point of view;
793 uint16_t encoder_recordoffset;
794 uint16_t extencoder_recordoffset;
795 uint16_t device_tag; //a supported device vector, each display path starts with this.the paths are enumerated in the way of priority, a path appears first
796 uint8_t priority_id;
797 uint8_t reserved;
798};
799
800struct display_object_info_table_v1_4
801{
802 struct atom_common_table_header table_header;
803 uint16_t supporteddevices;
804 uint8_t number_of_path;
805 uint8_t reserved;
806 struct atom_display_object_path_v2 display_path[8]; //the real number of this included in the structure is calculated by using the (whole structure size - the header size- number_of_path)/size of atom_display_object_path
807};
808
809
810/*
811 ***************************************************************************
812 Data Table dce_info structure
813 ***************************************************************************
814*/
815struct atom_display_controller_info_v4_1
816{
817 struct atom_common_table_header table_header;
818 uint32_t display_caps;
819 uint32_t bootup_dispclk_10khz;
820 uint16_t dce_refclk_10khz;
821 uint16_t i2c_engine_refclk_10khz;
822 uint16_t dvi_ss_percentage; // in unit of 0.001%
823 uint16_t dvi_ss_rate_10hz;
824 uint16_t hdmi_ss_percentage; // in unit of 0.001%
825 uint16_t hdmi_ss_rate_10hz;
826 uint16_t dp_ss_percentage; // in unit of 0.001%
827 uint16_t dp_ss_rate_10hz;
828 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
829 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
830 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
831 uint8_t ss_reserved;
832 uint8_t hardcode_mode_num; // a hardcode mode number defined in StandardVESA_TimingTable when a CRT or DFP EDID is not available
833 uint8_t reserved1[3];
834 uint16_t dpphy_refclk_10khz;
835 uint16_t reserved2;
836 uint8_t dceip_min_ver;
837 uint8_t dceip_max_ver;
838 uint8_t max_disp_pipe_num;
839 uint8_t max_vbios_active_disp_pipe_num;
840 uint8_t max_ppll_num;
841 uint8_t max_disp_phy_num;
842 uint8_t max_aux_pairs;
843 uint8_t remotedisplayconfig;
844 uint8_t reserved3[8];
845};
846
847
848struct atom_display_controller_info_v4_2
849{
850 struct atom_common_table_header table_header;
851 uint32_t display_caps;
852 uint32_t bootup_dispclk_10khz;
853 uint16_t dce_refclk_10khz;
854 uint16_t i2c_engine_refclk_10khz;
855 uint16_t dvi_ss_percentage; // in unit of 0.001%
856 uint16_t dvi_ss_rate_10hz;
857 uint16_t hdmi_ss_percentage; // in unit of 0.001%
858 uint16_t hdmi_ss_rate_10hz;
859 uint16_t dp_ss_percentage; // in unit of 0.001%
860 uint16_t dp_ss_rate_10hz;
861 uint8_t dvi_ss_mode; // enum of atom_spread_spectrum_mode
862 uint8_t hdmi_ss_mode; // enum of atom_spread_spectrum_mode
863 uint8_t dp_ss_mode; // enum of atom_spread_spectrum_mode
864 uint8_t ss_reserved;
865 uint8_t dfp_hardcode_mode_num; // DFP hardcode mode number defined in StandardVESA_TimingTable when EDID is not available
866 uint8_t dfp_hardcode_refreshrate;// DFP hardcode mode refreshrate defined in StandardVESA_TimingTable when EDID is not available
867 uint8_t vga_hardcode_mode_num; // VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
868 uint8_t vga_hardcode_refreshrate;// VGA hardcode mode number defined in StandardVESA_TimingTable when EDID is not avablable
869 uint16_t dpphy_refclk_10khz;
870 uint16_t reserved2;
871 uint8_t dcnip_min_ver;
872 uint8_t dcnip_max_ver;
873 uint8_t max_disp_pipe_num;
874 uint8_t max_vbios_active_disp_pipe_num;
875 uint8_t max_ppll_num;
876 uint8_t max_disp_phy_num;
877 uint8_t max_aux_pairs;
878 uint8_t remotedisplayconfig;
879 uint8_t reserved3[8];
880};
881
882
883enum dce_info_caps_def
884{
885 // only for VBIOS
886 DCE_INFO_CAPS_FORCE_DISPDEV_CONNECTED =0x02,
887 // only for VBIOS
888 DCE_INFO_CAPS_DISABLE_DFP_DP_HBR2 =0x04,
889 // only for VBIOS
890 DCE_INFO_CAPS_ENABLE_INTERLAC_TIMING =0x08,
891
892};
893
894/*
895 ***************************************************************************
896 Data Table ATOM_EXTERNAL_DISPLAY_CONNECTION_INFO structure
897 ***************************************************************************
898*/
899struct atom_ext_display_path
900{
901 uint16_t device_tag; //A bit vector to show what devices are supported
902 uint16_t device_acpi_enum; //16bit device ACPI id.
903 uint16_t connectorobjid; //A physical connector for displays to plug in, using object connector definitions
904 uint8_t auxddclut_index; //An index into external AUX/DDC channel LUT
905 uint8_t hpdlut_index; //An index into external HPD pin LUT
906 uint16_t ext_encoder_objid; //external encoder object id
907 uint8_t channelmapping; // if ucChannelMapping=0, using default one to one mapping
908 uint8_t chpninvert; // bit vector for up to 8 lanes, =0: P and N is not invert, =1 P and N is inverted
909 uint16_t caps;
910 uint16_t reserved;
911};
912
913//usCaps
914enum ext_display_path_cap_def
915{
916 EXT_DISPLAY_PATH_CAPS__HBR2_DISABLE =0x0001,
917 EXT_DISPLAY_PATH_CAPS__DP_FIXED_VS_EN =0x0002,
918 EXT_DISPLAY_PATH_CAPS__EXT_CHIP_MASK =0x007C,
919};
920
921struct atom_external_display_connection_info
922{
923 struct atom_common_table_header table_header;
924 uint8_t guid[16]; // a GUID is a 16 byte long string
925 struct atom_ext_display_path path[7]; // total of fixed 7 entries.
926 uint8_t checksum; // a simple Checksum of the sum of whole structure equal to 0x0.
927 uint8_t stereopinid; // use for eDP panel
928 uint8_t remotedisplayconfig;
929 uint8_t edptolvdsrxid;
930 uint8_t fixdpvoltageswing; // usCaps[1]=1, this indicate DP_LANE_SET value
931 uint8_t reserved[3]; // for potential expansion
932};
933
934/*
935 ***************************************************************************
936 Data Table integratedsysteminfo structure
937 ***************************************************************************
938*/
939
940struct atom_camera_dphy_timing_param
941{
942 uint8_t profile_id; // SENSOR_PROFILES
943 uint32_t param;
944};
945
946struct atom_camera_dphy_elec_param
947{
948 uint16_t param[3];
949};
950
951struct atom_camera_module_info
952{
953 uint8_t module_id; // 0: Rear, 1: Front right of user, 2: Front left of user
954 uint8_t module_name[8];
955 struct atom_camera_dphy_timing_param timingparam[6]; // Exact number is under estimation and confirmation from sensor vendor
956};
957
958struct atom_camera_flashlight_info
959{
960 uint8_t flashlight_id; // 0: Rear, 1: Front
961 uint8_t name[8];
962};
963
964struct atom_camera_data
965{
966 uint32_t versionCode;
967 struct atom_camera_module_info cameraInfo[3]; // Assuming 3 camera sensors max
968 struct atom_camera_flashlight_info flashInfo; // Assuming 1 flashlight max
969 struct atom_camera_dphy_elec_param dphy_param;
970 uint32_t crc_val; // CRC
971};
972
973
974struct atom_14nm_dpphy_dvihdmi_tuningset
975{
976 uint32_t max_symclk_in10khz;
977 uint8_t encoder_mode; //atom_encode_mode_def, =2: DVI, =3: HDMI mode
978 uint8_t phy_sel; //bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
979 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
980 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
981 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
982 uint8_t tx_driver_fifty_ohms; //COMMON_ZCALCODE_CTRL[21].tx_driver_fifty_ohms
983 uint8_t deemph_sel; //MARGIN_DEEMPH_LANE0.DEEMPH_SEL
984};
985
986struct atom_14nm_dpphy_dp_setting{
987 uint8_t dp_vs_pemph_level; //enum of atom_dp_vs_preemph_def
988 uint16_t margindeemph; //COMMON_MAR_DEEMPH_NOM[7:0]tx_margin_nom [15:8]deemph_gen1_nom
989 uint8_t deemph_6db_4; //COMMON_SELDEEMPH60[31:24]deemph_6db_4
990 uint8_t boostadj; //CMD_BUS_GLOBAL_FOR_TX_LANE0 [19:16]tx_boost_adj [20]tx_boost_en [23:22]tx_binary_ron_code_offset
991};
992
993struct atom_14nm_dpphy_dp_tuningset{
994 uint8_t phy_sel; // bit vector of phy, bit0= phya, bit1=phyb, ....bit5 = phyf
995 uint8_t version;
996 uint16_t table_size; // size of atom_14nm_dpphy_dp_tuningset
997 uint16_t reserved;
998 struct atom_14nm_dpphy_dp_setting dptuning[10];
999};
1000
1001struct atom_14nm_dig_transmitter_info_header_v4_0{
1002 struct atom_common_table_header table_header;
1003 uint16_t pcie_phy_tmds_hdmi_macro_settings_offset; // offset of PCIEPhyTMDSHDMIMacroSettingsTbl
1004 uint16_t uniphy_vs_emph_lookup_table_offset; // offset of UniphyVSEmphLookUpTbl
1005 uint16_t uniphy_xbar_settings_table_offset; // offset of UniphyXbarSettingsTbl
1006};
1007
1008struct atom_14nm_combphy_tmds_vs_set
1009{
1010 uint8_t sym_clk;
1011 uint8_t dig_mode;
1012 uint8_t phy_sel;
1013 uint16_t common_mar_deemph_nom__margin_deemph_val;
1014 uint8_t common_seldeemph60__deemph_6db_4_val;
1015 uint8_t cmd_bus_global_for_tx_lane0__boostadj_val ;
1016 uint8_t common_zcalcode_ctrl__tx_driver_fifty_ohms_val;
1017 uint8_t margin_deemph_lane0__deemph_sel_val;
1018};
1019
Harry Wentlande719d512017-08-21 15:43:32 -0400[diff] [blame]1020struct atom_i2c_reg_info {
1021 uint8_t ucI2cRegIndex;
1022 uint8_t ucI2cRegVal;
1023};
1024
1025struct atom_hdmi_retimer_redriver_set {
1026 uint8_t HdmiSlvAddr;
1027 uint8_t HdmiRegNum;
1028 uint8_t Hdmi6GRegNum;
1029 struct atom_i2c_reg_info HdmiRegSetting[9]; //For non 6G Hz use
1030 struct atom_i2c_reg_info Hdmi6GhzRegSetting[3]; //For 6G Hz use.
1031};
1032
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1033struct atom_integrated_system_info_v1_11
1034{
1035 struct atom_common_table_header table_header;
1036 uint32_t vbios_misc; //enum of atom_system_vbiosmisc_def
1037 uint32_t gpucapinfo; //enum of atom_system_gpucapinf_def
1038 uint32_t system_config;
1039 uint32_t cpucapinfo;
1040 uint16_t gpuclk_ss_percentage; //unit of 0.001%, 1000 mean 1%
1041 uint16_t gpuclk_ss_type;
1042 uint16_t lvds_ss_percentage; //unit of 0.001%, 1000 mean 1%
1043 uint16_t lvds_ss_rate_10hz;
1044 uint16_t hdmi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1045 uint16_t hdmi_ss_rate_10hz;
1046 uint16_t dvi_ss_percentage; //unit of 0.001%, 1000 mean 1%
1047 uint16_t dvi_ss_rate_10hz;
1048 uint16_t dpphy_override; // bit vector, enum of atom_sysinfo_dpphy_override_def
1049 uint16_t lvds_misc; // enum of atom_sys_info_lvds_misc_def
1050 uint16_t backlight_pwm_hz; // pwm frequency in hz
1051 uint8_t memorytype; // enum of atom_sys_mem_type
1052 uint8_t umachannelnumber; // number of memory channels
1053 uint8_t pwr_on_digon_to_de; /* all pwr sequence numbers below are in uint of 4ms */
1054 uint8_t pwr_on_de_to_vary_bl;
1055 uint8_t pwr_down_vary_bloff_to_de;
1056 uint8_t pwr_down_de_to_digoff;
1057 uint8_t pwr_off_delay;
1058 uint8_t pwr_on_vary_bl_to_blon;
1059 uint8_t pwr_down_bloff_to_vary_bloff;
1060 uint8_t min_allowed_bl_level;
1061 struct atom_external_display_connection_info extdispconninfo;
1062 struct atom_14nm_dpphy_dvihdmi_tuningset dvi_tuningset;
1063 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi_tuningset;
1064 struct atom_14nm_dpphy_dvihdmi_tuningset hdmi6g_tuningset;
1065 struct atom_14nm_dpphy_dp_tuningset dp_tuningset;
1066 struct atom_14nm_dpphy_dp_tuningset dp_hbr3_tuningset;
1067 struct atom_camera_data camera_info;
Harry Wentlande719d512017-08-21 15:43:32 -0400[diff] [blame]1068 struct atom_hdmi_retimer_redriver_set dp0_retimer_set; //for DP0
1069 struct atom_hdmi_retimer_redriver_set dp1_retimer_set; //for DP1
1070 struct atom_hdmi_retimer_redriver_set dp2_retimer_set; //for DP2
1071 struct atom_hdmi_retimer_redriver_set dp3_retimer_set; //for DP3
1072 uint32_t reserved[108];
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1073};
1074
1075
1076// system_config
1077enum atom_system_vbiosmisc_def{
1078 INTEGRATED_SYSTEM_INFO__GET_EDID_CALLBACK_FUNC_SUPPORT = 0x01,
1079};
1080
1081
1082// gpucapinfo
1083enum atom_system_gpucapinf_def{
1084 SYS_INFO_GPUCAPS__ENABEL_DFS_BYPASS = 0x10,
1085};
1086
1087//dpphy_override
1088enum atom_sysinfo_dpphy_override_def{
1089 ATOM_ENABLE_DVI_TUNINGSET = 0x01,
1090 ATOM_ENABLE_HDMI_TUNINGSET = 0x02,
1091 ATOM_ENABLE_HDMI6G_TUNINGSET = 0x04,
1092 ATOM_ENABLE_DP_TUNINGSET = 0x08,
1093 ATOM_ENABLE_DP_HBR3_TUNINGSET = 0x10,
1094};
1095
1096//lvds_misc
1097enum atom_sys_info_lvds_misc_def
1098{
1099 SYS_INFO_LVDS_MISC_888_FPDI_MODE =0x01,
1100 SYS_INFO_LVDS_MISC_888_BPC_MODE =0x04,
1101 SYS_INFO_LVDS_MISC_OVERRIDE_EN =0x08,
1102};
1103
1104
1105//memorytype DMI Type 17 offset 12h - Memory Type
1106enum atom_dmi_t17_mem_type_def{
1107 OtherMemType = 0x01, ///< Assign 01 to Other
1108 UnknownMemType, ///< Assign 02 to Unknown
1109 DramMemType, ///< Assign 03 to DRAM
1110 EdramMemType, ///< Assign 04 to EDRAM
1111 VramMemType, ///< Assign 05 to VRAM
1112 SramMemType, ///< Assign 06 to SRAM
1113 RamMemType, ///< Assign 07 to RAM
1114 RomMemType, ///< Assign 08 to ROM
1115 FlashMemType, ///< Assign 09 to Flash
1116 EepromMemType, ///< Assign 10 to EEPROM
1117 FepromMemType, ///< Assign 11 to FEPROM
1118 EpromMemType, ///< Assign 12 to EPROM
1119 CdramMemType, ///< Assign 13 to CDRAM
1120 ThreeDramMemType, ///< Assign 14 to 3DRAM
1121 SdramMemType, ///< Assign 15 to SDRAM
1122 SgramMemType, ///< Assign 16 to SGRAM
1123 RdramMemType, ///< Assign 17 to RDRAM
1124 DdrMemType, ///< Assign 18 to DDR
1125 Ddr2MemType, ///< Assign 19 to DDR2
1126 Ddr2FbdimmMemType, ///< Assign 20 to DDR2 FB-DIMM
1127 Ddr3MemType = 0x18, ///< Assign 24 to DDR3
1128 Fbd2MemType, ///< Assign 25 to FBD2
1129 Ddr4MemType, ///< Assign 26 to DDR4
1130 LpDdrMemType, ///< Assign 27 to LPDDR
1131 LpDdr2MemType, ///< Assign 28 to LPDDR2
1132 LpDdr3MemType, ///< Assign 29 to LPDDR3
1133 LpDdr4MemType, ///< Assign 30 to LPDDR4
1134};
1135
1136
1137// this Table is used starting from NL/AM, used by SBIOS and pass the IntegratedSystemInfoTable/PowerPlayInfoTable/SystemCameraInfoTable
1138struct atom_fusion_system_info_v4
1139{
1140 struct atom_integrated_system_info_v1_11 sysinfo; // refer to ATOM_INTEGRATED_SYSTEM_INFO_V1_8 definition
1141 uint32_t powerplayinfo[256]; // Reserve 1024 bytes space for PowerPlayInfoTable
1142};
1143
1144
1145/*
1146 ***************************************************************************
1147 Data Table gfx_info structure
1148 ***************************************************************************
1149*/
1150
1151struct atom_gfx_info_v2_2
1152{
1153 struct atom_common_table_header table_header;
1154 uint8_t gfxip_min_ver;
1155 uint8_t gfxip_max_ver;
1156 uint8_t max_shader_engines;
1157 uint8_t max_tile_pipes;
1158 uint8_t max_cu_per_sh;
1159 uint8_t max_sh_per_se;
1160 uint8_t max_backends_per_se;
1161 uint8_t max_texture_channel_caches;
1162 uint32_t regaddr_cp_dma_src_addr;
1163 uint32_t regaddr_cp_dma_src_addr_hi;
1164 uint32_t regaddr_cp_dma_dst_addr;
1165 uint32_t regaddr_cp_dma_dst_addr_hi;
1166 uint32_t regaddr_cp_dma_command;
1167 uint32_t regaddr_cp_status;
1168 uint32_t regaddr_rlc_gpu_clock_32;
1169 uint32_t rlc_gpu_timer_refclk;
1170};
1171
1172
1173
1174/*
1175 ***************************************************************************
1176 Data Table smu_info structure
1177 ***************************************************************************
1178*/
1179struct atom_smu_info_v3_1
1180{
1181 struct atom_common_table_header table_header;
1182 uint8_t smuip_min_ver;
1183 uint8_t smuip_max_ver;
1184 uint8_t smu_rsd1;
1185 uint8_t gpuclk_ss_mode; // enum of atom_spread_spectrum_mode
1186 uint16_t sclk_ss_percentage;
1187 uint16_t sclk_ss_rate_10hz;
1188 uint16_t gpuclk_ss_percentage; // in unit of 0.001%
1189 uint16_t gpuclk_ss_rate_10hz;
1190 uint32_t core_refclk_10khz;
1191 uint8_t ac_dc_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for AC/DC switching, =0xff means invalid
1192 uint8_t ac_dc_polarity; // GPIO polarity for AC/DC switching
1193 uint8_t vr0hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR0 HOT event, =0xff means invalid
1194 uint8_t vr0hot_polarity; // GPIO polarity for VR0 HOT event
1195 uint8_t vr1hot_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for VR1 HOT event , =0xff means invalid
1196 uint8_t vr1hot_polarity; // GPIO polarity for VR1 HOT event
1197 uint8_t fw_ctf_gpio_bit; // GPIO bit shift in SMU_GPIOPAD_A configured for CTF, =0xff means invalid
1198 uint8_t fw_ctf_polarity; // GPIO polarity for CTF
1199};
1200
Evan Quanf3f88642017-12-25 10:13:31 +0800[diff] [blame]1201/*
1202 ***************************************************************************
1203 Data Table smc_dpm_info structure
1204 ***************************************************************************
1205 */
1206struct atom_smc_dpm_info_v4_1
1207{
1208 struct atom_common_table_header table_header;
1209 uint8_t liquid1_i2c_address;
1210 uint8_t liquid2_i2c_address;
1211 uint8_t vr_i2c_address;
1212 uint8_t plx_i2c_address;
1213
1214 uint8_t liquid_i2c_linescl;
1215 uint8_t liquid_i2c_linesda;
1216 uint8_t vr_i2c_linescl;
1217 uint8_t vr_i2c_linesda;
1218
1219 uint8_t plx_i2c_linescl;
1220 uint8_t plx_i2c_linesda;
1221 uint8_t vrsensorpresent;
1222 uint8_t liquidsensorpresent;
1223
1224 uint16_t maxvoltagestepgfx;
1225 uint16_t maxvoltagestepsoc;
1226
1227 uint8_t vddgfxvrmapping;
1228 uint8_t vddsocvrmapping;
1229 uint8_t vddmem0vrmapping;
1230 uint8_t vddmem1vrmapping;
1231
1232 uint8_t gfxulvphasesheddingmask;
1233 uint8_t soculvphasesheddingmask;
1234 uint8_t padding8_v[2];
1235
1236 uint16_t gfxmaxcurrent;
1237 uint8_t gfxoffset;
1238 uint8_t padding_telemetrygfx;
1239
1240 uint16_t socmaxcurrent;
1241 uint8_t socoffset;
1242 uint8_t padding_telemetrysoc;
1243
1244 uint16_t mem0maxcurrent;
1245 uint8_t mem0offset;
1246 uint8_t padding_telemetrymem0;
1247
1248 uint16_t mem1maxcurrent;
1249 uint8_t mem1offset;
1250 uint8_t padding_telemetrymem1;
1251
1252 uint8_t acdcgpio;
1253 uint8_t acdcpolarity;
1254 uint8_t vr0hotgpio;
1255 uint8_t vr0hotpolarity;
1256
1257 uint8_t vr1hotgpio;
1258 uint8_t vr1hotpolarity;
1259 uint8_t padding1;
1260 uint8_t padding2;
1261
1262 uint8_t ledpin0;
1263 uint8_t ledpin1;
1264 uint8_t ledpin2;
1265 uint8_t padding8_4;
1266
Kenneth Feng5d415352018-03-28 17:58:03 +0800[diff] [blame]1267 uint8_t pllgfxclkspreadenabled;
1268 uint8_t pllgfxclkspreadpercent;
1269 uint16_t pllgfxclkspreadfreq;
Evan Quanf3f88642017-12-25 10:13:31 +0800[diff] [blame]1270
1271 uint8_t uclkspreadenabled;
1272 uint8_t uclkspreadpercent;
1273 uint16_t uclkspreadfreq;
1274
1275 uint8_t socclkspreadenabled;
1276 uint8_t socclkspreadpercent;
1277 uint16_t socclkspreadfreq;
1278
Kenneth Feng5d415352018-03-28 17:58:03 +0800[diff] [blame]1279 uint8_t acggfxclkspreadenabled;
1280 uint8_t acggfxclkspreadpercent;
1281 uint16_t acggfxclkspreadfreq;
1282
1283 uint32_t boardreserved[10];
Evan Quanf3f88642017-12-25 10:13:31 +0800[diff] [blame]1284};
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1285
1286
1287/*
1288 ***************************************************************************
1289 Data Table asic_profiling_info structure
1290 ***************************************************************************
1291*/
1292struct atom_asic_profiling_info_v4_1
1293{
1294 struct atom_common_table_header table_header;
1295 uint32_t maxvddc;
1296 uint32_t minvddc;
1297 uint32_t avfs_meannsigma_acontant0;
1298 uint32_t avfs_meannsigma_acontant1;
1299 uint32_t avfs_meannsigma_acontant2;
1300 uint16_t avfs_meannsigma_dc_tol_sigma;
1301 uint16_t avfs_meannsigma_platform_mean;
1302 uint16_t avfs_meannsigma_platform_sigma;
1303 uint32_t gb_vdroop_table_cksoff_a0;
1304 uint32_t gb_vdroop_table_cksoff_a1;
1305 uint32_t gb_vdroop_table_cksoff_a2;
1306 uint32_t gb_vdroop_table_ckson_a0;
1307 uint32_t gb_vdroop_table_ckson_a1;
1308 uint32_t gb_vdroop_table_ckson_a2;
1309 uint32_t avfsgb_fuse_table_cksoff_m1;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1310 uint32_t avfsgb_fuse_table_cksoff_m2;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1311 uint32_t avfsgb_fuse_table_cksoff_b;
1312 uint32_t avfsgb_fuse_table_ckson_m1;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1313 uint32_t avfsgb_fuse_table_ckson_m2;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1314 uint32_t avfsgb_fuse_table_ckson_b;
1315 uint16_t max_voltage_0_25mv;
1316 uint8_t enable_gb_vdroop_table_cksoff;
1317 uint8_t enable_gb_vdroop_table_ckson;
1318 uint8_t enable_gb_fuse_table_cksoff;
1319 uint8_t enable_gb_fuse_table_ckson;
1320 uint16_t psm_age_comfactor;
1321 uint8_t enable_apply_avfs_cksoff_voltage;
1322 uint8_t reserved;
1323 uint32_t dispclk2gfxclk_a;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1324 uint32_t dispclk2gfxclk_b;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1325 uint32_t dispclk2gfxclk_c;
1326 uint32_t pixclk2gfxclk_a;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1327 uint32_t pixclk2gfxclk_b;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1328 uint32_t pixclk2gfxclk_c;
1329 uint32_t dcefclk2gfxclk_a;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1330 uint32_t dcefclk2gfxclk_b;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1331 uint32_t dcefclk2gfxclk_c;
1332 uint32_t phyclk2gfxclk_a;
Rex Zhu040cd2d2017-05-31 19:29:53 +0800[diff] [blame]1333 uint32_t phyclk2gfxclk_b;
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1334 uint32_t phyclk2gfxclk_c;
1335};
1336
Rex Zhub7437502017-06-24 16:45:58 +0800[diff] [blame]1337struct atom_asic_profiling_info_v4_2 {
1338 struct atom_common_table_header table_header;
1339 uint32_t maxvddc;
1340 uint32_t minvddc;
1341 uint32_t avfs_meannsigma_acontant0;
1342 uint32_t avfs_meannsigma_acontant1;
1343 uint32_t avfs_meannsigma_acontant2;
1344 uint16_t avfs_meannsigma_dc_tol_sigma;
1345 uint16_t avfs_meannsigma_platform_mean;
1346 uint16_t avfs_meannsigma_platform_sigma;
1347 uint32_t gb_vdroop_table_cksoff_a0;
1348 uint32_t gb_vdroop_table_cksoff_a1;
1349 uint32_t gb_vdroop_table_cksoff_a2;
1350 uint32_t gb_vdroop_table_ckson_a0;
1351 uint32_t gb_vdroop_table_ckson_a1;
1352 uint32_t gb_vdroop_table_ckson_a2;
1353 uint32_t avfsgb_fuse_table_cksoff_m1;
1354 uint32_t avfsgb_fuse_table_cksoff_m2;
1355 uint32_t avfsgb_fuse_table_cksoff_b;
1356 uint32_t avfsgb_fuse_table_ckson_m1;
1357 uint32_t avfsgb_fuse_table_ckson_m2;
1358 uint32_t avfsgb_fuse_table_ckson_b;
1359 uint16_t max_voltage_0_25mv;
1360 uint8_t enable_gb_vdroop_table_cksoff;
1361 uint8_t enable_gb_vdroop_table_ckson;
1362 uint8_t enable_gb_fuse_table_cksoff;
1363 uint8_t enable_gb_fuse_table_ckson;
1364 uint16_t psm_age_comfactor;
1365 uint8_t enable_apply_avfs_cksoff_voltage;
1366 uint8_t reserved;
1367 uint32_t dispclk2gfxclk_a;
1368 uint32_t dispclk2gfxclk_b;
1369 uint32_t dispclk2gfxclk_c;
1370 uint32_t pixclk2gfxclk_a;
1371 uint32_t pixclk2gfxclk_b;
1372 uint32_t pixclk2gfxclk_c;
1373 uint32_t dcefclk2gfxclk_a;
1374 uint32_t dcefclk2gfxclk_b;
1375 uint32_t dcefclk2gfxclk_c;
1376 uint32_t phyclk2gfxclk_a;
1377 uint32_t phyclk2gfxclk_b;
1378 uint32_t phyclk2gfxclk_c;
1379 uint32_t acg_gb_vdroop_table_a0;
1380 uint32_t acg_gb_vdroop_table_a1;
1381 uint32_t acg_gb_vdroop_table_a2;
1382 uint32_t acg_avfsgb_fuse_table_m1;
1383 uint32_t acg_avfsgb_fuse_table_m2;
1384 uint32_t acg_avfsgb_fuse_table_b;
1385 uint8_t enable_acg_gb_vdroop_table;
1386 uint8_t enable_acg_gb_fuse_table;
1387 uint32_t acg_dispclk2gfxclk_a;
1388 uint32_t acg_dispclk2gfxclk_b;
1389 uint32_t acg_dispclk2gfxclk_c;
1390 uint32_t acg_pixclk2gfxclk_a;
1391 uint32_t acg_pixclk2gfxclk_b;
1392 uint32_t acg_pixclk2gfxclk_c;
1393 uint32_t acg_dcefclk2gfxclk_a;
1394 uint32_t acg_dcefclk2gfxclk_b;
1395 uint32_t acg_dcefclk2gfxclk_c;
1396 uint32_t acg_phyclk2gfxclk_a;
1397 uint32_t acg_phyclk2gfxclk_b;
1398 uint32_t acg_phyclk2gfxclk_c;
1399};
Alex Deucher1fadf422017-03-02 16:55:42 -0500[diff] [blame]1400
1401/*
1402 ***************************************************************************
1403 Data Table multimedia_info structure
1404 ***************************************************************************
1405*/
1406struct atom_multimedia_info_v2_1
1407{
1408 struct atom_common_table_header table_header;
1409 uint8_t uvdip_min_ver;
1410 uint8_t uvdip_max_ver;
1411 uint8_t vceip_min_ver;
1412 uint8_t vceip_max_ver;
1413 uint16_t uvd_enc_max_input_width_pixels;
1414 uint16_t uvd_enc_max_input_height_pixels;
1415 uint16_t vce_enc_max_input_width_pixels;
1416 uint16_t vce_enc_max_input_height_pixels;
1417 uint32_t uvd_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
1418 uint32_t vce_enc_max_bandwidth; // 16x16 pixels/sec, codec independent
1419};
1420
1421
1422/*
1423 ***************************************************************************
1424 Data Table umc_info structure
1425 ***************************************************************************
1426*/
1427struct atom_umc_info_v3_1
1428{
1429 struct atom_common_table_header table_header;
1430 uint32_t ucode_version;
1431 uint32_t ucode_rom_startaddr;
1432 uint32_t ucode_length;
1433 uint16_t umc_reg_init_offset;
1434 uint16_t customer_ucode_name_offset;
1435 uint16_t mclk_ss_percentage;
1436 uint16_t mclk_ss_rate_10hz;
1437 uint8_t umcip_min_ver;
1438 uint8_t umcip_max_ver;
1439 uint8_t vram_type; //enum of atom_dgpu_vram_type
1440 uint8_t umc_config;
1441 uint32_t mem_refclk_10khz;
1442};
1443
1444
1445/*
1446 ***************************************************************************
1447 Data Table vram_info structure
1448 ***************************************************************************
1449*/
1450struct atom_vram_module_v9
1451{
1452 // Design Specific Values
1453 uint32_t memory_size; // Total memory size in unit of MB for CONFIG_MEMSIZE zeros
1454 uint32_t channel_enable; // for 32 channel ASIC usage
1455 uint32_t umcch_addrcfg;
1456 uint32_t umcch_addrsel;
1457 uint32_t umcch_colsel;
1458 uint16_t vram_module_size; // Size of atom_vram_module_v9
1459 uint8_t ext_memory_id; // Current memory module ID
1460 uint8_t memory_type; // enum of atom_dgpu_vram_type
1461 uint8_t channel_num; // Number of mem. channels supported in this module
1462 uint8_t channel_width; // CHANNEL_16BIT/CHANNEL_32BIT/CHANNEL_64BIT
1463 uint8_t density; // _8Mx32, _16Mx32, _16Mx16, _32Mx16
1464 uint8_t tunningset_id; // MC phy registers set per.
1465 uint8_t vender_rev_id; // [7:4] Revision, [3:0] Vendor code
1466 uint8_t refreshrate; // [1:0]=RefreshFactor (00=8ms, 01=16ms, 10=32ms,11=64ms)
1467 uint16_t vram_rsd2; // reserved
1468 char dram_pnstring[20]; // part number end with '0'.
1469};
1470
1471
1472struct atom_vram_info_header_v2_3
1473{
1474 struct atom_common_table_header table_header;
1475 uint16_t mem_adjust_tbloffset; // offset of atom_umc_init_reg_block structure for memory vendor specific UMC adjust setting
1476 uint16_t mem_clk_patch_tbloffset; // offset of atom_umc_init_reg_block structure for memory clock specific UMC setting
1477 uint16_t mc_adjust_pertile_tbloffset; // offset of atom_umc_init_reg_block structure for Per Byte Offset Preset Settings
1478 uint16_t mc_phyinit_tbloffset; // offset of atom_umc_init_reg_block structure for MC phy init set
1479 uint16_t dram_data_remap_tbloffset; // reserved for now
1480 uint16_t vram_rsd2[3];
1481 uint8_t vram_module_num; // indicate number of VRAM module
1482 uint8_t vram_rsd1[2];
1483 uint8_t mc_phy_tile_num; // indicate the MCD tile number which use in DramDataRemapTbl and usMcAdjustPerTileTblOffset
1484 struct atom_vram_module_v9 vram_module[16]; // just for allocation, real number of blocks is in ucNumOfVRAMModule;
1485};
1486
1487struct atom_umc_register_addr_info{
1488 uint32_t umc_register_addr:24;
1489 uint32_t umc_reg_type_ind:1;
1490 uint32_t umc_reg_rsvd:7;
1491};
1492
1493//atom_umc_register_addr_info.
1494enum atom_umc_register_addr_info_flag{
1495 b3ATOM_UMC_REG_ADD_INFO_INDIRECT_ACCESS =0x01,
1496};
1497
1498union atom_umc_register_addr_info_access
1499{
1500 struct atom_umc_register_addr_info umc_reg_addr;
1501 uint32_t u32umc_reg_addr;
1502};
1503
1504struct atom_umc_reg_setting_id_config{
1505 uint32_t memclockrange:24;
1506 uint32_t mem_blk_id:8;
1507};
1508
1509union atom_umc_reg_setting_id_config_access
1510{
1511 struct atom_umc_reg_setting_id_config umc_id_access;
1512 uint32_t u32umc_id_access;
1513};
1514
1515struct atom_umc_reg_setting_data_block{
1516 union atom_umc_reg_setting_id_config_access block_id;
1517 uint32_t u32umc_reg_data[1];
1518};
1519
1520struct atom_umc_init_reg_block{
1521 uint16_t umc_reg_num;
1522 uint16_t reserved;
1523 union atom_umc_register_addr_info_access umc_reg_list[1]; //for allocation purpose, the real number come from umc_reg_num;
1524 struct atom_umc_reg_setting_data_block umc_reg_setting_list[1];
1525};
1526
1527
1528/*
1529 ***************************************************************************
1530 Data Table voltageobject_info structure
1531 ***************************************************************************
1532*/
1533struct atom_i2c_data_entry
1534{
1535 uint16_t i2c_reg_index; // i2c register address, can be up to 16bit
1536 uint16_t i2c_reg_data; // i2c register data, can be up to 16bit
1537};
1538
1539struct atom_voltage_object_header_v4{
1540 uint8_t voltage_type; //enum atom_voltage_type
1541 uint8_t voltage_mode; //enum atom_voltage_object_mode
1542 uint16_t object_size; //Size of Object
1543};
1544
1545// atom_voltage_object_header_v4.voltage_mode
1546enum atom_voltage_object_mode
1547{
1548 VOLTAGE_OBJ_GPIO_LUT = 0, //VOLTAGE and GPIO Lookup table ->atom_gpio_voltage_object_v4
1549 VOLTAGE_OBJ_VR_I2C_INIT_SEQ = 3, //VOLTAGE REGULATOR INIT sequece through I2C -> atom_i2c_voltage_object_v4
1550 VOLTAGE_OBJ_PHASE_LUT = 4, //Set Vregulator Phase lookup table ->atom_gpio_voltage_object_v4
1551 VOLTAGE_OBJ_SVID2 = 7, //Indicate voltage control by SVID2 ->atom_svid2_voltage_object_v4
1552 VOLTAGE_OBJ_EVV = 8,
1553 VOLTAGE_OBJ_MERGED_POWER = 9,
1554};
1555
1556struct atom_i2c_voltage_object_v4
1557{
1558 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_VR_I2C_INIT_SEQ
1559 uint8_t regulator_id; //Indicate Voltage Regulator Id
1560 uint8_t i2c_id;
1561 uint8_t i2c_slave_addr;
1562 uint8_t i2c_control_offset;
1563 uint8_t i2c_flag; // Bit0: 0 - One byte data; 1 - Two byte data
1564 uint8_t i2c_speed; // =0, use default i2c speed, otherwise use it in unit of kHz.
1565 uint8_t reserved[2];
1566 struct atom_i2c_data_entry i2cdatalut[1]; // end with 0xff
1567};
1568
1569// ATOM_I2C_VOLTAGE_OBJECT_V3.ucVoltageControlFlag
1570enum atom_i2c_voltage_control_flag
1571{
1572 VOLTAGE_DATA_ONE_BYTE = 0,
1573 VOLTAGE_DATA_TWO_BYTE = 1,
1574};
1575
1576
1577struct atom_voltage_gpio_map_lut
1578{
1579 uint32_t voltage_gpio_reg_val; // The Voltage ID which is used to program GPIO register
1580 uint16_t voltage_level_mv; // The corresponding Voltage Value, in mV
1581};
1582
1583struct atom_gpio_voltage_object_v4
1584{
1585 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_GPIO_LUT or VOLTAGE_OBJ_PHASE_LUT
1586 uint8_t gpio_control_id; // default is 0 which indicate control through CG VID mode
1587 uint8_t gpio_entry_num; // indiate the entry numbers of Votlage/Gpio value Look up table
1588 uint8_t phase_delay_us; // phase delay in unit of micro second
1589 uint8_t reserved;
1590 uint32_t gpio_mask_val; // GPIO Mask value
1591 struct atom_voltage_gpio_map_lut voltage_gpio_lut[1];
1592};
1593
1594struct atom_svid2_voltage_object_v4
1595{
1596 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_SVID2
1597 uint8_t loadline_psi1; // bit4:0= loadline setting ( Core Loadline trim and offset trim ), bit5=0:PSI1_L disable =1: PSI1_L enable
1598 uint8_t psi0_l_vid_thresd; // VR PSI0_L VID threshold
1599 uint8_t psi0_enable; //
1600 uint8_t maxvstep;
1601 uint8_t telemetry_offset;
1602 uint8_t telemetry_gain;
1603 uint16_t reserved1;
1604};
1605
1606struct atom_merged_voltage_object_v4
1607{
1608 struct atom_voltage_object_header_v4 header; // voltage mode = VOLTAGE_OBJ_MERGED_POWER
1609 uint8_t merged_powerrail_type; //enum atom_voltage_type
1610 uint8_t reserved[3];
1611};
1612
1613union atom_voltage_object_v4{
1614 struct atom_gpio_voltage_object_v4 gpio_voltage_obj;
1615 struct atom_i2c_voltage_object_v4 i2c_voltage_obj;
1616 struct atom_svid2_voltage_object_v4 svid2_voltage_obj;
1617 struct atom_merged_voltage_object_v4 merged_voltage_obj;
1618};
1619
1620struct atom_voltage_objects_info_v4_1
1621{
1622 struct atom_common_table_header table_header;
1623 union atom_voltage_object_v4 voltage_object[1]; //Info for Voltage control
1624};
1625
1626
1627/*
1628 ***************************************************************************
1629 All Command Function structure definition
1630 ***************************************************************************
1631*/
1632
1633/*
1634 ***************************************************************************
1635 Structures used by asic_init
1636 ***************************************************************************
1637*/
1638
1639struct asic_init_engine_parameters
1640{
1641 uint32_t sclkfreqin10khz:24;
1642 uint32_t engineflag:8; /* enum atom_asic_init_engine_flag */
1643};
1644
1645struct asic_init_mem_parameters
1646{
1647 uint32_t mclkfreqin10khz:24;
1648 uint32_t memflag:8; /* enum atom_asic_init_mem_flag */
1649};
1650
1651struct asic_init_parameters_v2_1
1652{
1653 struct asic_init_engine_parameters engineparam;
1654 struct asic_init_mem_parameters memparam;
1655};
1656
1657struct asic_init_ps_allocation_v2_1
1658{
1659 struct asic_init_parameters_v2_1 param;
1660 uint32_t reserved[16];
1661};
1662
1663
1664enum atom_asic_init_engine_flag
1665{
1666 b3NORMAL_ENGINE_INIT = 0,
1667 b3SRIOV_SKIP_ASIC_INIT = 0x02,
1668 b3SRIOV_LOAD_UCODE = 0x40,
1669};
1670
1671enum atom_asic_init_mem_flag
1672{
1673 b3NORMAL_MEM_INIT = 0,
1674 b3DRAM_SELF_REFRESH_EXIT =0x20,
1675};
1676
1677/*
1678 ***************************************************************************
1679 Structures used by setengineclock
1680 ***************************************************************************
1681*/
1682
1683struct set_engine_clock_parameters_v2_1
1684{
1685 uint32_t sclkfreqin10khz:24;
1686 uint32_t sclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
1687 uint32_t reserved[10];
1688};
1689
1690struct set_engine_clock_ps_allocation_v2_1
1691{
1692 struct set_engine_clock_parameters_v2_1 clockinfo;
1693 uint32_t reserved[10];
1694};
1695
1696
1697enum atom_set_engine_mem_clock_flag
1698{
1699 b3NORMAL_CHANGE_CLOCK = 0,
1700 b3FIRST_TIME_CHANGE_CLOCK = 0x08,
1701 b3STORE_DPM_TRAINGING = 0x40, //Applicable to memory clock change,when set, it store specific DPM mode training result
1702};
1703
1704/*
1705 ***************************************************************************
1706 Structures used by getengineclock
1707 ***************************************************************************
1708*/
1709struct get_engine_clock_parameter
1710{
1711 uint32_t sclk_10khz; // current engine speed in 10KHz unit
1712 uint32_t reserved;
1713};
1714
1715/*
1716 ***************************************************************************
1717 Structures used by setmemoryclock
1718 ***************************************************************************
1719*/
1720struct set_memory_clock_parameters_v2_1
1721{
1722 uint32_t mclkfreqin10khz:24;
1723 uint32_t mclkflag:8; /* enum atom_set_engine_mem_clock_flag, */
1724 uint32_t reserved[10];
1725};
1726
1727struct set_memory_clock_ps_allocation_v2_1
1728{
1729 struct set_memory_clock_parameters_v2_1 clockinfo;
1730 uint32_t reserved[10];
1731};
1732
1733
1734/*
1735 ***************************************************************************
1736 Structures used by getmemoryclock
1737 ***************************************************************************
1738*/
1739struct get_memory_clock_parameter
1740{
1741 uint32_t mclk_10khz; // current engine speed in 10KHz unit
1742 uint32_t reserved;
1743};
1744
1745
1746
1747/*
1748 ***************************************************************************
1749 Structures used by setvoltage
1750 ***************************************************************************
1751*/
1752
1753struct set_voltage_parameters_v1_4
1754{
1755 uint8_t voltagetype; /* enum atom_voltage_type */
1756 uint8_t command; /* Indicate action: Set voltage level, enum atom_set_voltage_command */
1757 uint16_t vlevel_mv; /* real voltage level in unit of mv or Voltage Phase (0, 1, 2, .. ) */
1758};
1759
1760//set_voltage_parameters_v2_1.voltagemode
1761enum atom_set_voltage_command{
1762 ATOM_SET_VOLTAGE = 0,
1763 ATOM_INIT_VOLTAGE_REGULATOR = 3,
1764 ATOM_SET_VOLTAGE_PHASE = 4,
1765 ATOM_GET_LEAKAGE_ID = 8,
1766};
1767
1768struct set_voltage_ps_allocation_v1_4
1769{
1770 struct set_voltage_parameters_v1_4 setvoltageparam;
1771 uint32_t reserved[10];
1772};
1773
1774
1775/*
1776 ***************************************************************************
1777 Structures used by computegpuclockparam
1778 ***************************************************************************
1779*/
1780
1781//ATOM_COMPUTE_CLOCK_FREQ.ulComputeClockFlag
1782enum atom_gpu_clock_type
1783{
1784 COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK =0x00,
1785 COMPUTE_GPUCLK_INPUT_FLAG_GFXCLK =0x01,
1786 COMPUTE_GPUCLK_INPUT_FLAG_UCLK =0x02,
1787};
1788
1789struct compute_gpu_clock_input_parameter_v1_8
1790{
1791 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
1792 uint32_t gpu_clock_type:8; //Input indicate clock type: enum atom_gpu_clock_type
1793 uint32_t reserved[5];
1794};
1795
1796
1797struct compute_gpu_clock_output_parameter_v1_8
1798{
1799 uint32_t gpuclock_10khz:24; //Input= target clock, output = actual clock
1800 uint32_t dfs_did:8; //return parameter: DFS divider which is used to program to register directly
1801 uint32_t pll_fb_mult; //Feedback Multiplier, bit 8:0 int, bit 15:12 post_div, bit 31:16 frac
1802 uint32_t pll_ss_fbsmult; // Spread FB Mult: bit 8:0 int, bit 31:16 frac
1803 uint16_t pll_ss_slew_frac;
1804 uint8_t pll_ss_enable;
1805 uint8_t reserved;
1806 uint32_t reserved1[2];
1807};
1808
1809
1810
1811/*
1812 ***************************************************************************
1813 Structures used by ReadEfuseValue
1814 ***************************************************************************
1815*/
1816
1817struct read_efuse_input_parameters_v3_1
1818{
1819 uint16_t efuse_start_index;
1820 uint8_t reserved;
1821 uint8_t bitslen;
1822};
1823
1824// ReadEfuseValue input/output parameter
1825union read_efuse_value_parameters_v3_1
1826{
1827 struct read_efuse_input_parameters_v3_1 efuse_info;
1828 uint32_t efusevalue;
1829};
1830
1831
1832/*
1833 ***************************************************************************
1834 Structures used by getsmuclockinfo
1835 ***************************************************************************
1836*/
1837struct atom_get_smu_clock_info_parameters_v3_1
1838{
1839 uint8_t syspll_id; // 0= syspll0, 1=syspll1, 2=syspll2
1840 uint8_t clk_id; // atom_smu9_syspll0_clock_id (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
1841 uint8_t command; // enum of atom_get_smu_clock_info_command
1842 uint8_t dfsdid; // =0: get DFS DID from register, >0, give DFS divider, (only valid when command == GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ )
1843};
1844
1845enum atom_get_smu_clock_info_command
1846{
1847 GET_SMU_CLOCK_INFO_V3_1_GET_CLOCK_FREQ = 0,
1848 GET_SMU_CLOCK_INFO_V3_1_GET_PLLVCO_FREQ = 1,
1849 GET_SMU_CLOCK_INFO_V3_1_GET_PLLREFCLK_FREQ = 2,
1850};
1851
1852enum atom_smu9_syspll0_clock_id
1853{
1854 SMU9_SYSPLL0_SMNCLK_ID = 0, // SMNCLK
1855 SMU9_SYSPLL0_SOCCLK_ID = 1, // SOCCLK (FCLK)
1856 SMU9_SYSPLL0_MP0CLK_ID = 2, // MP0CLK
1857 SMU9_SYSPLL0_MP1CLK_ID = 3, // MP1CLK
1858 SMU9_SYSPLL0_LCLK_ID = 4, // LCLK
1859 SMU9_SYSPLL0_DCLK_ID = 5, // DCLK
1860 SMU9_SYSPLL0_VCLK_ID = 6, // VCLK
1861 SMU9_SYSPLL0_ECLK_ID = 7, // ECLK
1862 SMU9_SYSPLL0_DCEFCLK_ID = 8, // DCEFCLK
1863 SMU9_SYSPLL0_DPREFCLK_ID = 10, // DPREFCLK
1864 SMU9_SYSPLL0_DISPCLK_ID = 11, // DISPCLK
1865};
1866
1867struct atom_get_smu_clock_info_output_parameters_v3_1
1868{
1869 union {
1870 uint32_t smu_clock_freq_hz;
1871 uint32_t syspllvcofreq_10khz;
1872 uint32_t sysspllrefclk_10khz;
1873 }atom_smu_outputclkfreq;
1874};
1875
1876
1877
1878/*
1879 ***************************************************************************
1880 Structures used by dynamicmemorysettings
1881 ***************************************************************************
1882*/
1883
1884enum atom_dynamic_memory_setting_command
1885{
1886 COMPUTE_MEMORY_PLL_PARAM = 1,
1887 COMPUTE_ENGINE_PLL_PARAM = 2,
1888 ADJUST_MC_SETTING_PARAM = 3,
1889};
1890
1891/* when command = COMPUTE_MEMORY_PLL_PARAM or ADJUST_MC_SETTING_PARAM */
1892struct dynamic_mclk_settings_parameters_v2_1
1893{
1894 uint32_t mclk_10khz:24; //Input= target mclk
1895 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
1896 uint32_t reserved;
1897};
1898
1899/* when command = COMPUTE_ENGINE_PLL_PARAM */
1900struct dynamic_sclk_settings_parameters_v2_1
1901{
1902 uint32_t sclk_10khz:24; //Input= target mclk
1903 uint32_t command:8; //command enum of atom_dynamic_memory_setting_command
1904 uint32_t mclk_10khz;
1905 uint32_t reserved;
1906};
1907
1908union dynamic_memory_settings_parameters_v2_1
1909{
1910 struct dynamic_mclk_settings_parameters_v2_1 mclk_setting;
1911 struct dynamic_sclk_settings_parameters_v2_1 sclk_setting;
1912};
1913
1914
1915
1916/*
1917 ***************************************************************************
1918 Structures used by memorytraining
1919 ***************************************************************************
1920*/
1921
1922enum atom_umc6_0_ucode_function_call_enum_id
1923{
1924 UMC60_UCODE_FUNC_ID_REINIT = 0,
1925 UMC60_UCODE_FUNC_ID_ENTER_SELFREFRESH = 1,
1926 UMC60_UCODE_FUNC_ID_EXIT_SELFREFRESH = 2,
1927};
1928
1929
1930struct memory_training_parameters_v2_1
1931{
1932 uint8_t ucode_func_id;
1933 uint8_t ucode_reserved[3];
1934 uint32_t reserved[5];
1935};
1936
1937
1938/*
1939 ***************************************************************************
1940 Structures used by setpixelclock
1941 ***************************************************************************
1942*/
1943
1944struct set_pixel_clock_parameter_v1_7
1945{
1946 uint32_t pixclk_100hz; // target the pixel clock to drive the CRTC timing in unit of 100Hz.
1947
1948 uint8_t pll_id; // ATOM_PHY_PLL0/ATOM_PHY_PLL1/ATOM_PPLL0
1949 uint8_t encoderobjid; // ASIC encoder id defined in objectId.h,
1950 // indicate which graphic encoder will be used.
1951 uint8_t encoder_mode; // Encoder mode:
1952 uint8_t miscinfo; // enum atom_set_pixel_clock_v1_7_misc_info
1953 uint8_t crtc_id; // enum of atom_crtc_def
1954 uint8_t deep_color_ratio; // HDMI panel bit depth: enum atom_set_pixel_clock_v1_7_deepcolor_ratio
1955 uint8_t reserved1[2];
1956 uint32_t reserved2;
1957};
1958
1959//ucMiscInfo
1960enum atom_set_pixel_clock_v1_7_misc_info
1961{
1962 PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL = 0x01,
1963 PIXEL_CLOCK_V7_MISC_PROG_PHYPLL = 0x02,
1964 PIXEL_CLOCK_V7_MISC_YUV420_MODE = 0x04,
1965 PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN = 0x08,
1966 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC = 0x30,
1967 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN = 0x00,
1968 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_PCIE = 0x10,
1969 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK = 0x20,
1970 PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_REFPAD = 0x30,
1971 PIXEL_CLOCK_V7_MISC_ATOMIC_UPDATE = 0x40,
1972 PIXEL_CLOCK_V7_MISC_FORCE_SS_DIS = 0x80,
1973};
1974
1975/* deep_color_ratio */
1976enum atom_set_pixel_clock_v1_7_deepcolor_ratio
1977{
1978 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
1979 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
1980 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
1981 PIXEL_CLOCK_V7_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
1982};
1983
1984/*
1985 ***************************************************************************
1986 Structures used by setdceclock
1987 ***************************************************************************
1988*/
1989
1990// SetDCEClock input parameter for DCE11.2( ELM and BF ) and above
1991struct set_dce_clock_parameters_v2_1
1992{
1993 uint32_t dceclk_10khz; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency.
1994 uint8_t dceclktype; // =0: DISPCLK =1: DPREFCLK =2: PIXCLK
1995 uint8_t dceclksrc; // ATOM_PLL0 or ATOM_GCK_DFS or ATOM_FCH_CLK or ATOM_COMBOPHY_PLLx
1996 uint8_t dceclkflag; // Bit [1:0] = PPLL ref clock source ( when ucDCEClkSrc= ATOM_PPLL0 )
1997 uint8_t crtc_id; // ucDisp Pipe Id, ATOM_CRTC0/1/2/..., use only when ucDCEClkType = PIXCLK
1998};
1999
2000//ucDCEClkType
2001enum atom_set_dce_clock_clock_type
2002{
2003 DCE_CLOCK_TYPE_DISPCLK = 0,
2004 DCE_CLOCK_TYPE_DPREFCLK = 1,
2005 DCE_CLOCK_TYPE_PIXELCLK = 2, // used by VBIOS internally, called by SetPixelClock
2006};
2007
2008//ucDCEClkFlag when ucDCEClkType == DPREFCLK
2009enum atom_set_dce_clock_dprefclk_flag
2010{
2011 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_MASK = 0x03,
2012 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENERICA = 0x00,
2013 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_GENLK = 0x01,
2014 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_PCIE = 0x02,
2015 DCE_CLOCK_FLAG_PLL_REFCLK_SRC_XTALIN = 0x03,
2016};
2017
2018//ucDCEClkFlag when ucDCEClkType == PIXCLK
2019enum atom_set_dce_clock_pixclk_flag
2020{
2021 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_MASK = 0x03,
2022 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_DIS = 0x00, //00 - DCCG_DEEP_COLOR_DTO_DISABLE: Disable Deep Color DTO
2023 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_5_4 = 0x01, //01 - DCCG_DEEP_COLOR_DTO_5_4_RATIO: Set Deep Color DTO to 5:4
2024 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_3_2 = 0x02, //02 - DCCG_DEEP_COLOR_DTO_3_2_RATIO: Set Deep Color DTO to 3:2
2025 DCE_CLOCK_FLAG_PCLK_DEEPCOLOR_RATIO_2_1 = 0x03, //03 - DCCG_DEEP_COLOR_DTO_2_1_RATIO: Set Deep Color DTO to 2:1
2026 DCE_CLOCK_FLAG_PIXCLK_YUV420_MODE = 0x04,
2027};
2028
2029struct set_dce_clock_ps_allocation_v2_1
2030{
2031 struct set_dce_clock_parameters_v2_1 param;
2032 uint32_t ulReserved[2];
2033};
2034
2035
2036/****************************************************************************/
2037// Structures used by BlankCRTC
2038/****************************************************************************/
2039struct blank_crtc_parameters
2040{
2041 uint8_t crtc_id; // enum atom_crtc_def
2042 uint8_t blanking; // enum atom_blank_crtc_command
2043 uint16_t reserved;
2044 uint32_t reserved1;
2045};
2046
2047enum atom_blank_crtc_command
2048{
2049 ATOM_BLANKING = 1,
2050 ATOM_BLANKING_OFF = 0,
2051};
2052
2053/****************************************************************************/
2054// Structures used by enablecrtc
2055/****************************************************************************/
2056struct enable_crtc_parameters
2057{
2058 uint8_t crtc_id; // enum atom_crtc_def
2059 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2060 uint8_t padding[2];
2061};
2062
2063
2064/****************************************************************************/
2065// Structure used by EnableDispPowerGating
2066/****************************************************************************/
2067struct enable_disp_power_gating_parameters_v2_1
2068{
2069 uint8_t disp_pipe_id; // ATOM_CRTC1, ATOM_CRTC2, ...
2070 uint8_t enable; // ATOM_ENABLE or ATOM_DISABLE
2071 uint8_t padding[2];
2072};
2073
2074struct enable_disp_power_gating_ps_allocation
2075{
2076 struct enable_disp_power_gating_parameters_v2_1 param;
2077 uint32_t ulReserved[4];
2078};
2079
2080/****************************************************************************/
2081// Structure used in setcrtc_usingdtdtiming
2082/****************************************************************************/
2083struct set_crtc_using_dtd_timing_parameters
2084{
2085 uint16_t h_size;
2086 uint16_t h_blanking_time;
2087 uint16_t v_size;
2088 uint16_t v_blanking_time;
2089 uint16_t h_syncoffset;
2090 uint16_t h_syncwidth;
2091 uint16_t v_syncoffset;
2092 uint16_t v_syncwidth;
2093 uint16_t modemiscinfo;
2094 uint8_t h_border;
2095 uint8_t v_border;
2096 uint8_t crtc_id; // enum atom_crtc_def
2097 uint8_t encoder_mode; // atom_encode_mode_def
2098 uint8_t padding[2];
2099};
2100
2101
2102/****************************************************************************/
2103// Structures used by processi2cchanneltransaction
2104/****************************************************************************/
2105struct process_i2c_channel_transaction_parameters
2106{
2107 uint8_t i2cspeed_khz;
2108 union {
2109 uint8_t regindex;
2110 uint8_t status; /* enum atom_process_i2c_flag */
2111 } regind_status;
2112 uint16_t i2c_data_out;
2113 uint8_t flag; /* enum atom_process_i2c_status */
2114 uint8_t trans_bytes;
2115 uint8_t slave_addr;
2116 uint8_t i2c_id;
2117};
2118
2119//ucFlag
2120enum atom_process_i2c_flag
2121{
2122 HW_I2C_WRITE = 1,
2123 HW_I2C_READ = 0,
2124 I2C_2BYTE_ADDR = 0x02,
2125 HW_I2C_SMBUS_BYTE_WR = 0x04,
2126};
2127
2128//status
2129enum atom_process_i2c_status
2130{
2131 HW_ASSISTED_I2C_STATUS_FAILURE =2,
2132 HW_ASSISTED_I2C_STATUS_SUCCESS =1,
2133};
2134
2135
2136/****************************************************************************/
2137// Structures used by processauxchanneltransaction
2138/****************************************************************************/
2139
2140struct process_aux_channel_transaction_parameters_v1_2
2141{
2142 uint16_t aux_request;
2143 uint16_t dataout;
2144 uint8_t channelid;
2145 union {
2146 uint8_t reply_status;
2147 uint8_t aux_delay;
2148 } aux_status_delay;
2149 uint8_t dataout_len;
2150 uint8_t hpd_id; //=0: HPD1, =1: HPD2, =2: HPD3, =3: HPD4, =4: HPD5, =5: HPD6
2151};
2152
2153
2154/****************************************************************************/
2155// Structures used by selectcrtc_source
2156/****************************************************************************/
2157
2158struct select_crtc_source_parameters_v2_3
2159{
2160 uint8_t crtc_id; // enum atom_crtc_def
2161 uint8_t encoder_id; // enum atom_dig_def
2162 uint8_t encode_mode; // enum atom_encode_mode_def
2163 uint8_t dst_bpc; // enum atom_panel_bit_per_color
2164};
2165
2166
2167/****************************************************************************/
2168// Structures used by digxencodercontrol
2169/****************************************************************************/
2170
2171// ucAction:
2172enum atom_dig_encoder_control_action
2173{
2174 ATOM_ENCODER_CMD_DISABLE_DIG = 0,
2175 ATOM_ENCODER_CMD_ENABLE_DIG = 1,
2176 ATOM_ENCODER_CMD_DP_LINK_TRAINING_START = 0x08,
2177 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1 = 0x09,
2178 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2 = 0x0a,
2179 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3 = 0x13,
2180 ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE = 0x0b,
2181 ATOM_ENCODER_CMD_DP_VIDEO_OFF = 0x0c,
2182 ATOM_ENCODER_CMD_DP_VIDEO_ON = 0x0d,
2183 ATOM_ENCODER_CMD_SETUP_PANEL_MODE = 0x10,
2184 ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN4 = 0x14,
2185 ATOM_ENCODER_CMD_STREAM_SETUP = 0x0F,
2186 ATOM_ENCODER_CMD_LINK_SETUP = 0x11,
2187 ATOM_ENCODER_CMD_ENCODER_BLANK = 0x12,
2188};
2189
2190//define ucPanelMode
2191enum atom_dig_encoder_control_panelmode
2192{
2193 DP_PANEL_MODE_DISABLE = 0x00,
2194 DP_PANEL_MODE_ENABLE_eDP_MODE = 0x01,
2195 DP_PANEL_MODE_ENABLE_LVLINK_MODE = 0x11,
2196};
2197
2198//ucDigId
2199enum atom_dig_encoder_control_v5_digid
2200{
2201 ATOM_ENCODER_CONFIG_V5_DIG0_ENCODER = 0x00,
2202 ATOM_ENCODER_CONFIG_V5_DIG1_ENCODER = 0x01,
2203 ATOM_ENCODER_CONFIG_V5_DIG2_ENCODER = 0x02,
2204 ATOM_ENCODER_CONFIG_V5_DIG3_ENCODER = 0x03,
2205 ATOM_ENCODER_CONFIG_V5_DIG4_ENCODER = 0x04,
2206 ATOM_ENCODER_CONFIG_V5_DIG5_ENCODER = 0x05,
2207 ATOM_ENCODER_CONFIG_V5_DIG6_ENCODER = 0x06,
2208 ATOM_ENCODER_CONFIG_V5_DIG7_ENCODER = 0x07,
2209};
2210
2211struct dig_encoder_stream_setup_parameters_v1_5
2212{
2213 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2214 uint8_t action; // = ATOM_ENOCODER_CMD_STREAM_SETUP
2215 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2216 uint8_t lanenum; // Lane number
2217 uint32_t pclk_10khz; // Pixel Clock in 10Khz
2218 uint8_t bitpercolor;
2219 uint8_t dplinkrate_270mhz;//= DP link rate/270Mhz, =6: 1.62G = 10: 2.7G, =20: 5.4Ghz, =30: 8.1Ghz etc
2220 uint8_t reserved[2];
2221};
2222
2223struct dig_encoder_link_setup_parameters_v1_5
2224{
2225 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2226 uint8_t action; // = ATOM_ENOCODER_CMD_LINK_SETUP
2227 uint8_t digmode; // ATOM_ENCODER_MODE_DP/ATOM_ENCODER_MODE_DVI/ATOM_ENCODER_MODE_HDMI
2228 uint8_t lanenum; // Lane number
2229 uint8_t symclk_10khz; // Symbol Clock in 10Khz
2230 uint8_t hpd_sel;
2231 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2232 uint8_t reserved[2];
2233};
2234
2235struct dp_panel_mode_set_parameters_v1_5
2236{
2237 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2238 uint8_t action; // = ATOM_ENCODER_CMD_DPLINK_SETUP
2239 uint8_t panelmode; // enum atom_dig_encoder_control_panelmode
2240 uint8_t reserved1;
2241 uint32_t reserved2[2];
2242};
2243
2244struct dig_encoder_generic_cmd_parameters_v1_5
2245{
2246 uint8_t digid; // 0~6 map to DIG0~DIG6 enum atom_dig_encoder_control_v5_digid
2247 uint8_t action; // = rest of generic encoder command which does not carry any parameters
2248 uint8_t reserved1[2];
2249 uint32_t reserved2[2];
2250};
2251
2252union dig_encoder_control_parameters_v1_5
2253{
2254 struct dig_encoder_generic_cmd_parameters_v1_5 cmd_param;
2255 struct dig_encoder_stream_setup_parameters_v1_5 stream_param;
2256 struct dig_encoder_link_setup_parameters_v1_5 link_param;
2257 struct dp_panel_mode_set_parameters_v1_5 dppanel_param;
2258};
2259
2260/*
2261 ***************************************************************************
2262 Structures used by dig1transmittercontrol
2263 ***************************************************************************
2264*/
2265struct dig_transmitter_control_parameters_v1_6
2266{
2267 uint8_t phyid; // 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4= UNIPHYE 5=UNIPHYF
2268 uint8_t action; // define as ATOM_TRANSMITER_ACTION_xxx
2269 union {
2270 uint8_t digmode; // enum atom_encode_mode_def
2271 uint8_t dplaneset; // DP voltage swing and pre-emphasis value defined in DPCD DP_LANE_SET, "DP_LANE_SET__xDB_y_zV"
2272 } mode_laneset;
2273 uint8_t lanenum; // Lane number 1, 2, 4, 8
2274 uint32_t symclk_10khz; // Symbol Clock in 10Khz
2275 uint8_t hpdsel; // =1: HPD1, =2: HPD2, .... =6: HPD6, =0: HPD is not assigned
2276 uint8_t digfe_sel; // DIG stream( front-end ) selection, bit0 means DIG0 FE is enable,
2277 uint8_t connobj_id; // Connector Object Id defined in ObjectId.h
2278 uint8_t reserved;
2279 uint32_t reserved1;
2280};
2281
2282struct dig_transmitter_control_ps_allocation_v1_6
2283{
2284 struct dig_transmitter_control_parameters_v1_6 param;
2285 uint32_t reserved[4];
2286};
2287
2288//ucAction
2289enum atom_dig_transmitter_control_action
2290{
2291 ATOM_TRANSMITTER_ACTION_DISABLE = 0,
2292 ATOM_TRANSMITTER_ACTION_ENABLE = 1,
2293 ATOM_TRANSMITTER_ACTION_LCD_BLOFF = 2,
2294 ATOM_TRANSMITTER_ACTION_LCD_BLON = 3,
2295 ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL = 4,
2296 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_START = 5,
2297 ATOM_TRANSMITTER_ACTION_LCD_SELFTEST_STOP = 6,
2298 ATOM_TRANSMITTER_ACTION_INIT = 7,
2299 ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT = 8,
2300 ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT = 9,
2301 ATOM_TRANSMITTER_ACTION_SETUP = 10,
2302 ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH = 11,
2303 ATOM_TRANSMITTER_ACTION_POWER_ON = 12,
2304 ATOM_TRANSMITTER_ACTION_POWER_OFF = 13,
2305};
2306
2307// digfe_sel
2308enum atom_dig_transmitter_control_digfe_sel
2309{
2310 ATOM_TRANMSITTER_V6__DIGA_SEL = 0x01,
2311 ATOM_TRANMSITTER_V6__DIGB_SEL = 0x02,
2312 ATOM_TRANMSITTER_V6__DIGC_SEL = 0x04,
2313 ATOM_TRANMSITTER_V6__DIGD_SEL = 0x08,
2314 ATOM_TRANMSITTER_V6__DIGE_SEL = 0x10,
2315 ATOM_TRANMSITTER_V6__DIGF_SEL = 0x20,
2316 ATOM_TRANMSITTER_V6__DIGG_SEL = 0x40,
2317};
2318
2319
2320//ucHPDSel
2321enum atom_dig_transmitter_control_hpd_sel
2322{
2323 ATOM_TRANSMITTER_V6_NO_HPD_SEL = 0x00,
2324 ATOM_TRANSMITTER_V6_HPD1_SEL = 0x01,
2325 ATOM_TRANSMITTER_V6_HPD2_SEL = 0x02,
2326 ATOM_TRANSMITTER_V6_HPD3_SEL = 0x03,
2327 ATOM_TRANSMITTER_V6_HPD4_SEL = 0x04,
2328 ATOM_TRANSMITTER_V6_HPD5_SEL = 0x05,
2329 ATOM_TRANSMITTER_V6_HPD6_SEL = 0x06,
2330};
2331
2332// ucDPLaneSet
2333enum atom_dig_transmitter_control_dplaneset
2334{
2335 DP_LANE_SET__0DB_0_4V = 0x00,
2336 DP_LANE_SET__0DB_0_6V = 0x01,
2337 DP_LANE_SET__0DB_0_8V = 0x02,
2338 DP_LANE_SET__0DB_1_2V = 0x03,
2339 DP_LANE_SET__3_5DB_0_4V = 0x08,
2340 DP_LANE_SET__3_5DB_0_6V = 0x09,
2341 DP_LANE_SET__3_5DB_0_8V = 0x0a,
2342 DP_LANE_SET__6DB_0_4V = 0x10,
2343 DP_LANE_SET__6DB_0_6V = 0x11,
2344 DP_LANE_SET__9_5DB_0_4V = 0x18,
2345};
2346
2347
2348
2349/****************************************************************************/
2350// Structures used by ExternalEncoderControl V2.4
2351/****************************************************************************/
2352
2353struct external_encoder_control_parameters_v2_4
2354{
2355 uint16_t pixelclock_10khz; // pixel clock in 10Khz, valid when ucAction=SETUP/ENABLE_OUTPUT
2356 uint8_t config; // indicate which encoder, and DP link rate when ucAction = SETUP/ENABLE_OUTPUT
2357 uint8_t action; //
2358 uint8_t encodermode; // encoder mode, only used when ucAction = SETUP/ENABLE_OUTPUT
2359 uint8_t lanenum; // lane number, only used when ucAction = SETUP/ENABLE_OUTPUT
2360 uint8_t bitpercolor; // output bit per color, only valid when ucAction = SETUP/ENABLE_OUTPUT and ucEncodeMode= DP
2361 uint8_t hpd_id;
2362};
2363
2364
2365// ucAction
2366enum external_encoder_control_action_def
2367{
2368 EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT = 0x00,
2369 EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT = 0x01,
2370 EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT = 0x07,
2371 EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP = 0x0f,
2372 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF = 0x10,
2373 EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING = 0x11,
2374 EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION = 0x12,
2375 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP = 0x14,
2376};
2377
2378// ucConfig
2379enum external_encoder_control_v2_4_config_def
2380{
2381 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_MASK = 0x03,
2382 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_1_62GHZ = 0x00,
2383 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ = 0x01,
2384 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ = 0x02,
2385 EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_3_24GHZ = 0x03,
2386 EXTERNAL_ENCODER_CONFIG_V3_ENCODER_SEL_MAKS = 0x70,
2387 EXTERNAL_ENCODER_CONFIG_V3_ENCODER1 = 0x00,
2388 EXTERNAL_ENCODER_CONFIG_V3_ENCODER2 = 0x10,
2389 EXTERNAL_ENCODER_CONFIG_V3_ENCODER3 = 0x20,
2390};
2391
2392struct external_encoder_control_ps_allocation_v2_4
2393{
2394 struct external_encoder_control_parameters_v2_4 sExtEncoder;
2395 uint32_t reserved[2];
2396};
2397
2398
2399/*
2400 ***************************************************************************
2401 AMD ACPI Table
2402
2403 ***************************************************************************
2404*/
2405
2406struct amd_acpi_description_header{
2407 uint32_t signature;
2408 uint32_t tableLength; //Length
2409 uint8_t revision;
2410 uint8_t checksum;
2411 uint8_t oemId[6];
2412 uint8_t oemTableId[8]; //UINT64 OemTableId;
2413 uint32_t oemRevision;
2414 uint32_t creatorId;
2415 uint32_t creatorRevision;
2416};
2417
2418struct uefi_acpi_vfct{
2419 struct amd_acpi_description_header sheader;
2420 uint8_t tableUUID[16]; //0x24
2421 uint32_t vbiosimageoffset; //0x34. Offset to the first GOP_VBIOS_CONTENT block from the beginning of the stucture.
2422 uint32_t lib1Imageoffset; //0x38. Offset to the first GOP_LIB1_CONTENT block from the beginning of the stucture.
2423 uint32_t reserved[4]; //0x3C
2424};
2425
2426struct vfct_image_header{
2427 uint32_t pcibus; //0x4C
2428 uint32_t pcidevice; //0x50
2429 uint32_t pcifunction; //0x54
2430 uint16_t vendorid; //0x58
2431 uint16_t deviceid; //0x5A
2432 uint16_t ssvid; //0x5C
2433 uint16_t ssid; //0x5E
2434 uint32_t revision; //0x60
2435 uint32_t imagelength; //0x64
2436};
2437
2438
2439struct gop_vbios_content {
2440 struct vfct_image_header vbiosheader;
2441 uint8_t vbioscontent[1];
2442};
2443
2444struct gop_lib1_content {
2445 struct vfct_image_header lib1header;
2446 uint8_t lib1content[1];
2447};
2448
2449
2450
2451/*
2452 ***************************************************************************
2453 Scratch Register definitions
2454 Each number below indicates which scratch regiser request, Active and
2455 Connect all share the same definitions as display_device_tag defines
2456 ***************************************************************************
2457*/
2458
2459enum scratch_register_def{
2460 ATOM_DEVICE_CONNECT_INFO_DEF = 0,
2461 ATOM_BL_BRI_LEVEL_INFO_DEF = 2,
2462 ATOM_ACTIVE_INFO_DEF = 3,
2463 ATOM_LCD_INFO_DEF = 4,
2464 ATOM_DEVICE_REQ_INFO_DEF = 5,
2465 ATOM_ACC_CHANGE_INFO_DEF = 6,
2466 ATOM_PRE_OS_MODE_INFO_DEF = 7,
2467 ATOM_PRE_OS_ASSERTION_DEF = 8, //For GOP to record a 32bit assertion code, this is enabled by default in prodution GOP drivers.
2468 ATOM_INTERNAL_TIMER_INFO_DEF = 10,
2469};
2470
2471enum scratch_device_connect_info_bit_def{
2472 ATOM_DISPLAY_LCD1_CONNECT =0x0002,
2473 ATOM_DISPLAY_DFP1_CONNECT =0x0008,
2474 ATOM_DISPLAY_DFP2_CONNECT =0x0080,
2475 ATOM_DISPLAY_DFP3_CONNECT =0x0200,
2476 ATOM_DISPLAY_DFP4_CONNECT =0x0400,
2477 ATOM_DISPLAY_DFP5_CONNECT =0x0800,
2478 ATOM_DISPLAY_DFP6_CONNECT =0x0040,
2479 ATOM_DISPLAY_DFPx_CONNECT =0x0ec8,
2480 ATOM_CONNECT_INFO_DEVICE_MASK =0x0fff,
2481};
2482
2483enum scratch_bl_bri_level_info_bit_def{
2484 ATOM_CURRENT_BL_LEVEL_SHIFT =0x8,
2485#ifndef _H2INC
2486 ATOM_CURRENT_BL_LEVEL_MASK =0x0000ff00,
2487 ATOM_DEVICE_DPMS_STATE =0x00010000,
2488#endif
2489};
2490
2491enum scratch_active_info_bits_def{
2492 ATOM_DISPLAY_LCD1_ACTIVE =0x0002,
2493 ATOM_DISPLAY_DFP1_ACTIVE =0x0008,
2494 ATOM_DISPLAY_DFP2_ACTIVE =0x0080,
2495 ATOM_DISPLAY_DFP3_ACTIVE =0x0200,
2496 ATOM_DISPLAY_DFP4_ACTIVE =0x0400,
2497 ATOM_DISPLAY_DFP5_ACTIVE =0x0800,
2498 ATOM_DISPLAY_DFP6_ACTIVE =0x0040,
2499 ATOM_ACTIVE_INFO_DEVICE_MASK =0x0fff,
2500};
2501
2502enum scratch_device_req_info_bits_def{
2503 ATOM_DISPLAY_LCD1_REQ =0x0002,
2504 ATOM_DISPLAY_DFP1_REQ =0x0008,
2505 ATOM_DISPLAY_DFP2_REQ =0x0080,
2506 ATOM_DISPLAY_DFP3_REQ =0x0200,
2507 ATOM_DISPLAY_DFP4_REQ =0x0400,
2508 ATOM_DISPLAY_DFP5_REQ =0x0800,
2509 ATOM_DISPLAY_DFP6_REQ =0x0040,
2510 ATOM_REQ_INFO_DEVICE_MASK =0x0fff,
2511};
2512
2513enum scratch_acc_change_info_bitshift_def{
2514 ATOM_ACC_CHANGE_ACC_MODE_SHIFT =4,
2515 ATOM_ACC_CHANGE_LID_STATUS_SHIFT =6,
2516};
2517
2518enum scratch_acc_change_info_bits_def{
2519 ATOM_ACC_CHANGE_ACC_MODE =0x00000010,
2520 ATOM_ACC_CHANGE_LID_STATUS =0x00000040,
2521};
2522
2523enum scratch_pre_os_mode_info_bits_def{
2524 ATOM_PRE_OS_MODE_MASK =0x00000003,
2525 ATOM_PRE_OS_MODE_VGA =0x00000000,
2526 ATOM_PRE_OS_MODE_VESA =0x00000001,
2527 ATOM_PRE_OS_MODE_GOP =0x00000002,
2528 ATOM_PRE_OS_MODE_PIXEL_DEPTH =0x0000000C,
2529 ATOM_PRE_OS_MODE_PIXEL_FORMAT_MASK=0x000000F0,
2530 ATOM_PRE_OS_MODE_8BIT_PAL_EN =0x00000100,
2531 ATOM_ASIC_INIT_COMPLETE =0x00000200,
2532#ifndef _H2INC
2533 ATOM_PRE_OS_MODE_NUMBER_MASK =0xFFFF0000,
2534#endif
2535};
2536
2537
2538
2539/*
2540 ***************************************************************************
2541 ATOM firmware ID header file
2542 !! Please keep it at end of the atomfirmware.h !!
2543 ***************************************************************************
2544*/
2545#include "atomfirmwareid.h"
2546#pragma pack()
2547
2548#endif
2549