Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 1 | /* |
Robert Richter | 6852fd9 | 2008-07-22 21:09:08 +0200 | [diff] [blame] | 2 | * @file op_model_amd.c |
Barry Kasindorf | bd87f1f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 3 | * athlon / K7 / K8 / Family 10h model-specific MSR operations |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 5 | * @remark Copyright 2002-2009 OProfile authors |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * @remark Read the file COPYING |
| 7 | * |
| 8 | * @author John Levon |
| 9 | * @author Philippe Elie |
| 10 | * @author Graydon Hoare |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 11 | * @author Robert Richter <robert.richter@amd.com> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 12 | * @author Barry Kasindorf |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 13 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | |
| 15 | #include <linux/oprofile.h> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 16 | #include <linux/device.h> |
| 17 | #include <linux/pci.h> |
| 18 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 19 | #include <asm/ptrace.h> |
| 20 | #include <asm/msr.h> |
Don Zickus | 3e4ff11 | 2006-06-26 13:57:01 +0200 | [diff] [blame] | 21 | #include <asm/nmi.h> |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 22 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 23 | #include "op_x86_model.h" |
| 24 | #include "op_counter.h" |
| 25 | |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 26 | #define NUM_COUNTERS 4 |
| 27 | #define NUM_CONTROLS 4 |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 28 | #define OP_EVENT_MASK 0x0FFF |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame^] | 29 | #define OP_CTR_OVERFLOW (1ULL<<31) |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 30 | |
| 31 | #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 32 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 33 | static unsigned long reset_value[NUM_COUNTERS]; |
| 34 | |
| 35 | #ifdef CONFIG_OPROFILE_IBS |
| 36 | |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 37 | /* IbsFetchCtl bits/masks */ |
| 38 | #define IBS_FETCH_HIGH_VALID_BIT (1UL << 17) /* bit 49 */ |
| 39 | #define IBS_FETCH_HIGH_ENABLE (1UL << 16) /* bit 48 */ |
| 40 | #define IBS_FETCH_LOW_MAX_CNT_MASK 0x0000FFFFUL /* MaxCnt mask */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 41 | |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 42 | /*IbsOpCtl bits */ |
| 43 | #define IBS_OP_LOW_VALID_BIT (1ULL<<18) /* bit 18 */ |
| 44 | #define IBS_OP_LOW_ENABLE (1ULL<<17) /* bit 17 */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 45 | |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 46 | #define IBS_FETCH_SIZE 6 |
| 47 | #define IBS_OP_SIZE 12 |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 48 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 49 | static int has_ibs; /* AMD Family10h and later */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 50 | |
| 51 | struct op_ibs_config { |
| 52 | unsigned long op_enabled; |
| 53 | unsigned long fetch_enabled; |
| 54 | unsigned long max_cnt_fetch; |
| 55 | unsigned long max_cnt_op; |
| 56 | unsigned long rand_en; |
| 57 | unsigned long dispatched_ops; |
| 58 | }; |
| 59 | |
| 60 | static struct op_ibs_config ibs_config; |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 61 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 62 | #endif |
| 63 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 64 | /* functions for op_amd_spec */ |
Robert Richter | dfa1542 | 2008-07-22 21:08:49 +0200 | [diff] [blame] | 65 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 66 | static void op_amd_fill_in_addresses(struct op_msrs * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 67 | { |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 68 | int i; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 69 | |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 70 | for (i = 0; i < NUM_COUNTERS; i++) { |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 71 | if (reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) |
| 72 | msrs->counters[i].addr = MSR_K7_PERFCTR0 + i; |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 73 | else |
| 74 | msrs->counters[i].addr = 0; |
| 75 | } |
| 76 | |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 77 | for (i = 0; i < NUM_CONTROLS; i++) { |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 78 | if (reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) |
| 79 | msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 80 | else |
| 81 | msrs->controls[i].addr = 0; |
| 82 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 83 | } |
| 84 | |
Robert Richter | ef8828d | 2009-05-25 19:31:44 +0200 | [diff] [blame] | 85 | static void op_amd_setup_ctrs(struct op_x86_model_spec const *model, |
| 86 | struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 87 | { |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 88 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 89 | int i; |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 90 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 91 | /* clear all counters */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 92 | for (i = 0 ; i < NUM_CONTROLS; ++i) { |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 93 | if (unlikely(!CTRL_IS_RESERVED(msrs, i))) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 94 | continue; |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 95 | rdmsrl(msrs->controls[i].addr, val); |
| 96 | val &= model->reserved; |
| 97 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 98 | } |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 99 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 100 | /* avoid a false detection of ctr overflows in NMI handler */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 101 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 102 | if (unlikely(!CTR_IS_RESERVED(msrs, i))) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 103 | continue; |
Robert Richter | d2731a4 | 2009-05-22 19:47:38 +0200 | [diff] [blame] | 104 | wrmsr(msrs->counters[i].addr, -1, -1); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 105 | } |
| 106 | |
| 107 | /* enable active counters */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 108 | for (i = 0; i < NUM_COUNTERS; ++i) { |
| 109 | if ((counter_config[i].enabled) && (CTR_IS_RESERVED(msrs, i))) { |
| 110 | reset_value[i] = counter_config[i].count; |
Robert Richter | d2731a4 | 2009-05-22 19:47:38 +0200 | [diff] [blame] | 111 | wrmsr(msrs->counters[i].addr, -(unsigned int)counter_config[i].count, -1); |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 112 | rdmsrl(msrs->controls[i].addr, val); |
| 113 | val &= model->reserved; |
| 114 | val |= op_x86_get_ctrl(model, &counter_config[i]); |
| 115 | wrmsrl(msrs->controls[i].addr, val); |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 116 | } else { |
| 117 | reset_value[i] = 0; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 118 | } |
| 119 | } |
| 120 | } |
| 121 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 122 | #ifdef CONFIG_OPROFILE_IBS |
| 123 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 124 | static inline int |
| 125 | op_amd_handle_ibs(struct pt_regs * const regs, |
| 126 | struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 127 | { |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 128 | u32 low, high; |
| 129 | u64 msr; |
| 130 | struct op_entry entry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 131 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 132 | if (!has_ibs) |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 133 | return 1; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 134 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 135 | if (ibs_config.fetch_enabled) { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 136 | rdmsr(MSR_AMD64_IBSFETCHCTL, low, high); |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 137 | if (high & IBS_FETCH_HIGH_VALID_BIT) { |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 138 | rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 139 | oprofile_write_reserve(&entry, regs, msr, |
| 140 | IBS_FETCH_CODE, IBS_FETCH_SIZE); |
| 141 | oprofile_add_data(&entry, (u32)msr); |
| 142 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
| 143 | oprofile_add_data(&entry, low); |
| 144 | oprofile_add_data(&entry, high); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 145 | rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 146 | oprofile_add_data(&entry, (u32)msr); |
| 147 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
| 148 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 149 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 150 | /* reenable the IRQ */ |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 151 | high &= ~IBS_FETCH_HIGH_VALID_BIT; |
| 152 | high |= IBS_FETCH_HIGH_ENABLE; |
| 153 | low &= IBS_FETCH_LOW_MAX_CNT_MASK; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 154 | wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); |
| 155 | } |
| 156 | } |
| 157 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 158 | if (ibs_config.op_enabled) { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 159 | rdmsr(MSR_AMD64_IBSOPCTL, low, high); |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 160 | if (low & IBS_OP_LOW_VALID_BIT) { |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 161 | rdmsrl(MSR_AMD64_IBSOPRIP, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 162 | oprofile_write_reserve(&entry, regs, msr, |
| 163 | IBS_OP_CODE, IBS_OP_SIZE); |
| 164 | oprofile_add_data(&entry, (u32)msr); |
| 165 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 166 | rdmsrl(MSR_AMD64_IBSOPDATA, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 167 | oprofile_add_data(&entry, (u32)msr); |
| 168 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 169 | rdmsrl(MSR_AMD64_IBSOPDATA2, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 170 | oprofile_add_data(&entry, (u32)msr); |
| 171 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 172 | rdmsrl(MSR_AMD64_IBSOPDATA3, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 173 | oprofile_add_data(&entry, (u32)msr); |
| 174 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 175 | rdmsrl(MSR_AMD64_IBSDCLINAD, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 176 | oprofile_add_data(&entry, (u32)msr); |
| 177 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 178 | rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 179 | oprofile_add_data(&entry, (u32)msr); |
| 180 | oprofile_add_data(&entry, (u32)(msr >> 32)); |
| 181 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 182 | |
| 183 | /* reenable the IRQ */ |
Robert Richter | 543a157 | 2008-07-22 21:09:04 +0200 | [diff] [blame] | 184 | high = 0; |
Robert Richter | 87f0bac | 2008-07-22 21:09:03 +0200 | [diff] [blame] | 185 | low &= ~IBS_OP_LOW_VALID_BIT; |
| 186 | low |= IBS_OP_LOW_ENABLE; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 187 | wrmsr(MSR_AMD64_IBSOPCTL, low, high); |
| 188 | } |
| 189 | } |
| 190 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 191 | return 1; |
| 192 | } |
| 193 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 194 | static inline void op_amd_start_ibs(void) |
| 195 | { |
| 196 | unsigned int low, high; |
| 197 | if (has_ibs && ibs_config.fetch_enabled) { |
| 198 | low = (ibs_config.max_cnt_fetch >> 4) & 0xFFFF; |
| 199 | high = ((ibs_config.rand_en & 0x1) << 25) /* bit 57 */ |
| 200 | + IBS_FETCH_HIGH_ENABLE; |
| 201 | wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); |
| 202 | } |
| 203 | |
| 204 | if (has_ibs && ibs_config.op_enabled) { |
| 205 | low = ((ibs_config.max_cnt_op >> 4) & 0xFFFF) |
| 206 | + ((ibs_config.dispatched_ops & 0x1) << 19) /* bit 19 */ |
| 207 | + IBS_OP_LOW_ENABLE; |
| 208 | high = 0; |
| 209 | wrmsr(MSR_AMD64_IBSOPCTL, low, high); |
| 210 | } |
| 211 | } |
| 212 | |
| 213 | static void op_amd_stop_ibs(void) |
| 214 | { |
| 215 | unsigned int low, high; |
| 216 | if (has_ibs && ibs_config.fetch_enabled) { |
| 217 | /* clear max count and enable */ |
| 218 | low = 0; |
| 219 | high = 0; |
| 220 | wrmsr(MSR_AMD64_IBSFETCHCTL, low, high); |
| 221 | } |
| 222 | |
| 223 | if (has_ibs && ibs_config.op_enabled) { |
| 224 | /* clear max count and enable */ |
| 225 | low = 0; |
| 226 | high = 0; |
| 227 | wrmsr(MSR_AMD64_IBSOPCTL, low, high); |
| 228 | } |
| 229 | } |
| 230 | |
| 231 | #else |
| 232 | |
| 233 | static inline int op_amd_handle_ibs(struct pt_regs * const regs, |
| 234 | struct op_msrs const * const msrs) { } |
| 235 | static inline void op_amd_start_ibs(void) { } |
| 236 | static inline void op_amd_stop_ibs(void) { } |
| 237 | |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 238 | #endif |
| 239 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 240 | static int op_amd_check_ctrs(struct pt_regs * const regs, |
| 241 | struct op_msrs const * const msrs) |
| 242 | { |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame^] | 243 | u64 val; |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 244 | int i; |
| 245 | |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 246 | for (i = 0 ; i < NUM_COUNTERS; ++i) { |
| 247 | if (!reset_value[i]) |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 248 | continue; |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame^] | 249 | rdmsrl(msrs->counters[i].addr, val); |
| 250 | /* bit is clear if overflowed: */ |
| 251 | if (val & OP_CTR_OVERFLOW) |
| 252 | continue; |
| 253 | oprofile_add_sample(regs, i); |
| 254 | wrmsr(msrs->counters[i].addr, -(unsigned int)reset_value[i], -1); |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 255 | } |
| 256 | |
| 257 | op_amd_handle_ibs(regs, msrs); |
| 258 | |
| 259 | /* See op_model_ppro.c */ |
| 260 | return 1; |
| 261 | } |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 262 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 263 | static void op_amd_start(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 264 | { |
| 265 | unsigned int low, high; |
| 266 | int i; |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 267 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
| 268 | if (reset_value[i]) { |
Robert Richter | d2731a4 | 2009-05-22 19:47:38 +0200 | [diff] [blame] | 269 | rdmsr(msrs->controls[i].addr, low, high); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 270 | CTRL_SET_ACTIVE(low); |
Robert Richter | d2731a4 | 2009-05-22 19:47:38 +0200 | [diff] [blame] | 271 | wrmsr(msrs->controls[i].addr, low, high); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 272 | } |
| 273 | } |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 274 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 275 | op_amd_start_ibs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 276 | } |
| 277 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 278 | static void op_amd_stop(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 279 | { |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 280 | unsigned int low, high; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 281 | int i; |
| 282 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 283 | /* |
| 284 | * Subtle: stop on all counters to avoid race with setting our |
| 285 | * pm callback |
| 286 | */ |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 287 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
| 288 | if (!reset_value[i]) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 289 | continue; |
Robert Richter | d2731a4 | 2009-05-22 19:47:38 +0200 | [diff] [blame] | 290 | rdmsr(msrs->controls[i].addr, low, high); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 291 | CTRL_SET_INACTIVE(low); |
Robert Richter | d2731a4 | 2009-05-22 19:47:38 +0200 | [diff] [blame] | 292 | wrmsr(msrs->controls[i].addr, low, high); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 293 | } |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 294 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 295 | op_amd_stop_ibs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 296 | } |
| 297 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 298 | static void op_amd_shutdown(struct op_msrs const * const msrs) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 299 | { |
| 300 | int i; |
| 301 | |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 302 | for (i = 0 ; i < NUM_COUNTERS ; ++i) { |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 303 | if (CTR_IS_RESERVED(msrs, i)) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 304 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); |
| 305 | } |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 306 | for (i = 0 ; i < NUM_CONTROLS ; ++i) { |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 307 | if (CTRL_IS_RESERVED(msrs, i)) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 308 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); |
| 309 | } |
| 310 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 311 | |
Robert Richter | 9fa6812 | 2008-11-24 14:21:03 +0100 | [diff] [blame] | 312 | #ifdef CONFIG_OPROFILE_IBS |
Robert Richter | a4c408a | 2008-07-22 21:09:02 +0200 | [diff] [blame] | 313 | |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 314 | static u8 ibs_eilvt_off; |
| 315 | |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 316 | static inline void apic_init_ibs_nmi_per_cpu(void *arg) |
| 317 | { |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 318 | ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 319 | } |
| 320 | |
| 321 | static inline void apic_clear_ibs_nmi_per_cpu(void *arg) |
| 322 | { |
| 323 | setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1); |
| 324 | } |
| 325 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 326 | static int init_ibs_nmi(void) |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 327 | { |
| 328 | #define IBSCTL_LVTOFFSETVAL (1 << 8) |
| 329 | #define IBSCTL 0x1cc |
| 330 | struct pci_dev *cpu_cfg; |
| 331 | int nodes; |
| 332 | u32 value = 0; |
| 333 | |
| 334 | /* per CPU setup */ |
Robert Richter | ebb535d | 2008-07-22 21:08:59 +0200 | [diff] [blame] | 335 | on_each_cpu(apic_init_ibs_nmi_per_cpu, NULL, 1); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 336 | |
| 337 | nodes = 0; |
| 338 | cpu_cfg = NULL; |
| 339 | do { |
| 340 | cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD, |
| 341 | PCI_DEVICE_ID_AMD_10H_NB_MISC, |
| 342 | cpu_cfg); |
| 343 | if (!cpu_cfg) |
| 344 | break; |
| 345 | ++nodes; |
| 346 | pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off |
| 347 | | IBSCTL_LVTOFFSETVAL); |
| 348 | pci_read_config_dword(cpu_cfg, IBSCTL, &value); |
| 349 | if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) { |
Robert Richter | 83bd924 | 2008-12-15 15:09:50 +0100 | [diff] [blame] | 350 | pci_dev_put(cpu_cfg); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 351 | printk(KERN_DEBUG "Failed to setup IBS LVT offset, " |
| 352 | "IBSCTL = 0x%08x", value); |
| 353 | return 1; |
| 354 | } |
| 355 | } while (1); |
| 356 | |
| 357 | if (!nodes) { |
| 358 | printk(KERN_DEBUG "No CPU node configured for IBS"); |
| 359 | return 1; |
| 360 | } |
| 361 | |
| 362 | #ifdef CONFIG_NUMA |
| 363 | /* Sanity check */ |
| 364 | /* Works only for 64bit with proper numa implementation. */ |
| 365 | if (nodes != num_possible_nodes()) { |
| 366 | printk(KERN_DEBUG "Failed to setup CPU node(s) for IBS, " |
| 367 | "found: %d, expected %d", |
| 368 | nodes, num_possible_nodes()); |
| 369 | return 1; |
| 370 | } |
| 371 | #endif |
| 372 | return 0; |
| 373 | } |
| 374 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 375 | /* uninitialize the APIC for the IBS interrupts if needed */ |
| 376 | static void clear_ibs_nmi(void) |
| 377 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 378 | if (has_ibs) |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 379 | on_each_cpu(apic_clear_ibs_nmi_per_cpu, NULL, 1); |
| 380 | } |
| 381 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 382 | /* initialize the APIC for the IBS interrupts if available */ |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 383 | static void ibs_init(void) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 384 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 385 | has_ibs = boot_cpu_has(X86_FEATURE_IBS); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 386 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 387 | if (!has_ibs) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 388 | return; |
| 389 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 390 | if (init_ibs_nmi()) { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 391 | has_ibs = 0; |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 392 | return; |
| 393 | } |
| 394 | |
| 395 | printk(KERN_INFO "oprofile: AMD IBS detected\n"); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 396 | } |
| 397 | |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 398 | static void ibs_exit(void) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 399 | { |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 400 | if (!has_ibs) |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 401 | return; |
| 402 | |
| 403 | clear_ibs_nmi(); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 404 | } |
| 405 | |
Robert Richter | 25ad291 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 406 | static int (*create_arch_files)(struct super_block *sb, struct dentry *root); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 407 | |
Robert Richter | 25ad291 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 408 | static int setup_ibs_files(struct super_block *sb, struct dentry *root) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 409 | { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 410 | struct dentry *dir; |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 411 | int ret = 0; |
| 412 | |
| 413 | /* architecture specific files */ |
| 414 | if (create_arch_files) |
| 415 | ret = create_arch_files(sb, root); |
| 416 | |
| 417 | if (ret) |
| 418 | return ret; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 419 | |
Robert Richter | fc81be8 | 2008-12-18 00:28:27 +0100 | [diff] [blame] | 420 | if (!has_ibs) |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 421 | return ret; |
| 422 | |
| 423 | /* model specific files */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 424 | |
| 425 | /* setup some reasonable defaults */ |
| 426 | ibs_config.max_cnt_fetch = 250000; |
| 427 | ibs_config.fetch_enabled = 0; |
| 428 | ibs_config.max_cnt_op = 250000; |
| 429 | ibs_config.op_enabled = 0; |
| 430 | ibs_config.dispatched_ops = 1; |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 431 | |
| 432 | dir = oprofilefs_mkdir(sb, root, "ibs_fetch"); |
| 433 | oprofilefs_create_ulong(sb, dir, "enable", |
| 434 | &ibs_config.fetch_enabled); |
| 435 | oprofilefs_create_ulong(sb, dir, "max_count", |
| 436 | &ibs_config.max_cnt_fetch); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 437 | oprofilefs_create_ulong(sb, dir, "rand_enable", |
| 438 | &ibs_config.rand_en); |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 439 | |
Robert Richter | ccd755c | 2008-07-29 16:57:10 +0200 | [diff] [blame] | 440 | dir = oprofilefs_mkdir(sb, root, "ibs_op"); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 441 | oprofilefs_create_ulong(sb, dir, "enable", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 442 | &ibs_config.op_enabled); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 443 | oprofilefs_create_ulong(sb, dir, "max_count", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 444 | &ibs_config.max_cnt_op); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 445 | oprofilefs_create_ulong(sb, dir, "dispatched_ops", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 446 | &ibs_config.dispatched_ops); |
Robert Richter | fc2bd73 | 2008-07-22 21:09:00 +0200 | [diff] [blame] | 447 | |
| 448 | return 0; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 449 | } |
| 450 | |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 451 | static int op_amd_init(struct oprofile_operations *ops) |
| 452 | { |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 453 | ibs_init(); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 454 | create_arch_files = ops->create_files; |
| 455 | ops->create_files = setup_ibs_files; |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 456 | return 0; |
| 457 | } |
| 458 | |
| 459 | static void op_amd_exit(void) |
| 460 | { |
Robert Richter | fe615cb | 2008-11-24 14:58:03 +0100 | [diff] [blame] | 461 | ibs_exit(); |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 462 | } |
| 463 | |
Robert Richter | 9fa6812 | 2008-11-24 14:21:03 +0100 | [diff] [blame] | 464 | #else |
| 465 | |
| 466 | /* no IBS support */ |
| 467 | |
| 468 | static int op_amd_init(struct oprofile_operations *ops) |
| 469 | { |
| 470 | return 0; |
| 471 | } |
| 472 | |
| 473 | static void op_amd_exit(void) {} |
| 474 | |
| 475 | #endif /* CONFIG_OPROFILE_IBS */ |
Robert Richter | a4c408a | 2008-07-22 21:09:02 +0200 | [diff] [blame] | 476 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 477 | struct op_x86_model_spec const op_amd_spec = { |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 478 | .num_counters = NUM_COUNTERS, |
| 479 | .num_controls = NUM_CONTROLS, |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 480 | .reserved = MSR_AMD_EVENTSEL_RESERVED, |
| 481 | .event_mask = OP_EVENT_MASK, |
| 482 | .init = op_amd_init, |
| 483 | .exit = op_amd_exit, |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 484 | .fill_in_addresses = &op_amd_fill_in_addresses, |
| 485 | .setup_ctrs = &op_amd_setup_ctrs, |
| 486 | .check_ctrs = &op_amd_check_ctrs, |
| 487 | .start = &op_amd_start, |
| 488 | .stop = &op_amd_stop, |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 489 | .shutdown = &op_amd_shutdown, |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 490 | }; |